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Commit | Line | Data |
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2d24a3a7 WD |
1 | /* |
2 | * board/mx1ads/mx1ads.c | |
49822e23 | 3 | * |
2d24a3a7 WD |
4 | * (c) Copyright 2004 |
5 | * Techware Information Technology, Inc. | |
6 | * http://www.techware.com.tw/ | |
7 | * | |
8 | * Ming-Len Wu <minglen_wu@techware.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
2d24a3a7 | 26 | #include <common.h> |
b1c0eaac | 27 | #include <netdev.h> |
281e00a3 | 28 | /*#include <mc9328.h>*/ |
86c98882 | 29 | #include <asm/arch/imx-regs.h> |
2d24a3a7 | 30 | |
d87080b7 | 31 | DECLARE_GLOBAL_DATA_PTR; |
2d24a3a7 WD |
32 | |
33 | #define FCLK_SPEED 1 | |
34 | ||
35 | #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ | |
36 | #define M_MDIV 0xC3 | |
37 | #define M_PDIV 0x4 | |
38 | #define M_SDIV 0x1 | |
39 | #elif FCLK_SPEED==1 /* Fout = 202.8MHz */ | |
40 | #define M_MDIV 0xA1 | |
41 | #define M_PDIV 0x3 | |
42 | #define M_SDIV 0x1 | |
43 | #endif | |
44 | ||
45 | #define USB_CLOCK 1 | |
46 | ||
47 | #if USB_CLOCK==0 | |
48 | #define U_M_MDIV 0xA1 | |
49 | #define U_M_PDIV 0x3 | |
50 | #define U_M_SDIV 0x1 | |
51 | #elif USB_CLOCK==1 | |
52 | #define U_M_MDIV 0x48 | |
53 | #define U_M_PDIV 0x3 | |
54 | #define U_M_SDIV 0x2 | |
55 | #endif | |
56 | ||
57 | #if 0 | |
58 | ||
d87080b7 WD |
59 | static inline void delay (unsigned long loops) |
60 | { | |
2d24a3a7 | 61 | __asm__ volatile ("1:\n" |
d87080b7 WD |
62 | "subs %0, %1, #1\n" |
63 | "bne 1b":"=r" (loops):"0" (loops)); | |
2d24a3a7 WD |
64 | } |
65 | ||
49822e23 | 66 | #endif |
2d24a3a7 WD |
67 | |
68 | /* | |
69 | * Miscellaneous platform dependent initialisations | |
70 | */ | |
71 | ||
d87080b7 WD |
72 | void SetAsynchMode (void) |
73 | { | |
74 | __asm__ ("mrc p15,0,r0,c1,c0,0 \n" | |
75 | "mov r2, #0xC0000000 \n" | |
76 | "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n"); | |
2d24a3a7 | 77 | } |
49822e23 | 78 | |
2d24a3a7 WD |
79 | static u32 mc9328sid; |
80 | ||
e845f900 | 81 | int board_early_init_f(void) |
d87080b7 WD |
82 | { |
83 | volatile unsigned int tmp; | |
2d24a3a7 | 84 | |
d87080b7 | 85 | mc9328sid = SIDR; |
2d24a3a7 | 86 | |
d87080b7 | 87 | GPCR = 0x000003AB; /* I/O pad driving strength */ |
2d24a3a7 | 88 | |
53677ef1 WD |
89 | /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ |
90 | /* MX1_CS1L = 0x11110601; */ | |
2d24a3a7 | 91 | |
d87080b7 | 92 | MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ |
2d24a3a7 WD |
93 | |
94 | /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and | |
95 | * BCLK divider to 2 (i.e. BCLK to 48 MHz) | |
96 | */ | |
d87080b7 | 97 | CSCR = 0xAF000403; |
2d24a3a7 | 98 | |
d87080b7 WD |
99 | CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ |
100 | CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ | |
2d24a3a7 WD |
101 | |
102 | /* setup cs4 for cs8900 ethernet */ | |
49822e23 | 103 | |
d87080b7 WD |
104 | CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ |
105 | CS4L = 0x00001501; | |
49822e23 | 106 | |
d87080b7 WD |
107 | GIUS (0) &= 0xFF3FFFFF; |
108 | GPR (0) &= 0xFF3FFFFF; | |
49822e23 | 109 | |
d87080b7 WD |
110 | tmp = *(unsigned int *) (0x1500000C); |
111 | tmp = *(unsigned int *) (0x1500000C); | |
2d24a3a7 | 112 | |
d87080b7 | 113 | SetAsynchMode (); |
2d24a3a7 | 114 | |
d87080b7 WD |
115 | icache_enable (); |
116 | dcache_enable (); | |
2d24a3a7 WD |
117 | |
118 | /* set PERCLKs */ | |
d87080b7 | 119 | PCDR = 0x00000055; /* set PERCLKS */ |
49822e23 WD |
120 | |
121 | /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes | |
122 | * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place | |
2d24a3a7 WD |
123 | * all sources selected as normal interrupt |
124 | */ | |
2d24a3a7 | 125 | |
281e00a3 WD |
126 | /* MX1_INTTYPEH = 0; |
127 | MX1_INTTYPEL = 0; | |
128 | */ | |
2d24a3a7 WD |
129 | return 0; |
130 | } | |
131 | ||
e845f900 FE |
132 | int board_init(void) |
133 | { | |
134 | gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; | |
135 | ||
136 | gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
d87080b7 WD |
141 | int board_late_init (void) |
142 | { | |
143 | ||
144 | setenv ("stdout", "serial"); | |
145 | setenv ("stderr", "serial"); | |
146 | ||
147 | switch (mc9328sid) { | |
148 | case 0x0005901d: | |
149 | printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n", | |
150 | mc9328sid); | |
151 | break; | |
152 | case 0x04d4c01d: | |
153 | printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n", | |
154 | mc9328sid); | |
155 | break; | |
156 | case 0x00d4c01d: | |
157 | printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n", | |
158 | mc9328sid); | |
159 | break; | |
160 | ||
161 | default: | |
162 | printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n", | |
163 | mc9328sid); | |
164 | break; | |
2d24a3a7 | 165 | } |
2d24a3a7 | 166 | return 0; |
49822e23 WD |
167 | } |
168 | ||
e845f900 FE |
169 | int dram_init(void) |
170 | { | |
171 | /* dram_init must store complete ramsize in gd->ram_size */ | |
a55d23cc | 172 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, |
e845f900 FE |
173 | PHYS_SDRAM_1_SIZE); |
174 | return 0; | |
175 | } | |
176 | ||
177 | void dram_init_banksize(void) | |
d87080b7 | 178 | { |
2d24a3a7 | 179 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
d87080b7 | 180 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
2d24a3a7 | 181 | } |
b1c0eaac BW |
182 | |
183 | #ifdef CONFIG_CMD_NET | |
184 | int board_eth_init(bd_t *bis) | |
185 | { | |
186 | int rc = 0; | |
187 | #ifdef CONFIG_CS8900 | |
188 | rc = cs8900_initialize(0, CONFIG_CS8900_BASE); | |
189 | #endif | |
190 | return rc; | |
191 | } | |
192 | #endif |