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2d24a3a7 WD |
1 | /* |
2 | * board/mx1ads/syncflash.c | |
49822e23 | 3 | * |
2d24a3a7 WD |
4 | * (c) Copyright 2004 |
5 | * Techware Information Technology, Inc. | |
6 | * http://www.techware.com.tw/ | |
7 | * | |
8 | * Ming-Len Wu <minglen_wu@techware.com.tw> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
2d24a3a7 WD |
11 | */ |
12 | ||
13 | #include <common.h> | |
281e00a3 WD |
14 | /*#include <mc9328.h>*/ |
15 | #include <asm/arch/imx-regs.h> | |
2d24a3a7 WD |
16 | |
17 | typedef unsigned long * p_u32; | |
18 | ||
19 | /* 4Mx16x2 IAM=0 CSD1 */ | |
20 | ||
6d0f6bcf | 21 | flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
2d24a3a7 WD |
22 | |
23 | /* Following Setting is for CSD1 */ | |
281e00a3 WD |
24 | #define SFCTL 0x00221004 |
25 | #define reg_SFCTL __REG(SFCTL) | |
2d24a3a7 | 26 | |
281e00a3 | 27 | #define SYNCFLASH_A10 (0x00100000) |
2d24a3a7 | 28 | |
281e00a3 | 29 | #define CMD_NORMAL (0x81020300) /* Normal Mode */ |
53677ef1 WD |
30 | #define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ |
31 | #define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ | |
32 | #define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ | |
33 | #define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ | |
281e00a3 | 34 | #define CMD_PROGRAM (CMD_NORMAL + 0x70000000) |
2d24a3a7 | 35 | |
6d0f6bcf | 36 | #define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ |
2d24a3a7 WD |
37 | |
38 | /* LCR Command */ | |
281e00a3 WD |
39 | #define LCR_READSTATUS (0x0001C000) /* 0x70 */ |
40 | #define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ | |
41 | #define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ | |
42 | #define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ | |
43 | #define LCR_SR_CLEAR (0x00014000) /* 0x50 */ | |
2d24a3a7 | 44 | |
53677ef1 | 45 | /* Get Status register */ |
2d24a3a7 | 46 | u32 SF_SR(void) { |
6859ea74 | 47 | u32 tmp; |
2d24a3a7 WD |
48 | |
49 | reg_SFCTL = CMD_PROGRAM; | |
6d0f6bcf | 50 | tmp = __REG(CONFIG_SYS_FLASH_BASE); |
49822e23 | 51 | |
2d24a3a7 WD |
52 | reg_SFCTL = CMD_NORMAL; |
53 | ||
53677ef1 | 54 | reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ |
6859ea74 | 55 | __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR); |
2d24a3a7 WD |
56 | |
57 | return tmp; | |
58 | } | |
59 | ||
53677ef1 | 60 | /* check if SyncFlash is ready */ |
2d24a3a7 WD |
61 | u8 SF_Ready(void) { |
62 | u32 tmp; | |
63 | ||
64 | tmp = SF_SR(); | |
65 | ||
66 | if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { | |
67 | printf ("SyncFlash Error code %08x\n",tmp); | |
68 | }; | |
69 | ||
70 | if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { | |
71 | printf ("SyncFlash Error code %08x\n",tmp); | |
2d24a3a7 WD |
72 | }; |
73 | ||
53677ef1 | 74 | if (tmp == 0x00800080) /* Test Bit 7 of SR */ |
2d24a3a7 WD |
75 | return 1; |
76 | else | |
77 | return 0; | |
78 | } | |
79 | ||
53677ef1 | 80 | /* Issue the precharge all command */ |
2d24a3a7 WD |
81 | void SF_PrechargeAll(void) { |
82 | ||
6859ea74 AG |
83 | /* Set Precharge Command */ |
84 | reg_SFCTL = CMD_PREC; | |
85 | /* Issue Precharge All Command */ | |
86 | __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); | |
2d24a3a7 WD |
87 | } |
88 | ||
89 | /* set SyncFlash to normal mode */ | |
90 | void SF_Normal(void) { | |
91 | ||
92 | SF_PrechargeAll(); | |
49822e23 | 93 | |
2d24a3a7 WD |
94 | reg_SFCTL = CMD_NORMAL; |
95 | } | |
96 | ||
53677ef1 | 97 | /* Erase SyncFlash */ |
2d24a3a7 | 98 | void SF_Erase(u32 RowAddress) { |
2d24a3a7 WD |
99 | |
100 | reg_SFCTL = CMD_NORMAL; | |
6859ea74 | 101 | __REG(RowAddress); |
2d24a3a7 WD |
102 | |
103 | reg_SFCTL = CMD_PREC; | |
6859ea74 | 104 | __REG(RowAddress); |
49822e23 | 105 | |
53677ef1 WD |
106 | reg_SFCTL = CMD_LCR; /* Set LCR mode */ |
107 | __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ | |
49822e23 | 108 | |
53677ef1 WD |
109 | reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ |
110 | __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ | |
2d24a3a7 WD |
111 | |
112 | while(!SF_Ready()); | |
113 | } | |
114 | ||
2d24a3a7 WD |
115 | void SF_NvmodeErase(void) { |
116 | SF_PrechargeAll(); | |
117 | ||
118 | reg_SFCTL = CMD_LCR; /* Set to LCR mode */ | |
6d0f6bcf | 119 | __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ |
49822e23 | 120 | |
53677ef1 | 121 | reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ |
6d0f6bcf | 122 | __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ |
2d24a3a7 WD |
123 | |
124 | while(!SF_Ready()); | |
125 | } | |
126 | ||
127 | void SF_NvmodeWrite(void) { | |
128 | SF_PrechargeAll(); | |
129 | ||
53677ef1 | 130 | reg_SFCTL = CMD_LCR; /* Set to LCR mode */ |
6d0f6bcf | 131 | __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ |
49822e23 | 132 | |
53677ef1 | 133 | reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ |
6d0f6bcf | 134 | __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ |
2d24a3a7 WD |
135 | } |
136 | ||
2d24a3a7 WD |
137 | /****************************************************************************************/ |
138 | ||
139 | ulong flash_init(void) { | |
140 | int i, j; | |
2d24a3a7 WD |
141 | |
142 | /* Turn on CSD1 for negating RESETSF of SyncFLash */ | |
143 | ||
53677ef1 | 144 | reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ |
2d24a3a7 WD |
145 | udelay(200); |
146 | ||
53677ef1 | 147 | reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ |
6859ea74 | 148 | __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ |
2d24a3a7 WD |
149 | |
150 | SF_Normal(); | |
49822e23 | 151 | |
2d24a3a7 WD |
152 | i = 0; |
153 | ||
53677ef1 | 154 | flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; |
49822e23 | 155 | |
53677ef1 | 156 | flash_info[i].size = FLASH_BANK_SIZE; |
6d0f6bcf | 157 | flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; |
2d24a3a7 | 158 | |
6d0f6bcf | 159 | memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); |
2d24a3a7 WD |
160 | |
161 | for (j = 0; j < flash_info[i].sector_count; j++) { | |
6d0f6bcf | 162 | flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000; |
2d24a3a7 | 163 | } |
49822e23 | 164 | |
2d24a3a7 | 165 | flash_protect(FLAG_PROTECT_SET, |
6d0f6bcf JCPV |
166 | CONFIG_SYS_FLASH_BASE, |
167 | CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, | |
2d24a3a7 WD |
168 | &flash_info[0]); |
169 | ||
170 | flash_protect(FLAG_PROTECT_SET, | |
0e8d1586 JCPV |
171 | CONFIG_ENV_ADDR, |
172 | CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, | |
2d24a3a7 WD |
173 | &flash_info[0]); |
174 | ||
175 | return FLASH_BANK_SIZE; | |
176 | } | |
177 | ||
2d24a3a7 WD |
178 | void flash_print_info (flash_info_t *info) { |
179 | ||
180 | int i; | |
181 | ||
182 | switch (info->flash_id & FLASH_VENDMASK) { | |
183 | case (FLASH_MAN_MT & FLASH_VENDMASK): | |
184 | printf("Micron: "); | |
185 | break; | |
186 | default: | |
187 | printf("Unknown Vendor "); | |
188 | break; | |
189 | } | |
49822e23 | 190 | |
2d24a3a7 WD |
191 | switch (info->flash_id & FLASH_TYPEMASK) { |
192 | case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): | |
193 | printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); | |
194 | break; | |
195 | default: | |
196 | printf("Unknown Chip Type\n"); | |
197 | return; | |
198 | break; | |
199 | } | |
200 | ||
201 | printf(" Size: %ld MB in %d Sectors\n", | |
202 | info->size >> 20, info->sector_count); | |
203 | ||
204 | printf(" Sector Start Addresses: "); | |
205 | ||
206 | for (i = 0; i < info->sector_count; i++) { | |
49822e23 | 207 | if ((i % 5) == 0) |
2d24a3a7 WD |
208 | printf ("\n "); |
209 | ||
210 | printf (" %08lX%s", info->start[i], | |
211 | info->protect[i] ? " (RO)" : " "); | |
212 | } | |
49822e23 | 213 | |
2d24a3a7 WD |
214 | printf ("\n"); |
215 | } | |
216 | ||
2d24a3a7 WD |
217 | /*-----------------------------------------------------------------------*/ |
218 | ||
219 | int flash_erase (flash_info_t *info, int s_first, int s_last) { | |
220 | int iflag, cflag, prot, sect; | |
221 | int rc = ERR_OK; | |
222 | ||
223 | /* first look for protection bits */ | |
224 | ||
225 | if (info->flash_id == FLASH_UNKNOWN) | |
226 | return ERR_UNKNOWN_FLASH_TYPE; | |
227 | ||
49822e23 | 228 | if ((s_first < 0) || (s_first > s_last)) |
2d24a3a7 WD |
229 | return ERR_INVAL; |
230 | ||
49822e23 | 231 | if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) |
2d24a3a7 WD |
232 | return ERR_UNKNOWN_FLASH_VENDOR; |
233 | ||
234 | prot = 0; | |
235 | ||
236 | for (sect = s_first; sect <= s_last; ++sect) { | |
49822e23 | 237 | if (info->protect[sect]) |
2d24a3a7 WD |
238 | prot++; |
239 | } | |
49822e23 | 240 | |
2d24a3a7 WD |
241 | if (prot) { |
242 | printf("protected!\n"); | |
243 | return ERR_PROTECTED; | |
244 | } | |
245 | /* | |
246 | * Disable interrupts which might cause a timeout | |
247 | * here. Remember that our exception vectors are | |
248 | * at address 0 in the flash, and we don't want a | |
249 | * (ticker) exception to happen while the flash | |
250 | * chip is in programming mode. | |
251 | */ | |
252 | ||
253 | cflag = icache_status(); | |
254 | icache_disable(); | |
255 | iflag = disable_interrupts(); | |
256 | ||
257 | /* Start erase on unprotected sectors */ | |
258 | for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { | |
49822e23 | 259 | |
2d24a3a7 WD |
260 | printf("Erasing sector %2d ... ", sect); |
261 | ||
262 | /* arm simple, non interrupt dependent timer */ | |
263 | ||
a60d1e5b | 264 | get_timer(0); |
2d24a3a7 WD |
265 | |
266 | SF_NvmodeErase(); | |
267 | SF_NvmodeWrite(); | |
268 | ||
6d0f6bcf | 269 | SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect)); |
2d24a3a7 WD |
270 | SF_Normal(); |
271 | ||
272 | printf("ok.\n"); | |
273 | } | |
274 | ||
275 | if (ctrlc()) | |
276 | printf("User Interrupt!\n"); | |
277 | ||
278 | if (iflag) | |
279 | enable_interrupts(); | |
280 | ||
281 | if (cflag) | |
282 | icache_enable(); | |
283 | ||
284 | return rc; | |
285 | } | |
286 | ||
2d24a3a7 WD |
287 | /*----------------------------------------------------------------------- |
288 | * Copy memory to flash. | |
289 | */ | |
290 | ||
291 | int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { | |
292 | int i; | |
293 | ||
49822e23 | 294 | for(i = 0; i < cnt; i += 4) { |
2d24a3a7 WD |
295 | |
296 | SF_PrechargeAll(); | |
297 | ||
298 | reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ | |
299 | __REG(addr + i) = __REG((u32)src + i); | |
300 | ||
301 | while(!SF_Ready()); | |
302 | } | |
303 | ||
304 | SF_Normal(); | |
49822e23 | 305 | |
2d24a3a7 WD |
306 | return ERR_OK; |
307 | } |