[thirdparty/u-boot.git] / board / nuvoton / arbel_evb / arbel_evb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2022 Nuvoton Technology Corp.
 */

#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/gcr.h>
#include "../common/uart.h"

#define SR_MII_CTRL_SWR_BIT15	15

#define DRAM_512MB_ECC_SIZE	0x1C000000ULL
#define DRAM_512MB_SIZE		0x20000000ULL
#define DRAM_1GB_ECC_SIZE	0x38000000ULL
#define DRAM_1GB_SIZE		0x40000000ULL
#define DRAM_2GB_ECC_SIZE	0x70000000ULL
#define DRAM_2GB_SIZE		0x80000000ULL
#define DRAM_4GB_ECC_SIZE	0xE0000000ULL
#define DRAM_4GB_SIZE		0x100000000ULL

DECLARE_GLOBAL_DATA_PTR;

int board_init(void)
{
	return 0;
}

int dram_init(void)
{
	struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;

	/*
	 * get dram active size value from bootblock.
	 * Value sent using scrpad_03 register.
	 * feature available in bootblock 0.0.6 and above.
	 */

	gd->ram_size = readl(&gcr->scrpad_c);

	if (gd->ram_size == 0)
		gd->ram_size = readl(&gcr->scrpad_b);
	else
		gd->ram_size *= 0x100000ULL;

	debug("ram_size: %llx ", gd->ram_size);

	return 0;
}

int dram_init_banksize(void)
{

	gd->bd->bi_dram[0].start = 0;

	switch (gd->ram_size) {
	case DRAM_512MB_ECC_SIZE:
	case DRAM_512MB_SIZE:
	case DRAM_1GB_ECC_SIZE:
	case DRAM_1GB_SIZE:
	case DRAM_2GB_ECC_SIZE:
	case DRAM_2GB_SIZE:
		gd->bd->bi_dram[0].size = gd->ram_size;
		gd->bd->bi_dram[1].start = 0;
		gd->bd->bi_dram[1].size = 0;
		break;
	case DRAM_4GB_ECC_SIZE:
		gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
		gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
		gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
			(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
		/* use bank0 only */
		gd->ram_size = DRAM_2GB_SIZE;
		break;
	case DRAM_4GB_SIZE:
		gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
		gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
		gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
		/* use bank0 only */
		gd->ram_size = DRAM_2GB_SIZE;
		break;
	default:
		gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
		gd->bd->bi_dram[1].start = 0;
		gd->bd->bi_dram[1].size = 0;
		gd->ram_size = DRAM_1GB_SIZE;
		break;
	}

	return 0;
}

int last_stage_init(void)
{
	board_set_console();

	return 0;
}
Commit	Line	Data
9ca71c9c JL	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (c) 2022 Nuvoton Technology Corp.
	4	*/
	5
	6	#include <common.h>
	7	#include <dm.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/gcr.h>
5a207078	10	#include "../common/uart.h"
9ca71c9c	11
4b7f29ff JL	12	#define SR_MII_CTRL_SWR_BIT15 15
	13
	14	#define DRAM_512MB_ECC_SIZE 0x1C000000ULL
	15	#define DRAM_512MB_SIZE 0x20000000ULL
	16	#define DRAM_1GB_ECC_SIZE 0x38000000ULL
	17	#define DRAM_1GB_SIZE 0x40000000ULL
	18	#define DRAM_2GB_ECC_SIZE 0x70000000ULL
	19	#define DRAM_2GB_SIZE 0x80000000ULL
1b7026f5	20	#define DRAM_4GB_ECC_SIZE 0xE0000000ULL
4b7f29ff JL	21	#define DRAM_4GB_SIZE 0x100000000ULL
4b7f29ff JL	22
9ca71c9c JL	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	int board_init(void)
	26	{
	27	return 0;
	28	}
	29
	30	int dram_init(void)
	31	{
	32	struct npcm_gcr gcr = (struct npcm_gcr )NPCM_GCR_BA;
	33
	34	/*
4b7f29ff JL	35	* get dram active size value from bootblock.
	36	* Value sent using scrpad_03 register.
	37	* feature available in bootblock 0.0.6 and above.
9ca71c9c	38	*/
4b7f29ff JL	39
4b7f29ff JL	40	gd->ram_size = readl(&gcr->scrpad_c);
4b7f29ff	41
1b7026f5	42	if (gd->ram_size == 0)
4b7f29ff	43	gd->ram_size = readl(&gcr->scrpad_b);
1b7026f5	44	else
4b7f29ff	45	gd->ram_size *= 0x100000ULL;
4b7f29ff	46
4b7f29ff JL	47	debug("ram_size: %llx ", gd->ram_size);
4b7f29ff JL	48
1b7026f5 JL	49	return 0;
	50	}
	51
	52	int dram_init_banksize(void)
	53	{
	54
	55	gd->bd->bi_dram[0].start = 0;
	56
4b7f29ff JL	57	switch (gd->ram_size) {
	58	case DRAM_512MB_ECC_SIZE:
	59	case DRAM_512MB_SIZE:
	60	case DRAM_1GB_ECC_SIZE:
	61	case DRAM_1GB_SIZE:
	62	case DRAM_2GB_ECC_SIZE:
	63	case DRAM_2GB_SIZE:
	64	gd->bd->bi_dram[0].size = gd->ram_size;
	65	gd->bd->bi_dram[1].start = 0;
	66	gd->bd->bi_dram[1].size = 0;
	67	break;
	68	case DRAM_4GB_ECC_SIZE:
1b7026f5	69	gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
4b7f29ff	70	gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
1b7026f5 JL	71	gd->bd->bi_dram[1].size = DRAM_2GB_SIZE -
	72	(DRAM_4GB_SIZE - DRAM_4GB_ECC_SIZE);
	73	/* use bank0 only */
	74	gd->ram_size = DRAM_2GB_SIZE;
4b7f29ff JL	75	break;
	76	case DRAM_4GB_SIZE:
	77	gd->bd->bi_dram[0].size = DRAM_2GB_SIZE;
	78	gd->bd->bi_dram[1].start = DRAM_4GB_SIZE;
	79	gd->bd->bi_dram[1].size = DRAM_2GB_SIZE;
1b7026f5 JL	80	/* use bank0 only */
1b7026f5 JL	81	gd->ram_size = DRAM_2GB_SIZE;
4b7f29ff JL	82	break;
	83	default:
	84	gd->bd->bi_dram[0].size = DRAM_1GB_SIZE;
	85	gd->bd->bi_dram[1].start = 0;
	86	gd->bd->bi_dram[1].size = 0;
1b7026f5	87	gd->ram_size = DRAM_1GB_SIZE;
4b7f29ff JL	88	break;
	89	}
	90
4b7f29ff JL	91	return 0;
	92	}
	93
5a207078 JL	94	int last_stage_init(void)
	95	{
	96	board_set_console();
	97
	98	return 0;
	99	}