[people/ms/u-boot.git] / board / omap1610inn / platform.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2003
 * Texas Instruments, <www.ti.com>
 * Kshitij Gupta <Kshitij@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>

#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#endif


_TEXT_BASE:
	.word	TEXT_BASE	/* sdram load addr from config.mk */

.globl platformsetup
platformsetup:


	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT1)                   *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT1
	ldr	r1,	VAL_ARM_IDLECT1
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT2)  		        *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT2
	ldr	r1,	VAL_ARM_IDLECT2
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT3)		        *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT3
	ldr	r1,	VAL_ARM_IDLECT3
	str	r1,	[r0]


	mov	r1,	#0x01		/* PER_EN bit */
	ldr	r0,	REG_ARM_RSTCT2
	strh	r1,	[r0]		/* CLKM; Peripheral reset. */

	/* Set CLKM to Sync-Scalable	*/
	/* I supposedly need to enable the dsp clock before switching */
	mov	r1,	#0x0000
	ldr	r0,	REG_ARM_SYSST
	strh	r1,	[r0]
	mov	r0,	#0x400
1:
	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
	bne	1b
	ldr	r1,	VAL_ARM_CKCTL
	ldr	r0,	REG_ARM_CKCTL
	strh	r1,	[r0]

	/* a few nops to let settle */
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

	/* setup DPLL 1 */
	/* Ramp up the clock to 96Mhz */
	ldr	r1,	VAL_DPLL1_CTL
	ldr	r0,	REG_DPLL1_CTL
	strh	r1,	[r0]
	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
	beq	lock_end	/* Do not look for lock if BYPASS selected */
2:
	ldrh	r1,	[r0]
	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
	beq 2b			/*	loop until bit goes hi. */
lock_end:


	/*------------------------------------------------------*
	 * Turn off the watchdog during init...			*
 	 *------------------------------------------------------*/
	ldr	r0,	REG_WATCHDOG
	ldr	r1,	WATCHDOG_VAL1
	str	r1,	[r0]
	ldr	r1,	WATCHDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL1
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG

watch1Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch1Wait

	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG
watch2Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch2Wait


	/* Set memory timings corresponding to the new clock speed */

	/* Check execution location to determine current execution location
	 * and branch to appropriate initialization code.
	 */
	/* Load physical SDRAM base. */
	mov 	r0, 	#0x10000000
	/* Get current execution location. */
	mov 	r1, 	pc
	/* Compare. */
	cmp 	r1, 	r0
	/* Skip over EMIF-fast initialization if running from SDRAM. */
	bge 	skip_sdram

	/*
	* Delay for SDRAM initialization.
	*/
	mov	r3,	#0x1800		/* value should be checked */
3:
	subs	r3,	r3,	#0x1	/* Decrement count */
	bne 	3b


	/*
	 * Set SDRAM control values. Disable refresh before MRS command.
	 */

	/* mobile ddr operation */
	ldr	r0,	REG_SDRAM_OPERATION
	mov	r2,	#07
	str	r2,	[r0]

	/* config register */
	ldr	r0,	REG_SDRAM_CONFIG
	ldr	r1,	SDRAM_CONFIG_VAL
	str	r1,	[r0]

	/* manual command register */
	ldr	r0,	REG_SDRAM_MANUAL_CMD
	/* issue set cke high */
	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
	str	r1,	[r0]
	/* issue nop */
	mov	r1,	#CMD_SDRAM_NOP
	str	r1,	[r0]

	mov	r2,	#0x0100
waitMDDR1:
	subs	r2,	r2,	 #1
	bne	waitMDDR1	/* delay loop */

	/* issue precharge */
	mov	r1,	#CMD_SDRAM_PRECHARGE
	str	r1,	[r0]

	/* issue autorefresh x 2 */
	mov	r1,	#CMD_SDRAM_AUTOREFRESH
	str	r1,	[r0]
	str	r1,	[r0]

	/* mrs register ddr mobile */
	ldr	r0,	REG_SDRAM_MRS
	mov	r1,	#0x33
	str	r1,	[r0]

	/* emrs1 low-power register */
	ldr	r0,	REG_SDRAM_EMRS1
	/* self refresh on all banks */
	mov	r1,	#0
	str	r1,	[r0]

	ldr	r0,	REG_DLL_URD_CONTROL
	ldr	r1,	DLL_URD_CONTROL_VAL
	str	r1,	[r0]

	ldr	r0,	REG_DLL_LRD_CONTROL
	ldr	r1,	DLL_LRD_CONTROL_VAL
	str	r1,	[r0]

	ldr	r0,	REG_DLL_WRT_CONTROL
	ldr	r1,	DLL_WRT_CONTROL_VAL
	str	r1,	[r0]

	/* delay loop */
	mov	r2,	#0x0100
waitMDDR2:
	subs	r2,	r2,	#1
	bne	waitMDDR2

	/*
	 * Delay for SDRAM initialization.
	 */
	mov	r3,	#0x1800
4:
	subs	r3,	r3,	#1	/* Decrement count. */
	bne	4b
	b	common_tc

skip_sdram:

	ldr	r0,	REG_SDRAM_CONFIG
	ldr	r1,	SDRAM_CONFIG_VAL
	str	r1,	[r0]

common_tc:
	/* slow interface */
	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
	str	r1,	[r0] /* Chip Select 0 */

	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
	str	r1,	[r0] /* Chip Select 1 */
	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
	str	r1,	[r0] /* Chip Select 3 */
	/* back to arch calling code */
	mov	pc,	lr

	/* the literal pools origin */
	.ltorg


REG_TC_EMIFS_CONFIG:		/* 32 bits */
	.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
	.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
	.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
	.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
	.word 0xfffecc1c

/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL:			/* 16 bits */
	.word 0xfffece00

REG_ARM_IDLECT3:		/* 16 bits */
	.word 0xfffece24
REG_ARM_IDLECT2:		/* 16 bits */
	.word 0xfffece08
REG_ARM_IDLECT1:		/* 16 bits */
	.word 0xfffece04

REG_ARM_RSTCT2:			/* 16 bits */
	.word 0xfffece14
REG_ARM_SYSST:			/* 16 bits */
	.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL:			/* 16 bits */
	.word 0xfffecf00

/* Watch Dog register */
/* secure watchdog stop */
REG_WSPRDOG:
	.word 0xfffeb048
/* watchdog write pending */
REG_WWPSDOG:
	.word 0xfffeb034

WSPRDOG_VAL1:
	.word 0x0000aaaa
WSPRDOG_VAL2:
	.word 0x00005555

/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
 counter @8192 rows, 10 ns, 8 burst */
REG_SDRAM_CONFIG:
	.word 0xfffecc20

/* Operation register */
REG_SDRAM_OPERATION:
	.word 0xfffecc80

/* Manual command register */
REG_SDRAM_MANUAL_CMD:
	.word 0xfffecc84

/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
REG_SDRAM_MRS:
	.word 0xfffecc70

/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
REG_SDRAM_EMRS1:
	.word 0xfffecc78

/* WRT DLL register */
REG_DLL_WRT_CONTROL:
	.word 0xfffecc68
DLL_WRT_CONTROL_VAL:
	.word 0x03f00002

/* URD DLL register */
REG_DLL_URD_CONTROL:
	.word 0xfffeccc0
DLL_URD_CONTROL_VAL:
	.word 0x00800002

/* LRD DLL register */
REG_DLL_LRD_CONTROL:
	.word 0xfffecccc

REG_WATCHDOG:
	.word 0xfffec808

/* 96 MHz Samsung Mobile DDR */
SDRAM_CONFIG_VAL:
	.word 0x001200f4

DLL_LRD_CONTROL_VAL:
	.word 0x00800002

VAL_ARM_CKCTL:
	.word 0x3000
VAL_DPLL1_CTL:
	.word 0x2830

VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x00001131
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x88011131
VAL_TC_EMIFF_SDRAM_CONFIG:
	.word 0x010290fc
VAL_TC_EMIFF_MRS:
	.word 0x00000027

VAL_ARM_IDLECT1:
	.word 0x00000400

VAL_ARM_IDLECT2:
	.word 0x00000886
VAL_ARM_IDLECT3:
	.word 0x00000015

WATCHDOG_VAL1:
	.word 0x000000f5
WATCHDOG_VAL2:
	.word 0x000000a0

/* command values */
.equ CMD_SDRAM_NOP,		0x00000000
.equ CMD_SDRAM_PRECHARGE,	0x00000001
.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007
Commit	Line	Data
6f21347d WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2003
	5	* Texas Instruments, <www.ti.com>
	6	* Kshitij Gupta <Kshitij@ti.com>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <config.h>
	28	#include <version.h>
	29
	30	#if defined(CONFIG_OMAP1610)
	31	#include <./configs/omap1510.h>
	32	#endif
	33
	34
	35	_TEXT_BASE:
	36	.word TEXT_BASE /* sdram load addr from config.mk */
	37
	38	.globl platformsetup
	39	platformsetup:
	40
	41
	42	/------------------------------------------------------
	43	* Set up ARM CLM registers (IDLECT1) *
	44	------------------------------------------------------/
	45	ldr r0, REG_ARM_IDLECT1
	46	ldr r1, VAL_ARM_IDLECT1
	47	str r1, [r0]
	48
	49	/------------------------------------------------------
	50	* Set up ARM CLM registers (IDLECT2) *
	51	------------------------------------------------------/
	52	ldr r0, REG_ARM_IDLECT2
	53	ldr r1, VAL_ARM_IDLECT2
	54	str r1, [r0]
	55
	56	/------------------------------------------------------
	57	* Set up ARM CLM registers (IDLECT3) *
	58	------------------------------------------------------/
	59	ldr r0, REG_ARM_IDLECT3
	60	ldr r1, VAL_ARM_IDLECT3
	61	str r1, [r0]
	62
	63
	64	mov r1, #0x01 /* PER_EN bit */
65	ldr r0, REG_ARM_RSTCT2
66	strh r1, [r0] /* CLKM; Peripheral reset. */
67
68	/* Set CLKM to Sync-Scalable */
69	/* I supposedly need to enable the dsp clock before switching */
70	mov r1, #0x0000
71	ldr r0, REG_ARM_SYSST
72	strh r1, [r0]
73	mov r0, #0x400
74	1:
75	subs r0, r0, #0x1 /* wait for any bubbles to finish */
76	bne 1b
77	ldr r1, VAL_ARM_CKCTL
78	ldr r0, REG_ARM_CKCTL
79	strh r1, [r0]
80
81	/* a few nops to let settle */
82	nop
83	nop
84	nop
85	nop
86	nop
87	nop
88	nop
89	nop
90	nop
91	nop
92
93	/* setup DPLL 1 */
94	/* Ramp up the clock to 96Mhz */
95	ldr r1, VAL_DPLL1_CTL
96	ldr r0, REG_DPLL1_CTL
97	strh r1, [r0]
98	ands r1, r1, #0x10 /* Check if PLL is enabled. */
99	beq lock_end /* Do not look for lock if BYPASS selected */
100	2:
101	ldrh r1, [r0]
102	ands r1, r1, #0x01 /* Check the LOCK bit.*/
103	beq 2b /* loop until bit goes hi. */
104	lock_end:
105
106
107	/------------------------------------------------------
108	* Turn off the watchdog during init... *
109	------------------------------------------------------/
110	ldr r0, REG_WATCHDOG
111	ldr r1, WATCHDOG_VAL1
112	str r1, [r0]
113	ldr r1, WATCHDOG_VAL2
114	str r1, [r0]
115	ldr r0, REG_WSPRDOG
116	ldr r1, WSPRDOG_VAL1
117	str r1, [r0]
118	ldr r0, REG_WWPSDOG
119
120	watch1Wait:
121	ldr r1, [r0]
122	tst r1, #0x10
123	bne watch1Wait
124
125	ldr r0, REG_WSPRDOG
126	ldr r1, WSPRDOG_VAL2
127	str r1, [r0]
128	ldr r0, REG_WWPSDOG
129	watch2Wait:
130	ldr r1, [r0]
131	tst r1, #0x10
132	bne watch2Wait
133
134
6f21347d WD	135	/* Set memory timings corresponding to the new clock speed */
	136
	137	/* Check execution location to determine current execution location
	138	* and branch to appropriate initialization code.
	139	*/
	140	/* Load physical SDRAM base. */
	141	mov r0, #0x10000000
	142	/* Get current execution location. */
	143	mov r1, pc
	144	/* Compare. */
	145	cmp r1, r0
	146	/* Skip over EMIF-fast initialization if running from SDRAM. */
	147	bge skip_sdram
	148
	149	/*
	150	* Delay for SDRAM initialization.
	151	*/
	152	mov r3, #0x1800 /* value should be checked */
	153	3:
	154	subs r3, r3, #0x1 /* Decrement count */
	155	bne 3b
	156
	157
	158	/*
	159	* Set SDRAM control values. Disable refresh before MRS command.
	160	*/
	161
	162	/* mobile ddr operation */
	163	ldr r0, REG_SDRAM_OPERATION
	164	mov r2, #07
	165	str r2, [r0]
	166
	167	/* config register */
	168	ldr r0, REG_SDRAM_CONFIG
	169	ldr r1, SDRAM_CONFIG_VAL
	170	str r1, [r0]
	171
	172	/* manual command register */
	173	ldr r0, REG_SDRAM_MANUAL_CMD
	174	/* issue set cke high */
	175	mov r1, #CMD_SDRAM_CKE_SET_HIGH
	176	str r1, [r0]
	177	/* issue nop */
	178	mov r1, #CMD_SDRAM_NOP
	179	str r1, [r0]
	180
	181	mov r2, #0x0100
	182	waitMDDR1:
	183	subs r2, r2, #1
	184	bne waitMDDR1 /* delay loop */
	185
	186	/* issue precharge */
	187	mov r1, #CMD_SDRAM_PRECHARGE
	188	str r1, [r0]
	189
	190	/* issue autorefresh x 2 */
	191	mov r1, #CMD_SDRAM_AUTOREFRESH
	192	str r1, [r0]
	193	str r1, [r0]
	194
	195	/* mrs register ddr mobile */
	196	ldr r0, REG_SDRAM_MRS
	197	mov r1, #0x33
	198	str r1, [r0]
199
200	/* emrs1 low-power register */
201	ldr r0, REG_SDRAM_EMRS1
202	/* self refresh on all banks */
203	mov r1, #0
204	str r1, [r0]
205
206	ldr r0, REG_DLL_URD_CONTROL
207	ldr r1, DLL_URD_CONTROL_VAL
208	str r1, [r0]
209
210	ldr r0, REG_DLL_LRD_CONTROL
211	ldr r1, DLL_LRD_CONTROL_VAL
212	str r1, [r0]
213
214	ldr r0, REG_DLL_WRT_CONTROL
215	ldr r1, DLL_WRT_CONTROL_VAL
216	str r1, [r0]
217
218	/* delay loop */
219	mov r2, #0x0100
220	waitMDDR2:
221	subs r2, r2, #1
222	bne waitMDDR2
223
224	/*
225	* Delay for SDRAM initialization.
226	*/
227	mov r3, #0x1800
228	4:
229	subs r3, r3, #1 /* Decrement count. */
230	bne 4b
231	b common_tc
232
233	skip_sdram:
234
235	ldr r0, REG_SDRAM_CONFIG
236	ldr r1, SDRAM_CONFIG_VAL
237	str r1, [r0]
238
239	common_tc:
240	/* slow interface */
241	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
242	ldr r0, REG_TC_EMIFS_CS0_CONFIG
243	str r1, [r0] /* Chip Select 0 */
244
245	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
246	ldr r0, REG_TC_EMIFS_CS1_CONFIG
247	str r1, [r0] /* Chip Select 1 */
248	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
249	ldr r0, REG_TC_EMIFS_CS3_CONFIG
250	str r1, [r0] /* Chip Select 3 */
251	/* back to arch calling code */
252	mov pc, lr
253
254	/* the literal pools origin */
255	.ltorg
256
257
258	REG_TC_EMIFS_CONFIG: /* 32 bits */
259	.word 0xfffecc0c
260	REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
261	.word 0xfffecc10
262	REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
263	.word 0xfffecc14
264	REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
265	.word 0xfffecc18
266	REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
267	.word 0xfffecc1c
268
269	/* MPU clock/reset/power mode control registers */
270	REG_ARM_CKCTL: /* 16 bits */
271	.word 0xfffece00
272
273	REG_ARM_IDLECT3: /* 16 bits */
274	.word 0xfffece24
275	REG_ARM_IDLECT2: /* 16 bits */
42d1f039	276	.word 0xfffece08
6f21347d WD	277	REG_ARM_IDLECT1: /* 16 bits */
	278	.word 0xfffece04
	279
	280	REG_ARM_RSTCT2: /* 16 bits */
	281	.word 0xfffece14
	282	REG_ARM_SYSST: /* 16 bits */
	283	.word 0xfffece18
	284	/* DPLL control registers */
	285	REG_DPLL1_CTL: /* 16 bits */
	286	.word 0xfffecf00
	287
	288	/* Watch Dog register */
	289	/* secure watchdog stop */
	290	REG_WSPRDOG:
	291	.word 0xfffeb048
	292	/* watchdog write pending */
	293	REG_WWPSDOG:
42d1f039	294	.word 0xfffeb034
6f21347d WD	295
	296	WSPRDOG_VAL1:
	297	.word 0x0000aaaa
	298	WSPRDOG_VAL2:
	299	.word 0x00005555
	300
	301	/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
	302	counter @8192 rows, 10 ns, 8 burst */
	303	REG_SDRAM_CONFIG:
	304	.word 0xfffecc20
	305
	306	/* Operation register */
	307	REG_SDRAM_OPERATION:
	308	.word 0xfffecc80
	309
	310	/* Manual command register */
	311	REG_SDRAM_MANUAL_CMD:
	312	.word 0xfffecc84
	313
	314	/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
	315	REG_SDRAM_MRS:
	316	.word 0xfffecc70
	317
	318	/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
	319	REG_SDRAM_EMRS1:
	320	.word 0xfffecc78
	321
	322	/* WRT DLL register */
	323	REG_DLL_WRT_CONTROL:
	324	.word 0xfffecc68
	325	DLL_WRT_CONTROL_VAL:
	326	.word 0x03f00002
	327
	328	/* URD DLL register */
	329	REG_DLL_URD_CONTROL:
	330	.word 0xfffeccc0
	331	DLL_URD_CONTROL_VAL:
	332	.word 0x00800002
	333
	334	/* LRD DLL register */
	335	REG_DLL_LRD_CONTROL:
	336	.word 0xfffecccc
	337
	338	REG_WATCHDOG:
	339	.word 0xfffec808
	340
	341	/* 96 MHz Samsung Mobile DDR */
	342	SDRAM_CONFIG_VAL:
42d1f039	343	.word 0x001200f4
6f21347d WD	344
	345	DLL_LRD_CONTROL_VAL:
	346	.word 0x00800002
	347
	348	VAL_ARM_CKCTL:
	349	.word 0x3000
	350	VAL_DPLL1_CTL:
	351	.word 0x2830
	352
	353	VAL_TC_EMIFS_CS0_CONFIG:
	354	.word 0x002130b0
	355	VAL_TC_EMIFS_CS1_CONFIG:
	356	.word 0x00001131
	357	VAL_TC_EMIFS_CS2_CONFIG:
	358	.word 0x000055f0
	359	VAL_TC_EMIFS_CS3_CONFIG:
	360	.word 0x88011131
	361	VAL_TC_EMIFF_SDRAM_CONFIG:
	362	.word 0x010290fc
	363	VAL_TC_EMIFF_MRS:
	364	.word 0x00000027
	365
	366	VAL_ARM_IDLECT1:
	367	.word 0x00000400
	368
	369	VAL_ARM_IDLECT2:
	370	.word 0x00000886
	371	VAL_ARM_IDLECT3:
	372	.word 0x00000015
	373
	374	WATCHDOG_VAL1:
	375	.word 0x000000f5
	376	WATCHDOG_VAL2:
	377	.word 0x000000a0
	378
	379	/* command values */
	380	.equ CMD_SDRAM_NOP, 0x00000000
	381	.equ CMD_SDRAM_PRECHARGE, 0x00000001
	382	.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
	383	.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007