[people/ms/u-boot.git] / board / omap1610inn / platform.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2003
 * Texas Instruments, <www.ti.com>
 * Kshitij Gupta <Kshitij@ti.com>
 *
 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
 * 
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>

#if defined(CONFIG_OMAP1610)
#include <./configs/omap1510.h>
#endif


_TEXT_BASE:
	.word	TEXT_BASE	/* sdram load addr from config.mk */

.globl platformsetup
platformsetup:


	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT1)                   *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT1
	ldr	r1,	VAL_ARM_IDLECT1
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT2)  		        *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT2
	ldr	r1,	VAL_ARM_IDLECT2
	str	r1,	[r0]

	/*------------------------------------------------------*
	 * Set up ARM CLM registers (IDLECT3)		        *
	 *------------------------------------------------------*/
	ldr	r0,	REG_ARM_IDLECT3
	ldr	r1,	VAL_ARM_IDLECT3
	str	r1,	[r0]


	mov	r1,	#0x01		/* PER_EN bit */
	ldr	r0,	REG_ARM_RSTCT2
	strh	r1,	[r0]		/* CLKM; Peripheral reset. */

	/* Set CLKM to Sync-Scalable	*/
	/* I supposedly need to enable the dsp clock before switching */
	mov	r1,	#0x0000
	ldr	r0,	REG_ARM_SYSST
	strh	r1,	[r0]
	mov	r0,	#0x400
1:
	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
	bne	1b
	ldr	r1,	VAL_ARM_CKCTL
	ldr	r0,	REG_ARM_CKCTL
	strh	r1,	[r0]

	/* a few nops to let settle */
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

	/* setup DPLL 1 */
	/* Ramp up the clock to 96Mhz */
	ldr	r1,	VAL_DPLL1_CTL
	ldr	r0,	REG_DPLL1_CTL
	strh	r1,	[r0]
	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
	beq	lock_end	/* Do not look for lock if BYPASS selected */
2:
	ldrh	r1,	[r0]
	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
	beq 2b			/*	loop until bit goes hi. */
lock_end:


	/*------------------------------------------------------*
	 * Turn off the watchdog during init...			*
 	 *------------------------------------------------------*/
	ldr	r0,	REG_WATCHDOG
	ldr	r1,	WATCHDOG_VAL1
	str	r1,	[r0]
	ldr	r1,	WATCHDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL1
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG

watch1Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch1Wait

	ldr	r0,	REG_WSPRDOG
	ldr	r1,	WSPRDOG_VAL2
	str	r1,	[r0]
	ldr	r0,	REG_WWPSDOG
watch2Wait:
	ldr	r1,	[r0]
	tst	r1,	#0x10
	bne	watch2Wait


	/* Set memory timings corresponding to the new clock speed */

	/* Check execution location to determine current execution location
	 * and branch to appropriate initialization code.
	 */
	/* Load physical SDRAM base. */
	mov 	r0, 	#0x10000000
	/* Get current execution location. */
	mov 	r1, 	pc
	/* Compare. */
	cmp 	r1, 	r0
	/* Skip over EMIF-fast initialization if running from SDRAM. */
	bge 	skip_sdram

	/*
	* Delay for SDRAM initialization.
	*/
	mov	r3,	#0x1800		/* value should be checked */
3:
	subs	r3,	r3,	#0x1	/* Decrement count */
	bne 	3b


	/*
	 * Set SDRAM control values. Disable refresh before MRS command.
	 */

	/* mobile ddr operation */
	ldr	r0,	REG_SDRAM_OPERATION
	mov	r2,	#07
	str	r2,	[r0]

	/* config register */
	ldr	r0,	REG_SDRAM_CONFIG
	ldr	r1,	SDRAM_CONFIG_VAL
	str	r1,	[r0]

	/* manual command register */
	ldr	r0,	REG_SDRAM_MANUAL_CMD
	/* issue set cke high */
	mov	r1,	#CMD_SDRAM_CKE_SET_HIGH
	str	r1,	[r0]
	/* issue nop */
	mov	r1,	#CMD_SDRAM_NOP
	str	r1,	[r0]

	mov	r2,	#0x0100
waitMDDR1:
	subs	r2,	r2,	 #1
	bne	waitMDDR1	/* delay loop */

	/* issue precharge */
	mov	r1,	#CMD_SDRAM_PRECHARGE
	str	r1,	[r0]

	/* issue autorefresh x 2 */
	mov	r1,	#CMD_SDRAM_AUTOREFRESH
	str	r1,	[r0]
	str	r1,	[r0]

	/* mrs register ddr mobile */
	ldr	r0,	REG_SDRAM_MRS
	mov	r1,	#0x33
	str	r1,	[r0]

	/* emrs1 low-power register */
	ldr	r0,	REG_SDRAM_EMRS1
	/* self refresh on all banks */
	mov	r1,	#0
	str	r1,	[r0]

	ldr	r0,	REG_DLL_URD_CONTROL
	ldr	r1,	DLL_URD_CONTROL_VAL
	str	r1,	[r0]

	ldr	r0,	REG_DLL_LRD_CONTROL
	ldr	r1,	DLL_LRD_CONTROL_VAL
	str	r1,	[r0]

	ldr	r0,	REG_DLL_WRT_CONTROL
	ldr	r1,	DLL_WRT_CONTROL_VAL
	str	r1,	[r0]

	/* delay loop */
	mov	r2,	#0x0100
waitMDDR2:
	subs	r2,	r2,	#1
	bne	waitMDDR2

	/*
	 * Delay for SDRAM initialization.
	 */
	mov	r3,	#0x1800
4:
	subs	r3,	r3,	#1	/* Decrement count. */
	bne	4b
	b	common_tc

skip_sdram:

	ldr	r0,	REG_SDRAM_CONFIG
	ldr	r1,	SDRAM_CONFIG_VAL
	str	r1,	[r0]

common_tc:
	/* slow interface */
	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
	str	r1,	[r0] /* Chip Select 0 */

	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
	str	r1,	[r0] /* Chip Select 1 */
	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
	str	r1,	[r0] /* Chip Select 3 */

#ifdef CONFIG_H2_OMAP1610	
	/* inserting additional 2 clock cycle hold time for LAN */
	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
	ldr    	r1,     VAL_TC_EMIFS_CS1_ADVANCED
	str     r1,     [r0]
#endif
	/* Start MPU Timer 1 */
	ldr	r0,	REG_MPU_LOAD_TIMER
	ldr	r1,	VAL_MPU_LOAD_TIMER
	str	r1,	[r0]

	ldr	r0,	REG_MPU_CNTL_TIMER
	ldr	r1,	VAL_MPU_CNTL_TIMER
	str	r1,	[r0]

	/* back to arch calling code */
	mov	pc,	lr

	/* the literal pools origin */
	.ltorg


REG_TC_EMIFS_CONFIG:		/* 32 bits */
	.word 0xfffecc0c
REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
	.word 0xfffecc10
REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
	.word 0xfffecc14
REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
	.word 0xfffecc18
REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
	.word 0xfffecc1c

#ifdef CONFIG_H2_OMAP1610
REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
	.word 0xfffecc54
#endif

/* MPU clock/reset/power mode control registers */
REG_ARM_CKCTL:			/* 16 bits */
	.word 0xfffece00

REG_ARM_IDLECT3:		/* 16 bits */
	.word 0xfffece24
REG_ARM_IDLECT2:		/* 16 bits */
	.word 0xfffece08
REG_ARM_IDLECT1:		/* 16 bits */
	.word 0xfffece04

REG_ARM_RSTCT2:			/* 16 bits */
	.word 0xfffece14
REG_ARM_SYSST:			/* 16 bits */
	.word 0xfffece18
/* DPLL control registers */
REG_DPLL1_CTL:			/* 16 bits */
	.word 0xfffecf00

/* Watch Dog register */
/* secure watchdog stop */
REG_WSPRDOG:
	.word 0xfffeb048
/* watchdog write pending */
REG_WWPSDOG:
	.word 0xfffeb034

WSPRDOG_VAL1:
	.word 0x0000aaaa
WSPRDOG_VAL2:
	.word 0x00005555

/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
 counter @8192 rows, 10 ns, 8 burst */
REG_SDRAM_CONFIG:
	.word 0xfffecc20

/* Operation register */
REG_SDRAM_OPERATION:
	.word 0xfffecc80

/* Manual command register */
REG_SDRAM_MANUAL_CMD:
	.word 0xfffecc84

/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
REG_SDRAM_MRS:
	.word 0xfffecc70

/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
REG_SDRAM_EMRS1:
	.word 0xfffecc78

/* WRT DLL register */
REG_DLL_WRT_CONTROL:
	.word 0xfffecc68
DLL_WRT_CONTROL_VAL:
	.word 0x03f00002

/* URD DLL register */
REG_DLL_URD_CONTROL:
	.word 0xfffeccc0
DLL_URD_CONTROL_VAL:
	.word 0x00800002

/* LRD DLL register */
REG_DLL_LRD_CONTROL:
	.word 0xfffecccc

REG_WATCHDOG:
	.word 0xfffec808

REG_MPU_LOAD_TIMER:
	.word 0xfffec600
REG_MPU_CNTL_TIMER:
	.word 0xfffec500

/* 96 MHz Samsung Mobile DDR */
SDRAM_CONFIG_VAL:
	.word 0x001200f4

DLL_LRD_CONTROL_VAL:
	.word 0x00800002

VAL_ARM_CKCTL:
	.word 0x3000
VAL_DPLL1_CTL:
	.word 0x2830

#ifdef CONFIG_INNOVATOROMAP1610
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x002130b0
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x00001131
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0x000055f0
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x88011131
#endif

#ifdef CONFIG_H2_OMAP1610
VAL_TC_EMIFS_CS0_CONFIG:
	.word 0x00203331
VAL_TC_EMIFS_CS1_CONFIG:
	.word 0x8180fff3
VAL_TC_EMIFS_CS2_CONFIG:
	.word 0xf800f22a
VAL_TC_EMIFS_CS3_CONFIG:
	.word 0x88011131
VAL_TC_EMIFS_CS1_ADVANCED:
	.word 0x00000022
#endif

VAL_TC_EMIFF_SDRAM_CONFIG:
	.word 0x010290fc
VAL_TC_EMIFF_MRS:
	.word 0x00000027

VAL_ARM_IDLECT1:
	.word 0x00000400

VAL_ARM_IDLECT2:
	.word 0x00000886
VAL_ARM_IDLECT3:
	.word 0x00000015

WATCHDOG_VAL1:
	.word 0x000000f5
WATCHDOG_VAL2:
	.word 0x000000a0

VAL_MPU_LOAD_TIMER:
	.word 0xffffffff
VAL_MPU_CNTL_TIMER:
	.word 0xffffffa1

/* command values */
.equ CMD_SDRAM_NOP,		0x00000000
.equ CMD_SDRAM_PRECHARGE,	0x00000001
.equ CMD_SDRAM_AUTOREFRESH,	0x00000002
.equ CMD_SDRAM_CKE_SET_HIGH,	0x00000007
Commit	Line	Data
6f21347d WD	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2003
	5	* Texas Instruments, <www.ti.com>
	6	* Kshitij Gupta <Kshitij@ti.com>
	7	*
63e73c9a WD	8	* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
63e73c9a WD	9	*
6f21347d WD	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <config.h>
	30	#include <version.h>
	31
	32	#if defined(CONFIG_OMAP1610)
	33	#include <./configs/omap1510.h>
	34	#endif
	35
	36
	37	_TEXT_BASE:
	38	.word TEXT_BASE /* sdram load addr from config.mk */
	39
	40	.globl platformsetup
	41	platformsetup:
	42
	43
	44	/------------------------------------------------------
	45	* Set up ARM CLM registers (IDLECT1) *
	46	------------------------------------------------------/
	47	ldr r0, REG_ARM_IDLECT1
	48	ldr r1, VAL_ARM_IDLECT1
	49	str r1, [r0]
	50
	51	/------------------------------------------------------
	52	* Set up ARM CLM registers (IDLECT2) *
	53	------------------------------------------------------/
	54	ldr r0, REG_ARM_IDLECT2
	55	ldr r1, VAL_ARM_IDLECT2
	56	str r1, [r0]
	57
	58	/------------------------------------------------------
	59	* Set up ARM CLM registers (IDLECT3) *
	60	------------------------------------------------------/
	61	ldr r0, REG_ARM_IDLECT3
	62	ldr r1, VAL_ARM_IDLECT3
	63	str r1, [r0]
	64
	65
	66	mov r1, #0x01 /* PER_EN bit */
	67	ldr r0, REG_ARM_RSTCT2
	68	strh r1, [r0] /* CLKM; Peripheral reset. */
	69
	70	/* Set CLKM to Sync-Scalable */
	71	/* I supposedly need to enable the dsp clock before switching */
	72	mov r1, #0x0000
	73	ldr r0, REG_ARM_SYSST
74	strh r1, [r0]
75	mov r0, #0x400
76	1:
77	subs r0, r0, #0x1 /* wait for any bubbles to finish */
78	bne 1b
79	ldr r1, VAL_ARM_CKCTL
80	ldr r0, REG_ARM_CKCTL
81	strh r1, [r0]
82
83	/* a few nops to let settle */
84	nop
85	nop
86	nop
87	nop
88	nop
89	nop
90	nop
91	nop
92	nop
93	nop
94
95	/* setup DPLL 1 */
96	/* Ramp up the clock to 96Mhz */
97	ldr r1, VAL_DPLL1_CTL
98	ldr r0, REG_DPLL1_CTL
99	strh r1, [r0]
100	ands r1, r1, #0x10 /* Check if PLL is enabled. */
101	beq lock_end /* Do not look for lock if BYPASS selected */
102	2:
103	ldrh r1, [r0]
104	ands r1, r1, #0x01 /* Check the LOCK bit.*/
105	beq 2b /* loop until bit goes hi. */
106	lock_end:
107
108
109	/------------------------------------------------------
110	* Turn off the watchdog during init... *
111	------------------------------------------------------/
112	ldr r0, REG_WATCHDOG
113	ldr r1, WATCHDOG_VAL1
114	str r1, [r0]
115	ldr r1, WATCHDOG_VAL2
116	str r1, [r0]
117	ldr r0, REG_WSPRDOG
118	ldr r1, WSPRDOG_VAL1
119	str r1, [r0]
120	ldr r0, REG_WWPSDOG
121
122	watch1Wait:
123	ldr r1, [r0]
124	tst r1, #0x10
125	bne watch1Wait
126
127	ldr r0, REG_WSPRDOG
128	ldr r1, WSPRDOG_VAL2
129	str r1, [r0]
130	ldr r0, REG_WWPSDOG
131	watch2Wait:
132	ldr r1, [r0]
133	tst r1, #0x10
134	bne watch2Wait
135
136
6f21347d WD	137	/* Set memory timings corresponding to the new clock speed */
	138
	139	/* Check execution location to determine current execution location
	140	* and branch to appropriate initialization code.
	141	*/
	142	/* Load physical SDRAM base. */
	143	mov r0, #0x10000000
	144	/* Get current execution location. */
	145	mov r1, pc
	146	/* Compare. */
	147	cmp r1, r0
	148	/* Skip over EMIF-fast initialization if running from SDRAM. */
	149	bge skip_sdram
	150
	151	/*
	152	* Delay for SDRAM initialization.
	153	*/
	154	mov r3, #0x1800 /* value should be checked */
	155	3:
	156	subs r3, r3, #0x1 /* Decrement count */
	157	bne 3b
	158
	159
	160	/*
	161	* Set SDRAM control values. Disable refresh before MRS command.
	162	*/
	163
	164	/* mobile ddr operation */
	165	ldr r0, REG_SDRAM_OPERATION
	166	mov r2, #07
	167	str r2, [r0]
	168
	169	/* config register */
	170	ldr r0, REG_SDRAM_CONFIG
	171	ldr r1, SDRAM_CONFIG_VAL
	172	str r1, [r0]
	173
	174	/* manual command register */
	175	ldr r0, REG_SDRAM_MANUAL_CMD
	176	/* issue set cke high */
	177	mov r1, #CMD_SDRAM_CKE_SET_HIGH
	178	str r1, [r0]
	179	/* issue nop */
	180	mov r1, #CMD_SDRAM_NOP
	181	str r1, [r0]
	182
	183	mov r2, #0x0100
	184	waitMDDR1:
	185	subs r2, r2, #1
	186	bne waitMDDR1 /* delay loop */
	187
	188	/* issue precharge */
	189	mov r1, #CMD_SDRAM_PRECHARGE
	190	str r1, [r0]
	191
	192	/* issue autorefresh x 2 */
	193	mov r1, #CMD_SDRAM_AUTOREFRESH
	194	str r1, [r0]
	195	str r1, [r0]
	196
	197	/* mrs register ddr mobile */
	198	ldr r0, REG_SDRAM_MRS
	199	mov r1, #0x33
	200	str r1, [r0]
201
202	/* emrs1 low-power register */
203	ldr r0, REG_SDRAM_EMRS1
204	/* self refresh on all banks */
205	mov r1, #0
206	str r1, [r0]
207
208	ldr r0, REG_DLL_URD_CONTROL
209	ldr r1, DLL_URD_CONTROL_VAL
210	str r1, [r0]
211
212	ldr r0, REG_DLL_LRD_CONTROL
213	ldr r1, DLL_LRD_CONTROL_VAL
214	str r1, [r0]
215
216	ldr r0, REG_DLL_WRT_CONTROL
217	ldr r1, DLL_WRT_CONTROL_VAL
218	str r1, [r0]
219
220	/* delay loop */
221	mov r2, #0x0100
222	waitMDDR2:
223	subs r2, r2, #1
224	bne waitMDDR2
225
226	/*
227	* Delay for SDRAM initialization.
228	*/
229	mov r3, #0x1800
230	4:
231	subs r3, r3, #1 /* Decrement count. */
232	bne 4b
233	b common_tc
234
235	skip_sdram:
236
237	ldr r0, REG_SDRAM_CONFIG
238	ldr r1, SDRAM_CONFIG_VAL
239	str r1, [r0]
240
241	common_tc:
242	/* slow interface */
243	ldr r1, VAL_TC_EMIFS_CS0_CONFIG
244	ldr r0, REG_TC_EMIFS_CS0_CONFIG
245	str r1, [r0] /* Chip Select 0 */
246
247	ldr r1, VAL_TC_EMIFS_CS1_CONFIG
248	ldr r0, REG_TC_EMIFS_CS1_CONFIG
249	str r1, [r0] /* Chip Select 1 */
250	ldr r1, VAL_TC_EMIFS_CS3_CONFIG
251	ldr r0, REG_TC_EMIFS_CS3_CONFIG
252	str r1, [r0] /* Chip Select 3 */
63e73c9a WD	253
	254	#ifdef CONFIG_H2_OMAP1610
	255	/* inserting additional 2 clock cycle hold time for LAN */
	256	ldr r0, REG_TC_EMIFS_CS1_ADVANCED
	257	ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
	258	str r1, [r0]
	259	#endif
	260	/* Start MPU Timer 1 */
	261	ldr r0, REG_MPU_LOAD_TIMER
	262	ldr r1, VAL_MPU_LOAD_TIMER
	263	str r1, [r0]
	264
	265	ldr r0, REG_MPU_CNTL_TIMER
	266	ldr r1, VAL_MPU_CNTL_TIMER
	267	str r1, [r0]
	268
6f21347d WD	269	/* back to arch calling code */
	270	mov pc, lr
	271
	272	/* the literal pools origin */
	273	.ltorg
	274
	275
	276	REG_TC_EMIFS_CONFIG: /* 32 bits */
	277	.word 0xfffecc0c
	278	REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
	279	.word 0xfffecc10
	280	REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
	281	.word 0xfffecc14
	282	REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
	283	.word 0xfffecc18
	284	REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
	285	.word 0xfffecc1c
	286
63e73c9a WD	287	#ifdef CONFIG_H2_OMAP1610
	288	REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
	289	.word 0xfffecc54
	290	#endif
	291
6f21347d WD	292	/* MPU clock/reset/power mode control registers */
	293	REG_ARM_CKCTL: /* 16 bits */
	294	.word 0xfffece00
	295
	296	REG_ARM_IDLECT3: /* 16 bits */
	297	.word 0xfffece24
	298	REG_ARM_IDLECT2: /* 16 bits */
42d1f039	299	.word 0xfffece08
6f21347d WD	300	REG_ARM_IDLECT1: /* 16 bits */
	301	.word 0xfffece04
	302
	303	REG_ARM_RSTCT2: /* 16 bits */
	304	.word 0xfffece14
	305	REG_ARM_SYSST: /* 16 bits */
	306	.word 0xfffece18
	307	/* DPLL control registers */
	308	REG_DPLL1_CTL: /* 16 bits */
	309	.word 0xfffecf00
	310
	311	/* Watch Dog register */
	312	/* secure watchdog stop */
	313	REG_WSPRDOG:
	314	.word 0xfffeb048
	315	/* watchdog write pending */
	316	REG_WWPSDOG:
42d1f039	317	.word 0xfffeb034
6f21347d WD	318
	319	WSPRDOG_VAL1:
	320	.word 0x0000aaaa
	321	WSPRDOG_VAL2:
	322	.word 0x00005555
	323
	324	/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
	325	counter @8192 rows, 10 ns, 8 burst */
	326	REG_SDRAM_CONFIG:
	327	.word 0xfffecc20
	328
	329	/* Operation register */
	330	REG_SDRAM_OPERATION:
	331	.word 0xfffecc80
	332
	333	/* Manual command register */
	334	REG_SDRAM_MANUAL_CMD:
	335	.word 0xfffecc84
	336
	337	/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
	338	REG_SDRAM_MRS:
	339	.word 0xfffecc70
	340
	341	/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
	342	REG_SDRAM_EMRS1:
	343	.word 0xfffecc78
	344
	345	/* WRT DLL register */
	346	REG_DLL_WRT_CONTROL:
	347	.word 0xfffecc68
	348	DLL_WRT_CONTROL_VAL:
	349	.word 0x03f00002
	350
	351	/* URD DLL register */
	352	REG_DLL_URD_CONTROL:
	353	.word 0xfffeccc0
	354	DLL_URD_CONTROL_VAL:
	355	.word 0x00800002
	356
	357	/* LRD DLL register */
	358	REG_DLL_LRD_CONTROL:
	359	.word 0xfffecccc
	360
	361	REG_WATCHDOG:
	362	.word 0xfffec808
	363
63e73c9a WD	364	REG_MPU_LOAD_TIMER:
	365	.word 0xfffec600
	366	REG_MPU_CNTL_TIMER:
	367	.word 0xfffec500
	368
6f21347d WD	369	/* 96 MHz Samsung Mobile DDR */
6f21347d WD	370	SDRAM_CONFIG_VAL:
42d1f039	371	.word 0x001200f4
6f21347d WD	372
	373	DLL_LRD_CONTROL_VAL:
	374	.word 0x00800002
	375
	376	VAL_ARM_CKCTL:
	377	.word 0x3000
	378	VAL_DPLL1_CTL:
	379	.word 0x2830
	380
63e73c9a	381	#ifdef CONFIG_INNOVATOROMAP1610
6f21347d WD	382	VAL_TC_EMIFS_CS0_CONFIG:
	383	.word 0x002130b0
	384	VAL_TC_EMIFS_CS1_CONFIG:
	385	.word 0x00001131
	386	VAL_TC_EMIFS_CS2_CONFIG:
	387	.word 0x000055f0
	388	VAL_TC_EMIFS_CS3_CONFIG:
	389	.word 0x88011131
63e73c9a WD	390	#endif
	391
	392	#ifdef CONFIG_H2_OMAP1610
	393	VAL_TC_EMIFS_CS0_CONFIG:
	394	.word 0x00203331
	395	VAL_TC_EMIFS_CS1_CONFIG:
	396	.word 0x8180fff3
	397	VAL_TC_EMIFS_CS2_CONFIG:
	398	.word 0xf800f22a
	399	VAL_TC_EMIFS_CS3_CONFIG:
	400	.word 0x88011131
	401	VAL_TC_EMIFS_CS1_ADVANCED:
	402	.word 0x00000022
	403	#endif
	404
6f21347d WD	405	VAL_TC_EMIFF_SDRAM_CONFIG:
	406	.word 0x010290fc
	407	VAL_TC_EMIFF_MRS:
	408	.word 0x00000027
	409
	410	VAL_ARM_IDLECT1:
	411	.word 0x00000400
	412
	413	VAL_ARM_IDLECT2:
	414	.word 0x00000886
	415	VAL_ARM_IDLECT3:
	416	.word 0x00000015
	417
	418	WATCHDOG_VAL1:
	419	.word 0x000000f5
	420	WATCHDOG_VAL2:
	421	.word 0x000000a0
	422
63e73c9a WD	423	VAL_MPU_LOAD_TIMER:
	424	.word 0xffffffff
	425	VAL_MPU_CNTL_TIMER:
	426	.word 0xffffffa1
	427
6f21347d WD	428	/* command values */
	429	.equ CMD_SDRAM_NOP, 0x00000000
	430	.equ CMD_SDRAM_PRECHARGE, 0x00000001
	431	.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
	432	.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007