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fe5d488f AB |
1 | /* |
2 | * Maintainer : Steve Sakoman <steve@sakoman.com> | |
3 | * | |
4 | * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by | |
5 | * Richard Woodruff <r-woodruff2@ti.com> | |
6 | * Syed Mohammed Khasim <khasim@ti.com> | |
7 | * Sunil Kumar <sunilsaini05@gmail.com> | |
8 | * Shashi Ranjan <shashiranjanmca05@gmail.com> | |
9 | * | |
10 | * (C) Copyright 2004-2008 | |
11 | * Texas Instruments, <www.ti.com> | |
12 | * | |
13 | * SPDX-License-Identifier: GPL-2.0+ | |
14 | */ | |
15 | #include <asm/io.h> | |
16 | #include <asm/arch/mem.h> | |
17 | #include <asm/arch/sys_proto.h> | |
18 | #include "overo.h" | |
19 | ||
20 | /* | |
21 | * Routine: get_board_mem_timings | |
22 | * Description: If we use SPL then there is no x-loader nor config header | |
23 | * so we have to setup the DDR timings ourself on both banks. | |
24 | */ | |
25 | void get_board_mem_timings(struct board_sdrc_timings *timings) | |
26 | { | |
27 | timings->mr = MICRON_V_MR_165; | |
28 | switch (get_board_revision()) { | |
29 | case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ | |
30 | timings->mcfg = MICRON_V_MCFG_165(256 << 20); | |
31 | timings->ctrla = MICRON_V_ACTIMA_165; | |
32 | timings->ctrlb = MICRON_V_ACTIMB_165; | |
33 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; | |
34 | break; | |
35 | case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ | |
36 | case REVISION_4: | |
37 | timings->mcfg = MICRON_V_MCFG_200(256 << 20); | |
38 | timings->ctrla = MICRON_V_ACTIMA_200; | |
39 | timings->ctrlb = MICRON_V_ACTIMB_200; | |
40 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; | |
41 | break; | |
42 | case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ | |
43 | timings->mcfg = HYNIX_V_MCFG_200(256 << 20); | |
44 | timings->ctrla = HYNIX_V_ACTIMA_200; | |
45 | timings->ctrlb = HYNIX_V_ACTIMB_200; | |
46 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; | |
47 | break; | |
48 | case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ | |
49 | timings->mcfg = MCFG(512 << 20, 15); | |
50 | timings->ctrla = MICRON_V_ACTIMA_200; | |
51 | timings->ctrlb = MICRON_V_ACTIMB_200; | |
52 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; | |
53 | break; | |
54 | default: | |
55 | timings->mcfg = MICRON_V_MCFG_165(128 << 20); | |
56 | timings->ctrla = MICRON_V_ACTIMA_165; | |
57 | timings->ctrlb = MICRON_V_ACTIMB_165; | |
58 | timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; | |
59 | } | |
60 | } |