projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a4c8d138 SR |
1 | /* |
| 2 | * (C) Copyright 2006 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| a4c8d138 SR |
6 | */ |
| 7 | ||
| 25ddd1fb | 8 | #include <asm-offsets.h> |
| a4c8d138 | 9 | #include <ppc_asm.tmpl> |
| cf6eb6da | 10 | #include <asm/mmu.h> |
| a4c8d138 SR |
11 | #include <config.h> |
| 12 | ||
| a4c8d138 SR |
13 | /************************************************************************** |
| 14 | * TLB TABLE | |
| 15 | * | |
| 16 | * This table is used by the cpu boot code to setup the initial tlb | |
| 17 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 18 | * this table lets each board set things up however they like. | |
| 19 | * | |
| 20 | * Pointer to the table is returned in r1 | |
| 21 | * | |
| 22 | *************************************************************************/ | |
| 23 | ||
| 24 | .section .bootpg,"ax" | |
| 25 | .globl tlbtab | |
| 26 | ||
| 27 | tlbtab: | |
| 566a494f | 28 | tlbtab_start |
| a4c8d138 | 29 | |
| 566a494f HS |
30 | /* |
| 31 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
| 32 | * speed up boot process. It is patched after relocation to enable SA_I | |
| 33 | */ | |
| cf6eb6da | 34 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/) |
| a4c8d138 | 35 | |
| 566a494f | 36 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| cf6eb6da | 37 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
| a4c8d138 | 38 | |
| 566a494f HS |
39 | /* |
| 40 | * TLB entries for SDRAM are not needed on this platform. | |
| 41 | * They are dynamically generated in the SPD DDR detection | |
| 42 | * routine. | |
| 43 | */ | |
| a4c8d138 | 44 | |
| cf6eb6da | 45 | tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG ) |
| a4c8d138 | 46 | |
| 566a494f | 47 | /* PCI */ |
| cf6eb6da SR |
48 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG ) |
| 49 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG ) | |
| 50 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG ) | |
| 51 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG ) | |
| a4c8d138 | 52 | |
| 566a494f | 53 | /* USB 2.0 Device */ |
| cf6eb6da | 54 | tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG ) |
| 566a494f HS |
55 | |
| 56 | tlbtab_end |