projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a4c8d138 SR |
1 | /* |
| 2 | * (C) Copyright 2006 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #include <ppc_asm.tmpl> | |
| cf6eb6da | 25 | #include <asm/mmu.h> |
| a4c8d138 SR |
26 | #include <config.h> |
| 27 | ||
| a4c8d138 SR |
28 | /************************************************************************** |
| 29 | * TLB TABLE | |
| 30 | * | |
| 31 | * This table is used by the cpu boot code to setup the initial tlb | |
| 32 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 33 | * this table lets each board set things up however they like. | |
| 34 | * | |
| 35 | * Pointer to the table is returned in r1 | |
| 36 | * | |
| 37 | *************************************************************************/ | |
| 38 | ||
| 39 | .section .bootpg,"ax" | |
| 40 | .globl tlbtab | |
| 41 | ||
| 42 | tlbtab: | |
| 566a494f | 43 | tlbtab_start |
| a4c8d138 | 44 | |
| 566a494f HS |
45 | /* |
| 46 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
| 47 | * speed up boot process. It is patched after relocation to enable SA_I | |
| 48 | */ | |
| cf6eb6da | 49 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/) |
| a4c8d138 | 50 | |
| 566a494f | 51 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| cf6eb6da | 52 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
| a4c8d138 | 53 | |
| 566a494f HS |
54 | /* |
| 55 | * TLB entries for SDRAM are not needed on this platform. | |
| 56 | * They are dynamically generated in the SPD DDR detection | |
| 57 | * routine. | |
| 58 | */ | |
| a4c8d138 | 59 | |
| cf6eb6da | 60 | tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG ) |
| a4c8d138 | 61 | |
| 566a494f | 62 | /* PCI */ |
| cf6eb6da SR |
63 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG ) |
| 64 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG ) | |
| 65 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG ) | |
| 66 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG ) | |
| a4c8d138 | 67 | |
| 566a494f | 68 | /* USB 2.0 Device */ |
| cf6eb6da | 69 | tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG ) |
| 566a494f HS |
70 | |
| 71 | tlbtab_end |