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a4c8d138 SR |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <ppc4xx.h> | |
566a494f HS |
26 | #include <malloc.h> |
27 | #include <command.h> | |
28 | #include <crc.h> | |
a4c8d138 SR |
29 | #include <asm/processor.h> |
30 | #include <spd_sdram.h> | |
566a494f HS |
31 | #include <status_led.h> |
32 | #include <sha1.h> | |
a4c8d138 SR |
33 | |
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
36 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
37 | ||
566a494f HS |
38 | unsigned char sha1_checksum[SHA1_SUM_LEN]; |
39 | ||
40 | /* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */ | |
41 | unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, | |
42 | 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf}; | |
43 | ||
44 | static void set_leds (int val) | |
45 | { | |
46 | out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27)); | |
47 | } | |
48 | ||
49 | #define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27) | |
50 | ||
51 | void __led_init (led_id_t mask, int state) | |
52 | { | |
53 | int val = GET_LEDS; | |
54 | ||
55 | if (state == STATUS_LED_ON) | |
56 | val |= mask; | |
57 | else | |
58 | val &= ~mask; | |
59 | set_leds (val); | |
60 | } | |
61 | ||
62 | void __led_set (led_id_t mask, int state) | |
63 | { | |
64 | int val = GET_LEDS; | |
65 | ||
66 | if (state == STATUS_LED_ON) | |
67 | val |= mask; | |
68 | else if (state == STATUS_LED_OFF) | |
69 | val &= ~mask; | |
70 | set_leds (val); | |
71 | } | |
72 | ||
73 | void __led_toggle (led_id_t mask) | |
a4c8d138 | 74 | { |
566a494f HS |
75 | int val = GET_LEDS; |
76 | ||
77 | val ^= mask; | |
78 | set_leds (val); | |
a4c8d138 SR |
79 | } |
80 | ||
566a494f HS |
81 | static void status_led_blink (void) |
82 | { | |
83 | int i; | |
84 | int val = GET_LEDS; | |
85 | ||
86 | /* set all LED which are on, to state BLINKING */ | |
87 | for (i = 0; i < 4; i++) { | |
96e1d75b HS |
88 | if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING); |
89 | else status_led_set (3 - i, STATUS_LED_OFF); | |
90 | val = val >> 1; | |
566a494f HS |
91 | } |
92 | } | |
93 | ||
94 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) | |
95 | void show_boot_progress (int val) | |
a4c8d138 | 96 | { |
566a494f HS |
97 | /* find all valid Codes for val in README */ |
98 | if (val == -30) return; | |
99 | if (val < 0) { | |
100 | /* smthing goes wrong */ | |
101 | status_led_blink (); | |
102 | return; | |
103 | } | |
104 | switch (val) { | |
105 | case 1: | |
106 | /* validating Image */ | |
107 | status_led_set (0, STATUS_LED_OFF); | |
108 | status_led_set (1, STATUS_LED_ON); | |
109 | status_led_set (2, STATUS_LED_ON); | |
110 | break; | |
111 | case 15: | |
112 | /* booting */ | |
113 | status_led_set (0, STATUS_LED_ON); | |
114 | status_led_set (1, STATUS_LED_ON); | |
115 | status_led_set (2, STATUS_LED_ON); | |
116 | break; | |
96e1d75b | 117 | #if 0 |
566a494f HS |
118 | case 64: |
119 | /* starting Ethernet configuration */ | |
120 | status_led_set (0, STATUS_LED_OFF); | |
121 | status_led_set (1, STATUS_LED_OFF); | |
122 | status_led_set (2, STATUS_LED_ON); | |
123 | break; | |
96e1d75b | 124 | #endif |
566a494f HS |
125 | case 80: |
126 | /* loading Image */ | |
127 | status_led_set (0, STATUS_LED_ON); | |
128 | status_led_set (1, STATUS_LED_OFF); | |
129 | status_led_set (2, STATUS_LED_ON); | |
130 | break; | |
131 | } | |
a4c8d138 | 132 | } |
566a494f | 133 | #endif |
a4c8d138 SR |
134 | |
135 | int board_early_init_f(void) | |
136 | { | |
137 | register uint reg; | |
138 | ||
139 | set_leds(0); /* display boot info counter */ | |
140 | ||
141 | /*-------------------------------------------------------------------- | |
142 | * Setup the external bus controller/chip selects | |
143 | *-------------------------------------------------------------------*/ | |
144 | mtdcr(ebccfga, xbcfg); | |
145 | reg = mfdcr(ebccfgd); | |
146 | mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ | |
147 | ||
148 | /*-------------------------------------------------------------------- | |
149 | * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c | |
150 | * via define from board config file. | |
151 | *-------------------------------------------------------------------*/ | |
152 | ||
153 | /*-------------------------------------------------------------------- | |
154 | * Setup the interrupt controller polarities, triggers, etc. | |
155 | *-------------------------------------------------------------------*/ | |
156 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
157 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
158 | mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ | |
159 | mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */ | |
160 | mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */ | |
161 | mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ | |
162 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
163 | ||
164 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
165 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
166 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
167 | mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ | |
168 | mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ | |
169 | mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ | |
170 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
171 | ||
172 | /*-------------------------------------------------------------------- | |
173 | * Setup other serial configuration | |
174 | *-------------------------------------------------------------------*/ | |
175 | mfsdr(sdr_pci0, reg); | |
176 | mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ | |
177 | mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */ | |
178 | mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ | |
179 | ||
180 | return 0; | |
181 | } | |
182 | ||
566a494f HS |
183 | #define EEPROM_LEN 256 |
184 | void load_sernum_ethaddr (void) | |
185 | { | |
186 | int ret; | |
187 | char buf[EEPROM_LEN]; | |
188 | char mac[32]; | |
189 | char *use_eeprom; | |
190 | u16 checksumcrc16 = 0; | |
191 | ||
192 | /* read the MACs from EEprom */ | |
193 | status_led_set (0, STATUS_LED_ON); | |
194 | status_led_set (1, STATUS_LED_ON); | |
195 | ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN); | |
196 | if (ret == 0) { | |
197 | checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2); | |
198 | /* check, if the EEprom is programmed: | |
199 | * - The Prefix(Byte 0,1,2) is equal to "ATR" | |
200 | * - The checksum, stored in the last 2 Bytes, is correct | |
201 | */ | |
202 | if ((strncmp (buf,"ATR",3) != 0) || | |
4ef218f6 WD |
203 | ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) || |
204 | ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) { | |
566a494f HS |
205 | /* EEprom is not programmed */ |
206 | printf("%s: EEPROM Checksum not OK\n", __FUNCTION__); | |
207 | } else { | |
208 | /* get the MACs */ | |
4ef218f6 | 209 | sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", |
566a494f HS |
210 | buf[3], |
211 | buf[4], | |
212 | buf[5], | |
213 | buf[6], | |
214 | buf[7], | |
215 | buf[8]); | |
216 | setenv ("ethaddr", (char *) mac); | |
4ef218f6 | 217 | sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", |
566a494f HS |
218 | buf[9], |
219 | buf[10], | |
220 | buf[11], | |
221 | buf[12], | |
222 | buf[13], | |
223 | buf[14]); | |
224 | setenv ("eth1addr", (char *) mac); | |
225 | return; | |
226 | } | |
227 | } | |
228 | ||
229 | /* some error reading the EEprom */ | |
230 | if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) { | |
231 | /* dont use bootcmd */ | |
232 | setenv("bootdelay", "-1"); | |
233 | return; | |
234 | } | |
235 | /* == default ? use standard */ | |
236 | if (strncmp (use_eeprom, "default", 7) == 0) { | |
237 | return; | |
238 | } | |
239 | /* Env doesnt exist -> hang */ | |
240 | status_led_blink (); | |
241 | hang (); | |
242 | return; | |
243 | } | |
244 | ||
245 | #ifdef CONFIG_PREBOOT | |
246 | ||
247 | static uchar kbd_magic_prefix[] = "key_magic"; | |
248 | static uchar kbd_command_prefix[] = "key_cmd"; | |
249 | ||
250 | struct kbd_data_t { | |
251 | char s1; | |
252 | char s2; | |
253 | }; | |
254 | ||
255 | struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) | |
256 | { | |
257 | char *val; | |
258 | unsigned long tmp; | |
259 | ||
260 | /* use the DIPs for some bootoptions */ | |
261 | val = getenv (ENV_NAME_DIP); | |
262 | tmp = simple_strtoul (val, NULL, 16); | |
263 | ||
264 | kbd_data->s2 = (tmp & 0x0f); | |
265 | kbd_data->s1 = (tmp & 0xf0) >> 4; | |
266 | return kbd_data; | |
267 | } | |
268 | ||
269 | static int compare_magic (const struct kbd_data_t *kbd_data, char *str) | |
270 | { | |
271 | char s1 = str[0]; | |
272 | ||
273 | if (s1 >= '0' && s1 <= '9') | |
274 | s1 -= '0'; | |
275 | else if (s1 >= 'a' && s1 <= 'f') | |
276 | s1 = s1 - 'a' + 10; | |
277 | else if (s1 >= 'A' && s1 <= 'F') | |
278 | s1 = s1 - 'A' + 10; | |
279 | else | |
280 | return -1; | |
281 | ||
282 | if (s1 != kbd_data->s1) return -1; | |
283 | ||
284 | s1 = str[1]; | |
285 | if (s1 >= '0' && s1 <= '9') | |
286 | s1 -= '0'; | |
287 | else if (s1 >= 'a' && s1 <= 'f') | |
288 | s1 = s1 - 'a' + 10; | |
289 | else if (s1 >= 'A' && s1 <= 'F') | |
290 | s1 = s1 - 'A' + 10; | |
291 | else | |
292 | return -1; | |
293 | ||
294 | if (s1 != kbd_data->s2) return -1; | |
295 | return 0; | |
296 | } | |
297 | ||
298 | static char *key_match (const struct kbd_data_t *kbd_data) | |
299 | { | |
300 | char magic[sizeof (kbd_magic_prefix) + 1]; | |
301 | char *suffix; | |
302 | char *kbd_magic_keys; | |
303 | ||
304 | /* | |
305 | * The following string defines the characters that can be appended | |
306 | * to "key_magic" to form the names of environment variables that | |
307 | * hold "magic" key codes, i. e. such key codes that can cause | |
308 | * pre-boot actions. If the string is empty (""), then only | |
309 | * "key_magic" is checked (old behaviour); the string "125" causes | |
310 | * checks for "key_magic1", "key_magic2" and "key_magic5", etc. | |
311 | */ | |
312 | if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) | |
313 | kbd_magic_keys = ""; | |
314 | ||
315 | /* loop over all magic keys; | |
316 | * use '\0' suffix in case of empty string | |
317 | */ | |
318 | for (suffix = kbd_magic_keys; *suffix || | |
319 | suffix == kbd_magic_keys; ++suffix) { | |
320 | sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); | |
321 | if (compare_magic (kbd_data, getenv (magic)) == 0) { | |
322 | char cmd_name[sizeof (kbd_command_prefix) + 1]; | |
323 | char *cmd; | |
324 | ||
325 | sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); | |
326 | cmd = getenv (cmd_name); | |
327 | ||
328 | return (cmd); | |
329 | } | |
330 | } | |
331 | return (NULL); | |
332 | } | |
333 | ||
334 | #endif /* CONFIG_PREBOOT */ | |
335 | ||
336 | static int pcs440ep_readinputs (void) | |
337 | { | |
338 | int i; | |
339 | char value[20]; | |
340 | ||
341 | /* read the inputs and set the Envvars */ | |
342 | /* Revision Level Bit 26 - 29 */ | |
343 | i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2); | |
344 | i = swapbits[i]; | |
345 | sprintf (value, "%02x", i); | |
346 | setenv (ENV_NAME_REVLEV, value); | |
347 | /* Solder Switch Bit 30 - 33 */ | |
348 | i = (in32 (GPIO0_IR) & 0x00000003) << 2; | |
349 | i += (in32 (GPIO1_IR) & 0xc0000000) >> 30; | |
350 | i = swapbits[i]; | |
351 | sprintf (value, "%02x", i); | |
352 | setenv (ENV_NAME_SOLDER, value); | |
353 | /* DIP Switch Bit 49 - 56 */ | |
354 | i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7); | |
355 | i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4]; | |
356 | sprintf (value, "%02x", i); | |
357 | setenv (ENV_NAME_DIP, value); | |
358 | return 0; | |
359 | } | |
360 | ||
361 | ||
362 | #if defined(CONFIG_SHA1_CHECK_UB_IMG) | |
363 | /************************************************************************* | |
364 | * calculate a SHA1 sum for the U-Boot image in Flash. | |
365 | * | |
366 | ************************************************************************/ | |
367 | static int pcs440ep_sha1 (int docheck) | |
368 | { | |
369 | unsigned char *data; | |
370 | unsigned char *ptroff; | |
371 | unsigned char output[20]; | |
372 | unsigned char org[20]; | |
373 | int i, len = CONFIG_SHA1_LEN; | |
374 | ||
375 | memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len); | |
376 | data = (unsigned char *)CFG_LOAD_ADDR; | |
377 | ptroff = &data[len + SHA1_SUM_POS]; | |
378 | ||
379 | for (i = 0; i < SHA1_SUM_LEN; i++) { | |
380 | org[i] = ptroff[i]; | |
381 | ptroff[i] = 0; | |
382 | } | |
4ef218f6 | 383 | |
566a494f HS |
384 | sha1_csum ((unsigned char *) data, len, (unsigned char *)output); |
385 | ||
386 | if (docheck == 2) { | |
387 | for (i = 0; i < 20 ; i++) { | |
388 | printf("%02X ", output[i]); | |
389 | } | |
390 | printf("\n"); | |
391 | } | |
392 | if (docheck == 1) { | |
393 | for (i = 0; i < 20 ; i++) { | |
394 | if (org[i] != output[i]) return 1; | |
395 | } | |
396 | } | |
397 | return 0; | |
398 | } | |
399 | ||
400 | /************************************************************************* | |
401 | * do some checks after the SHA1 checksum from the U-Boot Image was | |
402 | * calculated. | |
403 | * | |
404 | ************************************************************************/ | |
405 | static void pcs440ep_checksha1 (void) | |
406 | { | |
407 | int ret; | |
408 | char *cs_test; | |
409 | ||
96e1d75b HS |
410 | status_led_set (0, STATUS_LED_OFF); |
411 | status_led_set (1, STATUS_LED_OFF); | |
412 | status_led_set (2, STATUS_LED_ON); | |
566a494f HS |
413 | ret = pcs440ep_sha1 (1); |
414 | if (ret == 0) return; | |
415 | ||
416 | if ((cs_test = getenv ("cs_test")) == NULL) { | |
417 | /* Env doesnt exist -> hang */ | |
418 | status_led_blink (); | |
419 | hang (); | |
420 | } | |
421 | ||
422 | if (strncmp (cs_test, "off", 3) == 0) { | |
423 | printf ("SHA1 U-Boot sum NOT ok!\n"); | |
424 | setenv ("bootdelay", "-1"); | |
425 | } | |
426 | } | |
427 | #else | |
428 | static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);} | |
429 | #endif | |
430 | ||
a4c8d138 SR |
431 | int misc_init_r (void) |
432 | { | |
433 | uint pbcr; | |
434 | int size_val = 0; | |
435 | ||
436 | /* Re-do sizing to get full correct info */ | |
437 | mtdcr(ebccfga, pb0cr); | |
438 | pbcr = mfdcr(ebccfgd); | |
439 | switch (gd->bd->bi_flashsize) { | |
440 | case 1 << 20: | |
441 | size_val = 0; | |
442 | break; | |
443 | case 2 << 20: | |
444 | size_val = 1; | |
445 | break; | |
446 | case 4 << 20: | |
447 | size_val = 2; | |
448 | break; | |
449 | case 8 << 20: | |
450 | size_val = 3; | |
451 | break; | |
452 | case 16 << 20: | |
453 | size_val = 4; | |
454 | break; | |
455 | case 32 << 20: | |
456 | size_val = 5; | |
457 | break; | |
458 | case 64 << 20: | |
459 | size_val = 6; | |
460 | break; | |
461 | case 128 << 20: | |
462 | size_val = 7; | |
463 | break; | |
464 | } | |
465 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); | |
466 | mtdcr(ebccfga, pb0cr); | |
467 | mtdcr(ebccfgd, pbcr); | |
468 | ||
469 | /* adjust flash start and offset */ | |
470 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
471 | gd->bd->bi_flashoffset = 0; | |
472 | ||
473 | /* Monitor protection ON by default */ | |
474 | (void)flash_protect(FLAG_PROTECT_SET, | |
475 | -CFG_MONITOR_LEN, | |
476 | 0xffffffff, | |
477 | &flash_info[1]); | |
478 | ||
479 | /* Env protection ON by default */ | |
480 | (void)flash_protect(FLAG_PROTECT_SET, | |
481 | CFG_ENV_ADDR_REDUND, | |
482 | CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, | |
4526c87e | 483 | &flash_info[1]); |
a4c8d138 | 484 | |
566a494f HS |
485 | pcs440ep_readinputs (); |
486 | pcs440ep_checksha1 (); | |
487 | #ifdef CONFIG_PREBOOT | |
488 | { | |
489 | struct kbd_data_t kbd_data; | |
490 | /* Decode keys */ | |
491 | char *str = strdup (key_match (get_keys (&kbd_data))); | |
492 | /* Set or delete definition */ | |
493 | setenv ("preboot", str); | |
494 | free (str); | |
495 | } | |
496 | #endif /* CONFIG_PREBOOT */ | |
a4c8d138 SR |
497 | return 0; |
498 | } | |
499 | ||
500 | int checkboard(void) | |
501 | { | |
502 | char *s = getenv("serial#"); | |
503 | ||
504 | printf("Board: PCS440EP"); | |
505 | if (s != NULL) { | |
506 | puts(", serial# "); | |
507 | puts(s); | |
508 | } | |
509 | putc('\n'); | |
510 | ||
511 | return (0); | |
512 | } | |
513 | ||
566a494f HS |
514 | void spd_ddr_init_hang (void) |
515 | { | |
516 | status_led_set (0, STATUS_LED_OFF); | |
517 | status_led_set (1, STATUS_LED_ON); | |
518 | /* we cannot use hang() because we are still running from | |
519 | Flash, and so the status_led driver is not initialized */ | |
520 | puts ("### ERROR ### Please RESET the board ###\n"); | |
521 | for (;;) { | |
522 | __led_toggle (4); | |
523 | udelay (100000); | |
524 | } | |
525 | } | |
566a494f | 526 | |
a4c8d138 SR |
527 | long int initdram (int board_type) |
528 | { | |
529 | long dram_size = 0; | |
530 | ||
566a494f HS |
531 | status_led_set (0, STATUS_LED_ON); |
532 | status_led_set (1, STATUS_LED_OFF); | |
a4c8d138 | 533 | dram_size = spd_sdram(); |
566a494f HS |
534 | status_led_set (0, STATUS_LED_OFF); |
535 | status_led_set (1, STATUS_LED_ON); | |
536 | if (dram_size == 0) { | |
537 | hang(); | |
538 | } | |
a4c8d138 SR |
539 | |
540 | return dram_size; | |
541 | } | |
542 | ||
543 | #if defined(CFG_DRAM_TEST) | |
544 | int testdram(void) | |
545 | { | |
546 | unsigned long *mem = (unsigned long *)0; | |
547 | const unsigned long kend = (1024 / sizeof(unsigned long)); | |
548 | unsigned long k, n; | |
549 | ||
550 | mtmsr(0); | |
551 | ||
552 | for (k = 0; k < CFG_KBYTES_SDRAM; | |
553 | ++k, mem += (1024 / sizeof(unsigned long))) { | |
554 | if ((k & 1023) == 0) { | |
555 | printf("%3d MB\r", k / 1024); | |
556 | } | |
557 | ||
558 | memset(mem, 0xaaaaaaaa, 1024); | |
559 | for (n = 0; n < kend; ++n) { | |
560 | if (mem[n] != 0xaaaaaaaa) { | |
561 | printf("SDRAM test fails at: %08x\n", | |
562 | (uint) & mem[n]); | |
563 | return 1; | |
564 | } | |
565 | } | |
566 | ||
567 | memset(mem, 0x55555555, 1024); | |
568 | for (n = 0; n < kend; ++n) { | |
569 | if (mem[n] != 0x55555555) { | |
570 | printf("SDRAM test fails at: %08x\n", | |
571 | (uint) & mem[n]); | |
572 | return 1; | |
573 | } | |
574 | } | |
575 | } | |
576 | printf("SDRAM test passes\n"); | |
577 | return 0; | |
578 | } | |
579 | #endif | |
580 | ||
581 | /************************************************************************* | |
582 | * pci_pre_init | |
583 | * | |
584 | * This routine is called just prior to registering the hose and gives | |
585 | * the board the opportunity to check things. Returning a value of zero | |
586 | * indicates that things are bad & PCI initialization should be aborted. | |
587 | * | |
588 | * Different boards may wish to customize the pci controller structure | |
589 | * (add regions, override default access routines, etc) or perform | |
590 | * certain pre-initialization actions. | |
591 | * | |
592 | ************************************************************************/ | |
466fff1a | 593 | #if defined(CONFIG_PCI) |
a4c8d138 SR |
594 | int pci_pre_init(struct pci_controller *hose) |
595 | { | |
596 | unsigned long addr; | |
597 | ||
598 | /*-------------------------------------------------------------------------+ | |
599 | | Set priority for all PLB3 devices to 0. | |
600 | | Set PLB3 arbiter to fair mode. | |
601 | +-------------------------------------------------------------------------*/ | |
602 | mfsdr(sdr_amp1, addr); | |
603 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
604 | addr = mfdcr(plb3_acr); | |
605 | mtdcr(plb3_acr, addr | 0x80000000); | |
606 | ||
607 | /*-------------------------------------------------------------------------+ | |
608 | | Set priority for all PLB4 devices to 0. | |
609 | +-------------------------------------------------------------------------*/ | |
610 | mfsdr(sdr_amp0, addr); | |
611 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
612 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
613 | mtdcr(plb4_acr, addr); | |
614 | ||
615 | /*-------------------------------------------------------------------------+ | |
616 | | Set Nebula PLB4 arbiter to fair mode. | |
617 | +-------------------------------------------------------------------------*/ | |
618 | /* Segment0 */ | |
619 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
620 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
621 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
622 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
623 | mtdcr(plb0_acr, addr); | |
624 | ||
625 | /* Segment1 */ | |
626 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
627 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
628 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
629 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
630 | mtdcr(plb1_acr, addr); | |
631 | ||
632 | return 1; | |
633 | } | |
466fff1a | 634 | #endif /* defined(CONFIG_PCI) */ |
a4c8d138 SR |
635 | |
636 | /************************************************************************* | |
637 | * pci_target_init | |
638 | * | |
639 | * The bootstrap configuration provides default settings for the pci | |
640 | * inbound map (PIM). But the bootstrap config choices are limited and | |
641 | * may not be sufficient for a given board. | |
642 | * | |
643 | ************************************************************************/ | |
644 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) | |
645 | void pci_target_init(struct pci_controller *hose) | |
646 | { | |
647 | /*--------------------------------------------------------------------------+ | |
648 | * Set up Direct MMIO registers | |
649 | *--------------------------------------------------------------------------*/ | |
650 | /*--------------------------------------------------------------------------+ | |
651 | | PowerPC440 EP PCI Master configuration. | |
652 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
653 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF | |
654 | | Use byte reversed out routines to handle endianess. | |
655 | | Make this region non-prefetchable. | |
656 | +--------------------------------------------------------------------------*/ | |
657 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
658 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ | |
659 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ | |
660 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
661 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
662 | ||
663 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
664 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ | |
665 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ | |
666 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
667 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
668 | ||
669 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
670 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ | |
671 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
672 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
673 | ||
674 | /*--------------------------------------------------------------------------+ | |
675 | * Set up Configuration registers | |
676 | *--------------------------------------------------------------------------*/ | |
677 | ||
678 | /* Program the board's subsystem id/vendor id */ | |
679 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
680 | CFG_PCI_SUBSYS_VENDORID); | |
681 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); | |
682 | ||
683 | /* Configure command register as bus master */ | |
684 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
685 | ||
686 | /* 240nS PCI clock */ | |
687 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
688 | ||
689 | /* No error reporting */ | |
690 | pci_write_config_word(0, PCI_ERREN, 0); | |
691 | ||
692 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
693 | ||
694 | } | |
695 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ | |
696 | ||
697 | /************************************************************************* | |
698 | * pci_master_init | |
699 | * | |
700 | ************************************************************************/ | |
701 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) | |
702 | void pci_master_init(struct pci_controller *hose) | |
703 | { | |
704 | unsigned short temp_short; | |
705 | ||
706 | /*--------------------------------------------------------------------------+ | |
707 | | Write the PowerPC440 EP PCI Configuration regs. | |
708 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
709 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
710 | +--------------------------------------------------------------------------*/ | |
711 | pci_read_config_word(0, PCI_COMMAND, &temp_short); | |
712 | pci_write_config_word(0, PCI_COMMAND, | |
713 | temp_short | PCI_COMMAND_MASTER | | |
714 | PCI_COMMAND_MEMORY); | |
715 | } | |
716 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ | |
717 | ||
718 | /************************************************************************* | |
719 | * is_pci_host | |
720 | * | |
721 | * This routine is called to determine if a pci scan should be | |
722 | * performed. With various hardware environments (especially cPCI and | |
723 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
724 | * bit in the strap register, or generic host/adapter assumptions. | |
725 | * | |
726 | * Rather than hard-code a bad assumption in the general 440 code, the | |
727 | * 440 pci code requires the board to decide at runtime. | |
728 | * | |
729 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
730 | * | |
731 | * | |
732 | ************************************************************************/ | |
733 | #if defined(CONFIG_PCI) | |
734 | int is_pci_host(struct pci_controller *hose) | |
735 | { | |
736 | /* PCS440EP is always configured as host. */ | |
737 | return (1); | |
738 | } | |
739 | #endif /* defined(CONFIG_PCI) */ | |
740 | ||
741 | /************************************************************************* | |
742 | * hw_watchdog_reset | |
743 | * | |
744 | * This routine is called to reset (keep alive) the watchdog timer | |
745 | * | |
746 | ************************************************************************/ | |
747 | #if defined(CONFIG_HW_WATCHDOG) | |
748 | void hw_watchdog_reset(void) | |
749 | { | |
750 | ||
751 | } | |
752 | #endif | |
566a494f HS |
753 | |
754 | /************************************************************************* | |
755 | * "led" Commando for the U-Boot shell | |
756 | * | |
757 | ************************************************************************/ | |
758 | int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
759 | { | |
96e1d75b | 760 | int rcode = 0, i; |
566a494f HS |
761 | ulong pattern = 0; |
762 | ||
96e1d75b HS |
763 | pattern = simple_strtoul (argv[1], NULL, 16); |
764 | if (pattern > 0x400) { | |
765 | int val = GET_LEDS; | |
766 | printf ("led: %x\n", val); | |
767 | return rcode; | |
768 | } | |
769 | if (pattern > 0x200) { | |
566a494f HS |
770 | status_led_blink (); |
771 | hang (); | |
772 | return rcode; | |
773 | } | |
96e1d75b | 774 | if (pattern > 0x100) { |
566a494f HS |
775 | status_led_blink (); |
776 | return rcode; | |
777 | } | |
778 | pattern &= 0x0f; | |
96e1d75b HS |
779 | for (i = 0; i < 4; i++) { |
780 | if (pattern & 0x01) status_led_set (i, STATUS_LED_ON); | |
781 | else status_led_set (i, STATUS_LED_OFF); | |
782 | pattern = pattern >> 1; | |
783 | } | |
566a494f HS |
784 | return rcode; |
785 | } | |
786 | ||
787 | U_BOOT_CMD( | |
788 | led, 2, 1, do_led, | |
96e1d75b HS |
789 | "led [bitmask] - set the DIAG-LED\n", |
790 | "[bitmask] 0x01 = DIAG 1 on\n" | |
791 | " 0x02 = DIAG 2 on\n" | |
792 | " 0x04 = DIAG 3 on\n" | |
793 | " 0x08 = DIAG 4 on\n" | |
794 | " > 0x100 set the LED, who are on, to state blinking\n" | |
566a494f HS |
795 | ); |
796 | ||
797 | #if defined(CONFIG_SHA1_CHECK_UB_IMG) | |
798 | /************************************************************************* | |
799 | * "sha1" Commando for the U-Boot shell | |
800 | * | |
801 | ************************************************************************/ | |
802 | int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
803 | { | |
804 | int rcode = -1; | |
805 | ||
806 | if (argc < 2) { | |
807 | usage: | |
808 | printf ("Usage:\n%s\n", cmdtp->usage); | |
809 | return 1; | |
810 | } | |
811 | ||
812 | if (argc >= 3) { | |
813 | unsigned char *data; | |
814 | unsigned char output[20]; | |
815 | int len; | |
816 | int i; | |
4ef218f6 | 817 | |
566a494f HS |
818 | data = (unsigned char *)simple_strtoul (argv[1], NULL, 16); |
819 | len = simple_strtoul (argv[2], NULL, 16); | |
820 | sha1_csum (data, len, (unsigned char *)output); | |
821 | printf ("U-Boot sum:\n"); | |
822 | for (i = 0; i < 20 ; i++) { | |
823 | printf ("%02X ", output[i]); | |
824 | } | |
825 | printf ("\n"); | |
826 | if (argc == 4) { | |
827 | data = (unsigned char *)simple_strtoul (argv[3], NULL, 16); | |
828 | memcpy (data, output, 20); | |
829 | } | |
830 | return 0; | |
831 | } | |
832 | if (argc == 2) { | |
833 | char *ptr = argv[1]; | |
834 | if (*ptr != '-') goto usage; | |
835 | ptr++; | |
836 | if ((*ptr == 'c') || (*ptr == 'C')) { | |
837 | rcode = pcs440ep_sha1 (1); | |
838 | printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : ""); | |
839 | } else if ((*ptr == 'p') || (*ptr == 'P')) { | |
840 | rcode = pcs440ep_sha1 (2); | |
841 | } else { | |
842 | rcode = pcs440ep_sha1 (0); | |
843 | } | |
4ef218f6 | 844 | return rcode; |
566a494f HS |
845 | } |
846 | return rcode; | |
847 | } | |
848 | ||
849 | U_BOOT_CMD( | |
850 | sha1, 4, 1, do_sha1, | |
851 | "sha1 - calculate the SHA1 Sum\n", | |
852 | "address len [addr] calculate the SHA1 sum [save at addr]\n" | |
853 | " -p calculate the SHA1 sum from the U-Boot image in flash and print\n" | |
854 | " -c check the U-Boot image in flash\n" | |
855 | ); | |
856 | #endif | |
857 | ||
858 | #ifdef CONFIG_IDE_PREINIT | |
859 | int ide_preinit (void) | |
860 | { | |
861 | /* Set True IDE Mode */ | |
862 | out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000)); | |
863 | out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); | |
864 | out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040)); | |
865 | udelay (100000); | |
866 | return 0; | |
867 | } | |
868 | #endif | |
869 | ||
870 | #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) | |
871 | void ide_set_reset (int idereset) | |
872 | { | |
873 | debug ("ide_reset(%d)\n", idereset); | |
874 | if (idereset == 0) { | |
875 | out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); | |
876 | } else { | |
877 | out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000)); | |
878 | } | |
879 | udelay (10000); | |
880 | } | |
881 | #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ |