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a4c8d138 SR |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <ppc4xx.h> | |
566a494f HS |
26 | #include <malloc.h> |
27 | #include <command.h> | |
28 | #include <crc.h> | |
a4c8d138 SR |
29 | #include <asm/processor.h> |
30 | #include <spd_sdram.h> | |
566a494f HS |
31 | #include <status_led.h> |
32 | #include <sha1.h> | |
a4c8d138 SR |
33 | |
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
36 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
37 | ||
566a494f HS |
38 | unsigned char sha1_checksum[SHA1_SUM_LEN]; |
39 | ||
40 | /* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */ | |
41 | unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, | |
42 | 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf}; | |
43 | ||
44 | static void set_leds (int val) | |
45 | { | |
46 | out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27)); | |
47 | } | |
48 | ||
49 | #define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27) | |
50 | ||
51 | void __led_init (led_id_t mask, int state) | |
52 | { | |
53 | int val = GET_LEDS; | |
54 | ||
55 | if (state == STATUS_LED_ON) | |
56 | val |= mask; | |
57 | else | |
58 | val &= ~mask; | |
59 | set_leds (val); | |
60 | } | |
61 | ||
62 | void __led_set (led_id_t mask, int state) | |
63 | { | |
64 | int val = GET_LEDS; | |
65 | ||
66 | if (state == STATUS_LED_ON) | |
67 | val |= mask; | |
68 | else if (state == STATUS_LED_OFF) | |
69 | val &= ~mask; | |
70 | set_leds (val); | |
71 | } | |
72 | ||
73 | void __led_toggle (led_id_t mask) | |
74 | { | |
75 | int val = GET_LEDS; | |
76 | ||
77 | val ^= mask; | |
78 | set_leds (val); | |
79 | } | |
80 | ||
81 | static void status_led_blink (void) | |
82 | { | |
83 | int i; | |
84 | int val = GET_LEDS; | |
85 | ||
86 | /* set all LED which are on, to state BLINKING */ | |
87 | for (i = 0; i < 4; i++) { | |
88 | if (val & 0x08) status_led_set (i, STATUS_LED_BLINKING); | |
89 | val = val << 1; | |
90 | } | |
91 | } | |
92 | ||
93 | #if defined(CONFIG_SHOW_BOOT_PROGRESS) | |
94 | void show_boot_progress (int val) | |
a4c8d138 | 95 | { |
566a494f HS |
96 | /* find all valid Codes for val in README */ |
97 | if (val == -30) return; | |
98 | if (val < 0) { | |
99 | /* smthing goes wrong */ | |
100 | status_led_blink (); | |
101 | return; | |
102 | } | |
103 | switch (val) { | |
104 | case 1: | |
105 | /* validating Image */ | |
106 | status_led_set (0, STATUS_LED_OFF); | |
107 | status_led_set (1, STATUS_LED_ON); | |
108 | status_led_set (2, STATUS_LED_ON); | |
109 | break; | |
110 | case 15: | |
111 | /* booting */ | |
112 | status_led_set (0, STATUS_LED_ON); | |
113 | status_led_set (1, STATUS_LED_ON); | |
114 | status_led_set (2, STATUS_LED_ON); | |
115 | break; | |
116 | case 64: | |
117 | /* starting Ethernet configuration */ | |
118 | status_led_set (0, STATUS_LED_OFF); | |
119 | status_led_set (1, STATUS_LED_OFF); | |
120 | status_led_set (2, STATUS_LED_ON); | |
121 | break; | |
122 | case 80: | |
123 | /* loading Image */ | |
124 | status_led_set (0, STATUS_LED_ON); | |
125 | status_led_set (1, STATUS_LED_OFF); | |
126 | status_led_set (2, STATUS_LED_ON); | |
127 | break; | |
128 | } | |
a4c8d138 | 129 | } |
566a494f | 130 | #endif |
a4c8d138 SR |
131 | |
132 | int board_early_init_f(void) | |
133 | { | |
134 | register uint reg; | |
135 | ||
136 | set_leds(0); /* display boot info counter */ | |
137 | ||
138 | /*-------------------------------------------------------------------- | |
139 | * Setup the external bus controller/chip selects | |
140 | *-------------------------------------------------------------------*/ | |
141 | mtdcr(ebccfga, xbcfg); | |
142 | reg = mfdcr(ebccfgd); | |
143 | mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ | |
144 | ||
145 | /*-------------------------------------------------------------------- | |
146 | * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c | |
147 | * via define from board config file. | |
148 | *-------------------------------------------------------------------*/ | |
149 | ||
150 | /*-------------------------------------------------------------------- | |
151 | * Setup the interrupt controller polarities, triggers, etc. | |
152 | *-------------------------------------------------------------------*/ | |
153 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
154 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
155 | mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */ | |
156 | mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */ | |
157 | mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */ | |
158 | mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ | |
159 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
160 | ||
161 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
162 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
163 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
164 | mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ | |
165 | mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ | |
166 | mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ | |
167 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
168 | ||
169 | /*-------------------------------------------------------------------- | |
170 | * Setup other serial configuration | |
171 | *-------------------------------------------------------------------*/ | |
172 | mfsdr(sdr_pci0, reg); | |
173 | mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ | |
174 | mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */ | |
175 | mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
566a494f HS |
180 | #define EEPROM_LEN 256 |
181 | void load_sernum_ethaddr (void) | |
182 | { | |
183 | int ret; | |
184 | char buf[EEPROM_LEN]; | |
185 | char mac[32]; | |
186 | char *use_eeprom; | |
187 | u16 checksumcrc16 = 0; | |
188 | ||
189 | /* read the MACs from EEprom */ | |
190 | status_led_set (0, STATUS_LED_ON); | |
191 | status_led_set (1, STATUS_LED_ON); | |
192 | ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN); | |
193 | if (ret == 0) { | |
194 | checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2); | |
195 | /* check, if the EEprom is programmed: | |
196 | * - The Prefix(Byte 0,1,2) is equal to "ATR" | |
197 | * - The checksum, stored in the last 2 Bytes, is correct | |
198 | */ | |
199 | if ((strncmp (buf,"ATR",3) != 0) || | |
200 | ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) || | |
201 | ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) | |
202 | { | |
203 | /* EEprom is not programmed */ | |
204 | printf("%s: EEPROM Checksum not OK\n", __FUNCTION__); | |
205 | } else { | |
206 | /* get the MACs */ | |
207 | sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", | |
208 | buf[3], | |
209 | buf[4], | |
210 | buf[5], | |
211 | buf[6], | |
212 | buf[7], | |
213 | buf[8]); | |
214 | setenv ("ethaddr", (char *) mac); | |
215 | sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", | |
216 | buf[9], | |
217 | buf[10], | |
218 | buf[11], | |
219 | buf[12], | |
220 | buf[13], | |
221 | buf[14]); | |
222 | setenv ("eth1addr", (char *) mac); | |
223 | return; | |
224 | } | |
225 | } | |
226 | ||
227 | /* some error reading the EEprom */ | |
228 | if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) { | |
229 | /* dont use bootcmd */ | |
230 | setenv("bootdelay", "-1"); | |
231 | return; | |
232 | } | |
233 | /* == default ? use standard */ | |
234 | if (strncmp (use_eeprom, "default", 7) == 0) { | |
235 | return; | |
236 | } | |
237 | /* Env doesnt exist -> hang */ | |
238 | status_led_blink (); | |
239 | hang (); | |
240 | return; | |
241 | } | |
242 | ||
243 | #ifdef CONFIG_PREBOOT | |
244 | ||
245 | static uchar kbd_magic_prefix[] = "key_magic"; | |
246 | static uchar kbd_command_prefix[] = "key_cmd"; | |
247 | ||
248 | struct kbd_data_t { | |
249 | char s1; | |
250 | char s2; | |
251 | }; | |
252 | ||
253 | struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) | |
254 | { | |
255 | char *val; | |
256 | unsigned long tmp; | |
257 | ||
258 | /* use the DIPs for some bootoptions */ | |
259 | val = getenv (ENV_NAME_DIP); | |
260 | tmp = simple_strtoul (val, NULL, 16); | |
261 | ||
262 | kbd_data->s2 = (tmp & 0x0f); | |
263 | kbd_data->s1 = (tmp & 0xf0) >> 4; | |
264 | return kbd_data; | |
265 | } | |
266 | ||
267 | static int compare_magic (const struct kbd_data_t *kbd_data, char *str) | |
268 | { | |
269 | char s1 = str[0]; | |
270 | ||
271 | if (s1 >= '0' && s1 <= '9') | |
272 | s1 -= '0'; | |
273 | else if (s1 >= 'a' && s1 <= 'f') | |
274 | s1 = s1 - 'a' + 10; | |
275 | else if (s1 >= 'A' && s1 <= 'F') | |
276 | s1 = s1 - 'A' + 10; | |
277 | else | |
278 | return -1; | |
279 | ||
280 | if (s1 != kbd_data->s1) return -1; | |
281 | ||
282 | s1 = str[1]; | |
283 | if (s1 >= '0' && s1 <= '9') | |
284 | s1 -= '0'; | |
285 | else if (s1 >= 'a' && s1 <= 'f') | |
286 | s1 = s1 - 'a' + 10; | |
287 | else if (s1 >= 'A' && s1 <= 'F') | |
288 | s1 = s1 - 'A' + 10; | |
289 | else | |
290 | return -1; | |
291 | ||
292 | if (s1 != kbd_data->s2) return -1; | |
293 | return 0; | |
294 | } | |
295 | ||
296 | static char *key_match (const struct kbd_data_t *kbd_data) | |
297 | { | |
298 | char magic[sizeof (kbd_magic_prefix) + 1]; | |
299 | char *suffix; | |
300 | char *kbd_magic_keys; | |
301 | ||
302 | /* | |
303 | * The following string defines the characters that can be appended | |
304 | * to "key_magic" to form the names of environment variables that | |
305 | * hold "magic" key codes, i. e. such key codes that can cause | |
306 | * pre-boot actions. If the string is empty (""), then only | |
307 | * "key_magic" is checked (old behaviour); the string "125" causes | |
308 | * checks for "key_magic1", "key_magic2" and "key_magic5", etc. | |
309 | */ | |
310 | if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) | |
311 | kbd_magic_keys = ""; | |
312 | ||
313 | /* loop over all magic keys; | |
314 | * use '\0' suffix in case of empty string | |
315 | */ | |
316 | for (suffix = kbd_magic_keys; *suffix || | |
317 | suffix == kbd_magic_keys; ++suffix) { | |
318 | sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); | |
319 | if (compare_magic (kbd_data, getenv (magic)) == 0) { | |
320 | char cmd_name[sizeof (kbd_command_prefix) + 1]; | |
321 | char *cmd; | |
322 | ||
323 | sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); | |
324 | cmd = getenv (cmd_name); | |
325 | ||
326 | return (cmd); | |
327 | } | |
328 | } | |
329 | return (NULL); | |
330 | } | |
331 | ||
332 | #endif /* CONFIG_PREBOOT */ | |
333 | ||
334 | static int pcs440ep_readinputs (void) | |
335 | { | |
336 | int i; | |
337 | char value[20]; | |
338 | ||
339 | /* read the inputs and set the Envvars */ | |
340 | /* Revision Level Bit 26 - 29 */ | |
341 | i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2); | |
342 | i = swapbits[i]; | |
343 | sprintf (value, "%02x", i); | |
344 | setenv (ENV_NAME_REVLEV, value); | |
345 | /* Solder Switch Bit 30 - 33 */ | |
346 | i = (in32 (GPIO0_IR) & 0x00000003) << 2; | |
347 | i += (in32 (GPIO1_IR) & 0xc0000000) >> 30; | |
348 | i = swapbits[i]; | |
349 | sprintf (value, "%02x", i); | |
350 | setenv (ENV_NAME_SOLDER, value); | |
351 | /* DIP Switch Bit 49 - 56 */ | |
352 | i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7); | |
353 | i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4]; | |
354 | sprintf (value, "%02x", i); | |
355 | setenv (ENV_NAME_DIP, value); | |
356 | return 0; | |
357 | } | |
358 | ||
359 | ||
360 | #if defined(CONFIG_SHA1_CHECK_UB_IMG) | |
361 | /************************************************************************* | |
362 | * calculate a SHA1 sum for the U-Boot image in Flash. | |
363 | * | |
364 | ************************************************************************/ | |
365 | static int pcs440ep_sha1 (int docheck) | |
366 | { | |
367 | unsigned char *data; | |
368 | unsigned char *ptroff; | |
369 | unsigned char output[20]; | |
370 | unsigned char org[20]; | |
371 | int i, len = CONFIG_SHA1_LEN; | |
372 | ||
373 | memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len); | |
374 | data = (unsigned char *)CFG_LOAD_ADDR; | |
375 | ptroff = &data[len + SHA1_SUM_POS]; | |
376 | ||
377 | for (i = 0; i < SHA1_SUM_LEN; i++) { | |
378 | org[i] = ptroff[i]; | |
379 | ptroff[i] = 0; | |
380 | } | |
381 | ||
382 | sha1_csum ((unsigned char *) data, len, (unsigned char *)output); | |
383 | ||
384 | if (docheck == 2) { | |
385 | for (i = 0; i < 20 ; i++) { | |
386 | printf("%02X ", output[i]); | |
387 | } | |
388 | printf("\n"); | |
389 | } | |
390 | if (docheck == 1) { | |
391 | for (i = 0; i < 20 ; i++) { | |
392 | if (org[i] != output[i]) return 1; | |
393 | } | |
394 | } | |
395 | return 0; | |
396 | } | |
397 | ||
398 | /************************************************************************* | |
399 | * do some checks after the SHA1 checksum from the U-Boot Image was | |
400 | * calculated. | |
401 | * | |
402 | ************************************************************************/ | |
403 | static void pcs440ep_checksha1 (void) | |
404 | { | |
405 | int ret; | |
406 | char *cs_test; | |
407 | ||
408 | ret = pcs440ep_sha1 (1); | |
409 | if (ret == 0) return; | |
410 | ||
411 | if ((cs_test = getenv ("cs_test")) == NULL) { | |
412 | /* Env doesnt exist -> hang */ | |
413 | status_led_blink (); | |
414 | hang (); | |
415 | } | |
416 | ||
417 | if (strncmp (cs_test, "off", 3) == 0) { | |
418 | printf ("SHA1 U-Boot sum NOT ok!\n"); | |
419 | setenv ("bootdelay", "-1"); | |
420 | } | |
421 | } | |
422 | #else | |
423 | static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);} | |
424 | #endif | |
425 | ||
a4c8d138 SR |
426 | int misc_init_r (void) |
427 | { | |
428 | uint pbcr; | |
429 | int size_val = 0; | |
430 | ||
431 | /* Re-do sizing to get full correct info */ | |
432 | mtdcr(ebccfga, pb0cr); | |
433 | pbcr = mfdcr(ebccfgd); | |
434 | switch (gd->bd->bi_flashsize) { | |
435 | case 1 << 20: | |
436 | size_val = 0; | |
437 | break; | |
438 | case 2 << 20: | |
439 | size_val = 1; | |
440 | break; | |
441 | case 4 << 20: | |
442 | size_val = 2; | |
443 | break; | |
444 | case 8 << 20: | |
445 | size_val = 3; | |
446 | break; | |
447 | case 16 << 20: | |
448 | size_val = 4; | |
449 | break; | |
450 | case 32 << 20: | |
451 | size_val = 5; | |
452 | break; | |
453 | case 64 << 20: | |
454 | size_val = 6; | |
455 | break; | |
456 | case 128 << 20: | |
457 | size_val = 7; | |
458 | break; | |
459 | } | |
460 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); | |
461 | mtdcr(ebccfga, pb0cr); | |
462 | mtdcr(ebccfgd, pbcr); | |
463 | ||
464 | /* adjust flash start and offset */ | |
465 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
466 | gd->bd->bi_flashoffset = 0; | |
467 | ||
468 | /* Monitor protection ON by default */ | |
469 | (void)flash_protect(FLAG_PROTECT_SET, | |
470 | -CFG_MONITOR_LEN, | |
471 | 0xffffffff, | |
472 | &flash_info[1]); | |
473 | ||
474 | /* Env protection ON by default */ | |
475 | (void)flash_protect(FLAG_PROTECT_SET, | |
476 | CFG_ENV_ADDR_REDUND, | |
477 | CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, | |
4526c87e | 478 | &flash_info[1]); |
a4c8d138 | 479 | |
566a494f HS |
480 | pcs440ep_readinputs (); |
481 | pcs440ep_checksha1 (); | |
482 | #ifdef CONFIG_PREBOOT | |
483 | { | |
484 | struct kbd_data_t kbd_data; | |
485 | /* Decode keys */ | |
486 | char *str = strdup (key_match (get_keys (&kbd_data))); | |
487 | /* Set or delete definition */ | |
488 | setenv ("preboot", str); | |
489 | free (str); | |
490 | } | |
491 | #endif /* CONFIG_PREBOOT */ | |
a4c8d138 SR |
492 | return 0; |
493 | } | |
494 | ||
495 | int checkboard(void) | |
496 | { | |
497 | char *s = getenv("serial#"); | |
498 | ||
499 | printf("Board: PCS440EP"); | |
500 | if (s != NULL) { | |
501 | puts(", serial# "); | |
502 | puts(s); | |
503 | } | |
504 | putc('\n'); | |
505 | ||
506 | return (0); | |
507 | } | |
508 | ||
566a494f HS |
509 | |
510 | #if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG) | |
511 | void spd_ddr_init_hang (void) | |
512 | { | |
513 | status_led_set (0, STATUS_LED_OFF); | |
514 | status_led_set (1, STATUS_LED_ON); | |
515 | /* we cannot use hang() because we are still running from | |
516 | Flash, and so the status_led driver is not initialized */ | |
517 | puts ("### ERROR ### Please RESET the board ###\n"); | |
518 | for (;;) { | |
519 | __led_toggle (4); | |
520 | udelay (100000); | |
521 | } | |
522 | } | |
523 | #endif | |
524 | ||
a4c8d138 SR |
525 | long int initdram (int board_type) |
526 | { | |
527 | long dram_size = 0; | |
528 | ||
566a494f HS |
529 | status_led_set (0, STATUS_LED_ON); |
530 | status_led_set (1, STATUS_LED_OFF); | |
a4c8d138 | 531 | dram_size = spd_sdram(); |
566a494f HS |
532 | status_led_set (0, STATUS_LED_OFF); |
533 | status_led_set (1, STATUS_LED_ON); | |
534 | if (dram_size == 0) { | |
535 | hang(); | |
536 | } | |
a4c8d138 SR |
537 | |
538 | return dram_size; | |
539 | } | |
540 | ||
541 | #if defined(CFG_DRAM_TEST) | |
542 | int testdram(void) | |
543 | { | |
544 | unsigned long *mem = (unsigned long *)0; | |
545 | const unsigned long kend = (1024 / sizeof(unsigned long)); | |
546 | unsigned long k, n; | |
547 | ||
548 | mtmsr(0); | |
549 | ||
550 | for (k = 0; k < CFG_KBYTES_SDRAM; | |
551 | ++k, mem += (1024 / sizeof(unsigned long))) { | |
552 | if ((k & 1023) == 0) { | |
553 | printf("%3d MB\r", k / 1024); | |
554 | } | |
555 | ||
556 | memset(mem, 0xaaaaaaaa, 1024); | |
557 | for (n = 0; n < kend; ++n) { | |
558 | if (mem[n] != 0xaaaaaaaa) { | |
559 | printf("SDRAM test fails at: %08x\n", | |
560 | (uint) & mem[n]); | |
561 | return 1; | |
562 | } | |
563 | } | |
564 | ||
565 | memset(mem, 0x55555555, 1024); | |
566 | for (n = 0; n < kend; ++n) { | |
567 | if (mem[n] != 0x55555555) { | |
568 | printf("SDRAM test fails at: %08x\n", | |
569 | (uint) & mem[n]); | |
570 | return 1; | |
571 | } | |
572 | } | |
573 | } | |
574 | printf("SDRAM test passes\n"); | |
575 | return 0; | |
576 | } | |
577 | #endif | |
578 | ||
579 | /************************************************************************* | |
580 | * pci_pre_init | |
581 | * | |
582 | * This routine is called just prior to registering the hose and gives | |
583 | * the board the opportunity to check things. Returning a value of zero | |
584 | * indicates that things are bad & PCI initialization should be aborted. | |
585 | * | |
586 | * Different boards may wish to customize the pci controller structure | |
587 | * (add regions, override default access routines, etc) or perform | |
588 | * certain pre-initialization actions. | |
589 | * | |
590 | ************************************************************************/ | |
591 | #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) | |
592 | int pci_pre_init(struct pci_controller *hose) | |
593 | { | |
594 | unsigned long addr; | |
595 | ||
596 | /*-------------------------------------------------------------------------+ | |
597 | | Set priority for all PLB3 devices to 0. | |
598 | | Set PLB3 arbiter to fair mode. | |
599 | +-------------------------------------------------------------------------*/ | |
600 | mfsdr(sdr_amp1, addr); | |
601 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
602 | addr = mfdcr(plb3_acr); | |
603 | mtdcr(plb3_acr, addr | 0x80000000); | |
604 | ||
605 | /*-------------------------------------------------------------------------+ | |
606 | | Set priority for all PLB4 devices to 0. | |
607 | +-------------------------------------------------------------------------*/ | |
608 | mfsdr(sdr_amp0, addr); | |
609 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
610 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
611 | mtdcr(plb4_acr, addr); | |
612 | ||
613 | /*-------------------------------------------------------------------------+ | |
614 | | Set Nebula PLB4 arbiter to fair mode. | |
615 | +-------------------------------------------------------------------------*/ | |
616 | /* Segment0 */ | |
617 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
618 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
619 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
620 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
621 | mtdcr(plb0_acr, addr); | |
622 | ||
623 | /* Segment1 */ | |
624 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
625 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
626 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
627 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
628 | mtdcr(plb1_acr, addr); | |
629 | ||
630 | return 1; | |
631 | } | |
632 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ | |
633 | ||
634 | /************************************************************************* | |
635 | * pci_target_init | |
636 | * | |
637 | * The bootstrap configuration provides default settings for the pci | |
638 | * inbound map (PIM). But the bootstrap config choices are limited and | |
639 | * may not be sufficient for a given board. | |
640 | * | |
641 | ************************************************************************/ | |
642 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) | |
643 | void pci_target_init(struct pci_controller *hose) | |
644 | { | |
645 | /*--------------------------------------------------------------------------+ | |
646 | * Set up Direct MMIO registers | |
647 | *--------------------------------------------------------------------------*/ | |
648 | /*--------------------------------------------------------------------------+ | |
649 | | PowerPC440 EP PCI Master configuration. | |
650 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
651 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF | |
652 | | Use byte reversed out routines to handle endianess. | |
653 | | Make this region non-prefetchable. | |
654 | +--------------------------------------------------------------------------*/ | |
655 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
656 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ | |
657 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ | |
658 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
659 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
660 | ||
661 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
662 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ | |
663 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ | |
664 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
665 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
666 | ||
667 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
668 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ | |
669 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
670 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
671 | ||
672 | /*--------------------------------------------------------------------------+ | |
673 | * Set up Configuration registers | |
674 | *--------------------------------------------------------------------------*/ | |
675 | ||
676 | /* Program the board's subsystem id/vendor id */ | |
677 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
678 | CFG_PCI_SUBSYS_VENDORID); | |
679 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); | |
680 | ||
681 | /* Configure command register as bus master */ | |
682 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
683 | ||
684 | /* 240nS PCI clock */ | |
685 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
686 | ||
687 | /* No error reporting */ | |
688 | pci_write_config_word(0, PCI_ERREN, 0); | |
689 | ||
690 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
691 | ||
692 | } | |
693 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ | |
694 | ||
695 | /************************************************************************* | |
696 | * pci_master_init | |
697 | * | |
698 | ************************************************************************/ | |
699 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) | |
700 | void pci_master_init(struct pci_controller *hose) | |
701 | { | |
702 | unsigned short temp_short; | |
703 | ||
704 | /*--------------------------------------------------------------------------+ | |
705 | | Write the PowerPC440 EP PCI Configuration regs. | |
706 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
707 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
708 | +--------------------------------------------------------------------------*/ | |
709 | pci_read_config_word(0, PCI_COMMAND, &temp_short); | |
710 | pci_write_config_word(0, PCI_COMMAND, | |
711 | temp_short | PCI_COMMAND_MASTER | | |
712 | PCI_COMMAND_MEMORY); | |
713 | } | |
714 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ | |
715 | ||
716 | /************************************************************************* | |
717 | * is_pci_host | |
718 | * | |
719 | * This routine is called to determine if a pci scan should be | |
720 | * performed. With various hardware environments (especially cPCI and | |
721 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
722 | * bit in the strap register, or generic host/adapter assumptions. | |
723 | * | |
724 | * Rather than hard-code a bad assumption in the general 440 code, the | |
725 | * 440 pci code requires the board to decide at runtime. | |
726 | * | |
727 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
728 | * | |
729 | * | |
730 | ************************************************************************/ | |
731 | #if defined(CONFIG_PCI) | |
732 | int is_pci_host(struct pci_controller *hose) | |
733 | { | |
734 | /* PCS440EP is always configured as host. */ | |
735 | return (1); | |
736 | } | |
737 | #endif /* defined(CONFIG_PCI) */ | |
738 | ||
739 | /************************************************************************* | |
740 | * hw_watchdog_reset | |
741 | * | |
742 | * This routine is called to reset (keep alive) the watchdog timer | |
743 | * | |
744 | ************************************************************************/ | |
745 | #if defined(CONFIG_HW_WATCHDOG) | |
746 | void hw_watchdog_reset(void) | |
747 | { | |
748 | ||
749 | } | |
750 | #endif | |
566a494f HS |
751 | |
752 | /************************************************************************* | |
753 | * "led" Commando for the U-Boot shell | |
754 | * | |
755 | ************************************************************************/ | |
756 | int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
757 | { | |
758 | int rcode = 0; | |
759 | ulong pattern = 0; | |
760 | ||
761 | pattern = simple_strtoul (argv[1], NULL, 10); | |
762 | if (pattern > 200) { | |
763 | status_led_blink (); | |
764 | hang (); | |
765 | return rcode; | |
766 | } | |
767 | if (pattern > 100) { | |
768 | status_led_blink (); | |
769 | return rcode; | |
770 | } | |
771 | pattern &= 0x0f; | |
772 | set_leds (pattern); | |
773 | return rcode; | |
774 | } | |
775 | ||
776 | U_BOOT_CMD( | |
777 | led, 2, 1, do_led, | |
778 | "led - set the led\n", | |
779 | NULL | |
780 | ); | |
781 | ||
782 | #if defined(CONFIG_SHA1_CHECK_UB_IMG) | |
783 | /************************************************************************* | |
784 | * "sha1" Commando for the U-Boot shell | |
785 | * | |
786 | ************************************************************************/ | |
787 | int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
788 | { | |
789 | int rcode = -1; | |
790 | ||
791 | if (argc < 2) { | |
792 | usage: | |
793 | printf ("Usage:\n%s\n", cmdtp->usage); | |
794 | return 1; | |
795 | } | |
796 | ||
797 | if (argc >= 3) { | |
798 | unsigned char *data; | |
799 | unsigned char output[20]; | |
800 | int len; | |
801 | int i; | |
802 | ||
803 | data = (unsigned char *)simple_strtoul (argv[1], NULL, 16); | |
804 | len = simple_strtoul (argv[2], NULL, 16); | |
805 | sha1_csum (data, len, (unsigned char *)output); | |
806 | printf ("U-Boot sum:\n"); | |
807 | for (i = 0; i < 20 ; i++) { | |
808 | printf ("%02X ", output[i]); | |
809 | } | |
810 | printf ("\n"); | |
811 | if (argc == 4) { | |
812 | data = (unsigned char *)simple_strtoul (argv[3], NULL, 16); | |
813 | memcpy (data, output, 20); | |
814 | } | |
815 | return 0; | |
816 | } | |
817 | if (argc == 2) { | |
818 | char *ptr = argv[1]; | |
819 | if (*ptr != '-') goto usage; | |
820 | ptr++; | |
821 | if ((*ptr == 'c') || (*ptr == 'C')) { | |
822 | rcode = pcs440ep_sha1 (1); | |
823 | printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : ""); | |
824 | } else if ((*ptr == 'p') || (*ptr == 'P')) { | |
825 | rcode = pcs440ep_sha1 (2); | |
826 | } else { | |
827 | rcode = pcs440ep_sha1 (0); | |
828 | } | |
829 | return rcode; | |
830 | } | |
831 | return rcode; | |
832 | } | |
833 | ||
834 | U_BOOT_CMD( | |
835 | sha1, 4, 1, do_sha1, | |
836 | "sha1 - calculate the SHA1 Sum\n", | |
837 | "address len [addr] calculate the SHA1 sum [save at addr]\n" | |
838 | " -p calculate the SHA1 sum from the U-Boot image in flash and print\n" | |
839 | " -c check the U-Boot image in flash\n" | |
840 | ); | |
841 | #endif | |
842 | ||
843 | #ifdef CONFIG_IDE_PREINIT | |
844 | int ide_preinit (void) | |
845 | { | |
846 | /* Set True IDE Mode */ | |
847 | out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000)); | |
848 | out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); | |
849 | out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040)); | |
850 | udelay (100000); | |
851 | return 0; | |
852 | } | |
853 | #endif | |
854 | ||
855 | #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) | |
856 | void ide_set_reset (int idereset) | |
857 | { | |
858 | debug ("ide_reset(%d)\n", idereset); | |
859 | if (idereset == 0) { | |
860 | out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); | |
861 | } else { | |
862 | out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000)); | |
863 | } | |
864 | udelay (10000); | |
865 | } | |
866 | #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ | |
867 |