[people/ms/u-boot.git] / board / pcs440ep / pcs440ep.c

/*
 * (C) Copyright 2006
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/

static void set_leds(int val)
{
	unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
				 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
	out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
}

int board_early_init_f(void)
{
	register uint reg;

	set_leds(0);			/* display boot info counter */

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr(ebccfga, xbcfg);
	reg = mfdcr(ebccfgd);
	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */

	/*--------------------------------------------------------------------
	 * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
	 * via define from board config file.
	 *-------------------------------------------------------------------*/

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000001);	/* UIC1 crit is critical */
	mtdcr(uic0pr, 0xfffffe1f);	/* per ref-board manual */
	mtdcr(uic0tr, 0x01c00000);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	/*--------------------------------------------------------------------
	 * Setup other serial configuration
	 *-------------------------------------------------------------------*/
	mfsdr(sdr_pci0, reg);
	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
	mtsdr(sdr_pfc0, 0x00000100);	/* Pin function: enable GPIO49-63 */
	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins, select IRQ5 */

	return 0;
}

int misc_init_r (void)
{
	uint pbcr;
	int size_val = 0;

	/* Re-do sizing to get full correct info */
	mtdcr(ebccfga, pb0cr);
	pbcr = mfdcr(ebccfgd);
	switch (gd->bd->bi_flashsize) {
	case 1 << 20:
		size_val = 0;
		break;
	case 2 << 20:
		size_val = 1;
		break;
	case 4 << 20:
		size_val = 2;
		break;
	case 8 << 20:
		size_val = 3;
		break;
	case 16 << 20:
		size_val = 4;
		break;
	case 32 << 20:
		size_val = 5;
		break;
	case 64 << 20:
		size_val = 6;
		break;
	case 128 << 20:
		size_val = 7;
		break;
	}
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
	mtdcr(ebccfga, pb0cr);
	mtdcr(ebccfgd, pbcr);

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CFG_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[1]);

	/* Env protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    CFG_ENV_ADDR_REDUND,
			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
			    &flash_info[1]);

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: PCS440EP");
	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

long int initdram (int board_type)
{
	long dram_size = 0;

	set_leds(1);			/* display boot info counter */
	dram_size = spd_sdram();
	set_leds(2);			/* display boot info counter */

	return dram_size;
}

#if defined(CFG_DRAM_TEST)
int testdram(void)
{
	unsigned long *mem = (unsigned long *)0;
	const unsigned long kend = (1024 / sizeof(unsigned long));
	unsigned long k, n;

	mtmsr(0);

	for (k = 0; k < CFG_KBYTES_SDRAM;
	     ++k, mem += (1024 / sizeof(unsigned long))) {
		if ((k & 1023) == 0) {
			printf("%3d MB\r", k / 1024);
		}

		memset(mem, 0xaaaaaaaa, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0xaaaaaaaa) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}

		memset(mem, 0x55555555, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0x55555555) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}
	}
	printf("SDRAM test passes\n");
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
	unsigned long addr;

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB3 devices to 0.
	  | Set PLB3 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp1, addr);
	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb3_acr);
	mtdcr(plb3_acr, addr | 0x80000000);

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB4 devices to 0.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp0, addr);
	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
	mtdcr(plb4_acr, addr);

	/*-------------------------------------------------------------------------+
	  | Set Nebula PLB4 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	/* Segment0 */
	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
	mtdcr(plb0_acr, addr);

	/* Segment1 */
	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
	mtdcr(plb1_acr, addr);

	return 1;
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
	/*--------------------------------------------------------------------------+
	 * Set up Direct MMIO registers
	 *--------------------------------------------------------------------------*/
	/*--------------------------------------------------------------------------+
	  | PowerPC440 EP PCI Master configuration.
	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	  |   Use byte reversed out routines to handle endianess.
	  | Make this region non-prefetchable.
	  +--------------------------------------------------------------------------*/
	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */

	/*--------------------------------------------------------------------------+
	 * Set up Configuration registers
	 *--------------------------------------------------------------------------*/

	/* Program the board's subsystem id/vendor id */
	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
			      CFG_PCI_SUBSYS_VENDORID);
	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);

	/* Configure command register as bus master */
	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);

	/* 240nS PCI clock */
	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);

	/* No error reporting */
	pci_write_config_word(0, PCI_ERREN, 0);

	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);

}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  pci_master_init
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
	unsigned short temp_short;

	/*--------------------------------------------------------------------------+
	  | Write the PowerPC440 EP PCI Configuration regs.
	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
	  +--------------------------------------------------------------------------*/
	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	pci_write_config_word(0, PCI_COMMAND,
			      temp_short | PCI_COMMAND_MASTER |
			      PCI_COMMAND_MEMORY);
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* PCS440EP is always configured as host. */
	return (1);
}
#endif				/* defined(CONFIG_PCI) */

/*************************************************************************
 *  hw_watchdog_reset
 *
 *	This routine is called to reset (keep alive) the watchdog timer
 *
 ************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{

}
#endif
Commit	Line	Data
a4c8d138 SR	1	/*
	2	* (C) Copyright 2006
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <ppc4xx.h>
	26	#include <asm/processor.h>
	27	#include <spd_sdram.h>
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	32
	33	static void set_leds(int val)
	34	{
	35	unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
	36	0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
	37	out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) \| (led[val] << 27));
	38	}
	39
	40	int board_early_init_f(void)
	41	{
	42	register uint reg;
	43
	44	set_leds(0); /* display boot info counter */
	45
	46	/*--------------------------------------------------------------------
	47	* Setup the external bus controller/chip selects
	48	-------------------------------------------------------------------/
	49	mtdcr(ebccfga, xbcfg);
	50	reg = mfdcr(ebccfgd);
	51	mtdcr(ebccfgd, reg \| 0x04000000); /* Set ATC */
	52
	53	/*--------------------------------------------------------------------
	54	* GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
	55	* via define from board config file.
	56	-------------------------------------------------------------------/
	57
	58	/*--------------------------------------------------------------------
	59	* Setup the interrupt controller polarities, triggers, etc.
	60	-------------------------------------------------------------------/
	61	mtdcr(uic0sr, 0xffffffff); /* clear all */
	62	mtdcr(uic0er, 0x00000000); /* disable all */
	63	mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
	64	mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */
65	mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */
66	mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
67	mtdcr(uic0sr, 0xffffffff); /* clear all */
68
69	mtdcr(uic1sr, 0xffffffff); /* clear all */
70	mtdcr(uic1er, 0x00000000); /* disable all */
71	mtdcr(uic1cr, 0x00000000); /* all non-critical */
72	mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
73	mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
74	mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
75	mtdcr(uic1sr, 0xffffffff); /* clear all */
76
77	/*--------------------------------------------------------------------
78	* Setup other serial configuration
79	-------------------------------------------------------------------/
80	mfsdr(sdr_pci0, reg);
81	mtsdr(sdr_pci0, 0x80000000 \| reg); /* PCI arbiter enabled */
82	mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */
83	mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
84
85	return 0;
86	}
87
88	int misc_init_r (void)
89	{
90	uint pbcr;
91	int size_val = 0;
92
93	/* Re-do sizing to get full correct info */
94	mtdcr(ebccfga, pb0cr);
95	pbcr = mfdcr(ebccfgd);
96	switch (gd->bd->bi_flashsize) {
97	case 1 << 20:
98	size_val = 0;
99	break;
100	case 2 << 20:
101	size_val = 1;
102	break;
103	case 4 << 20:
104	size_val = 2;
105	break;
106	case 8 << 20:
107	size_val = 3;
108	break;
109	case 16 << 20:
110	size_val = 4;
111	break;
112	case 32 << 20:
113	size_val = 5;
114	break;
115	case 64 << 20:
116	size_val = 6;
117	break;
118	case 128 << 20:
119	size_val = 7;
120	break;
121	}
122	pbcr = (pbcr & 0x0001ffff) \| gd->bd->bi_flashstart \| (size_val << 17);
123	mtdcr(ebccfga, pb0cr);
124	mtdcr(ebccfgd, pbcr);
125
126	/* adjust flash start and offset */
127	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
128	gd->bd->bi_flashoffset = 0;
129
130	/* Monitor protection ON by default */
131	(void)flash_protect(FLAG_PROTECT_SET,
132	-CFG_MONITOR_LEN,
133	0xffffffff,
134	&flash_info[1]);
135
136	/* Env protection ON by default */
137	(void)flash_protect(FLAG_PROTECT_SET,
138	CFG_ENV_ADDR_REDUND,
139	CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
4526c87e	140	&flash_info[1]);
a4c8d138 SR	141
	142	return 0;
	143	}
	144
	145	int checkboard(void)
	146	{
	147	char *s = getenv("serial#");
	148
	149	printf("Board: PCS440EP");
	150	if (s != NULL) {
	151	puts(", serial# ");
	152	puts(s);
	153	}
	154	putc('\n');
	155
	156	return (0);
	157	}
	158
	159	long int initdram (int board_type)
	160	{
	161	long dram_size = 0;
	162
	163	set_leds(1); /* display boot info counter */
	164	dram_size = spd_sdram();
	165	set_leds(2); /* display boot info counter */
	166
	167	return dram_size;
	168	}
	169
	170	#if defined(CFG_DRAM_TEST)
	171	int testdram(void)
	172	{
	173	unsigned long mem = (unsigned long )0;
	174	const unsigned long kend = (1024 / sizeof(unsigned long));
	175	unsigned long k, n;
	176
	177	mtmsr(0);
	178
	179	for (k = 0; k < CFG_KBYTES_SDRAM;
	180	++k, mem += (1024 / sizeof(unsigned long))) {
	181	if ((k & 1023) == 0) {
	182	printf("%3d MB\r", k / 1024);
	183	}
	184
	185	memset(mem, 0xaaaaaaaa, 1024);
	186	for (n = 0; n < kend; ++n) {
	187	if (mem[n] != 0xaaaaaaaa) {
	188	printf("SDRAM test fails at: %08x\n",
	189	(uint) & mem[n]);
	190	return 1;
	191	}
	192	}
	193
	194	memset(mem, 0x55555555, 1024);
	195	for (n = 0; n < kend; ++n) {
	196	if (mem[n] != 0x55555555) {
	197	printf("SDRAM test fails at: %08x\n",
	198	(uint) & mem[n]);
	199	return 1;
	200	}
	201	}
	202	}
	203	printf("SDRAM test passes\n");
	204	return 0;
205	}
206	#endif
207
208	/*************************************************************************
209	* pci_pre_init
210	*
211	* This routine is called just prior to registering the hose and gives
212	* the board the opportunity to check things. Returning a value of zero
213	* indicates that things are bad & PCI initialization should be aborted.
214	*
215	* Different boards may wish to customize the pci controller structure
216	* (add regions, override default access routines, etc) or perform
217	* certain pre-initialization actions.
218	*
219	************************************************************************/
220	#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
221	int pci_pre_init(struct pci_controller *hose)
222	{
223	unsigned long addr;
224
225	/*-------------------------------------------------------------------------+
226	\| Set priority for all PLB3 devices to 0.
227	\| Set PLB3 arbiter to fair mode.
228	+-------------------------------------------------------------------------*/
229	mfsdr(sdr_amp1, addr);
230	mtsdr(sdr_amp1, (addr & 0x000000FF) \| 0x0000FF00);
231	addr = mfdcr(plb3_acr);
232	mtdcr(plb3_acr, addr \| 0x80000000);
233
234	/*-------------------------------------------------------------------------+
235	\| Set priority for all PLB4 devices to 0.
236	+-------------------------------------------------------------------------*/
237	mfsdr(sdr_amp0, addr);
238	mtsdr(sdr_amp0, (addr & 0x000000FF) \| 0x0000FF00);
239	addr = mfdcr(plb4_acr) \| 0xa0000000; /* Was 0x8---- */
240	mtdcr(plb4_acr, addr);
241
242	/*-------------------------------------------------------------------------+
243	\| Set Nebula PLB4 arbiter to fair mode.
244	+-------------------------------------------------------------------------*/
245	/* Segment0 */
246	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) \| plb0_acr_ppm_fair;
247	addr = (addr & ~plb0_acr_hbu_mask) \| plb0_acr_hbu_enabled;
248	addr = (addr & ~plb0_acr_rdp_mask) \| plb0_acr_rdp_4deep;
249	addr = (addr & ~plb0_acr_wrp_mask) \| plb0_acr_wrp_2deep;
250	mtdcr(plb0_acr, addr);
251
252	/* Segment1 */
253	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) \| plb1_acr_ppm_fair;
254	addr = (addr & ~plb1_acr_hbu_mask) \| plb1_acr_hbu_enabled;
255	addr = (addr & ~plb1_acr_rdp_mask) \| plb1_acr_rdp_4deep;
256	addr = (addr & ~plb1_acr_wrp_mask) \| plb1_acr_wrp_2deep;
257	mtdcr(plb1_acr, addr);
258
259	return 1;
260	}
261	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
262
263	/*************************************************************************
264	* pci_target_init
265	*
266	* The bootstrap configuration provides default settings for the pci
267	* inbound map (PIM). But the bootstrap config choices are limited and
268	* may not be sufficient for a given board.
269	*
270	************************************************************************/
271	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
272	void pci_target_init(struct pci_controller *hose)
273	{
274	/*--------------------------------------------------------------------------+
275	* Set up Direct MMIO registers
276	--------------------------------------------------------------------------/
277	/*--------------------------------------------------------------------------+
278	\| PowerPC440 EP PCI Master configuration.
279	\| Map one 1Gig range of PLB/processor addresses to PCI memory space.
280	\| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
281	\| Use byte reversed out routines to handle endianess.
282	\| Make this region non-prefetchable.
283	+--------------------------------------------------------------------------*/
284	out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
285	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
286	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
287	out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
288	out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
289
290	out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
291	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
292	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
293	out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
294	out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
295
296	out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
297	out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
298	out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
299	out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
300
301	/*--------------------------------------------------------------------------+
302	* Set up Configuration registers
303	--------------------------------------------------------------------------/
304
305	/* Program the board's subsystem id/vendor id */
306	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
307	CFG_PCI_SUBSYS_VENDORID);
308	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
309
310	/* Configure command register as bus master */
311	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
312
313	/* 240nS PCI clock */
314	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
315
316	/* No error reporting */
317	pci_write_config_word(0, PCI_ERREN, 0);
318
319	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
320
321	}
322	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
323
324	/*************************************************************************
325	* pci_master_init
326	*
327	************************************************************************/
328	#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
329	void pci_master_init(struct pci_controller *hose)
330	{
331	unsigned short temp_short;
332
333	/*--------------------------------------------------------------------------+
334	\| Write the PowerPC440 EP PCI Configuration regs.
335	\| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
336	\| Enable PowerPC440 EP to act as a PCI memory target (PTM).
337	+--------------------------------------------------------------------------*/
338	pci_read_config_word(0, PCI_COMMAND, &temp_short);
339	pci_write_config_word(0, PCI_COMMAND,
340	temp_short \| PCI_COMMAND_MASTER \|
341	PCI_COMMAND_MEMORY);
342	}
343	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
344
345	/*************************************************************************
346	* is_pci_host
347	*
348	* This routine is called to determine if a pci scan should be
349	* performed. With various hardware environments (especially cPCI and
350	* PPMC) it's insufficient to depend on the state of the arbiter enable
351	* bit in the strap register, or generic host/adapter assumptions.
352	*
353	* Rather than hard-code a bad assumption in the general 440 code, the
354	* 440 pci code requires the board to decide at runtime.
355	*
356	* Return 0 for adapter mode, non-zero for host (monarch) mode.
357	*
358	*
359	************************************************************************/
360	#if defined(CONFIG_PCI)
361	int is_pci_host(struct pci_controller *hose)
362	{
363	/* PCS440EP is always configured as host. */
364	return (1);
365	}
366	#endif /* defined(CONFIG_PCI) */
367
368	/*************************************************************************
369	* hw_watchdog_reset
370	*
371	* This routine is called to reset (keep alive) the watchdog timer
372	*
373	************************************************************************/
374	#if defined(CONFIG_HW_WATCHDOG)
375	void hw_watchdog_reset(void)
376	{
377
378	}
379	#endif