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efa329cb WD |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
49822e23 WD |
5 | * (C) Copyright 2004 |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
efa329cb WD |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <mpc5xxx.h> | |
13 | #include <pci.h> | |
19403633 | 14 | #include <netdev.h> |
efa329cb | 15 | |
49822e23 WD |
16 | #if defined(CONFIG_MPC5200_DDR) |
17 | #include "mt46v16m16-75.h" | |
18 | #else | |
19 | #include "mt48lc16m16a2-75.h" | |
20 | #endif | |
efa329cb | 21 | |
d87080b7 WD |
22 | DECLARE_GLOBAL_DATA_PTR; |
23 | ||
6d0f6bcf | 24 | #ifndef CONFIG_SYS_RAMBOOT |
efa329cb WD |
25 | static void sdram_start (int hi_addr) |
26 | { | |
27 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
28 | ||
29 | /* unlock mode register */ | |
49822e23 WD |
30 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
31 | __asm__ volatile ("sync"); | |
32 | ||
efa329cb | 33 | /* precharge all banks */ |
49822e23 WD |
34 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
35 | __asm__ volatile ("sync"); | |
36 | ||
37 | #if SDRAM_DDR | |
38 | /* set mode register: extended mode */ | |
39 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; | |
40 | __asm__ volatile ("sync"); | |
41 | ||
42 | /* set mode register: reset DLL */ | |
43 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; | |
44 | __asm__ volatile ("sync"); | |
efa329cb | 45 | #endif |
49822e23 | 46 | |
efa329cb | 47 | /* precharge all banks */ |
49822e23 WD |
48 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
49 | __asm__ volatile ("sync"); | |
50 | ||
efa329cb | 51 | /* auto refresh */ |
49822e23 WD |
52 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
53 | __asm__ volatile ("sync"); | |
54 | ||
efa329cb | 55 | /* set mode register */ |
49822e23 WD |
56 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
57 | __asm__ volatile ("sync"); | |
58 | ||
efa329cb | 59 | /* normal operation */ |
49822e23 WD |
60 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
61 | __asm__ volatile ("sync"); | |
efa329cb WD |
62 | } |
63 | #endif | |
64 | ||
49822e23 WD |
65 | /* |
66 | * ATTENTION: Although partially referenced initdram does NOT make real use | |
6d0f6bcf | 67 | * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE |
49822e23 WD |
68 | * is something else than 0x00000000. |
69 | */ | |
70 | ||
9973e3c6 | 71 | phys_size_t initdram (int board_type) |
efa329cb WD |
72 | { |
73 | ulong dramsize = 0; | |
49822e23 | 74 | ulong dramsize2 = 0; |
6d0f6bcf | 75 | #ifndef CONFIG_SYS_RAMBOOT |
efa329cb WD |
76 | ulong test1, test2; |
77 | ||
49822e23 | 78 | /* setup SDRAM chip selects */ |
efa329cb WD |
79 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ |
80 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ | |
49822e23 | 81 | __asm__ volatile ("sync"); |
efa329cb WD |
82 | |
83 | /* setup config registers */ | |
49822e23 WD |
84 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
85 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; | |
86 | __asm__ volatile ("sync"); | |
87 | ||
88 | #if SDRAM_DDR | |
89 | /* set tap delay */ | |
90 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; | |
91 | __asm__ volatile ("sync"); | |
92 | #endif | |
93 | ||
94 | /* find RAM size using SDRAM CS0 only */ | |
95 | sdram_start(0); | |
6d0f6bcf | 96 | test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); |
49822e23 | 97 | sdram_start(1); |
6d0f6bcf | 98 | test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); |
49822e23 WD |
99 | if (test1 > test2) { |
100 | sdram_start(0); | |
101 | dramsize = test1; | |
102 | } else { | |
103 | dramsize = test2; | |
104 | } | |
105 | ||
106 | /* memory smaller than 1MB is impossible */ | |
107 | if (dramsize < (1 << 20)) { | |
108 | dramsize = 0; | |
109 | } | |
110 | ||
111 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
112 | if (dramsize > 0) { | |
113 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; | |
114 | } else { | |
115 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ | |
116 | } | |
117 | ||
118 | /* let SDRAM CS1 start right after CS0 */ | |
119 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ | |
120 | ||
121 | /* find RAM size using SDRAM CS1 only */ | |
07cc0999 | 122 | if (!dramsize) |
a6310928 | 123 | sdram_start(0); |
6d0f6bcf | 124 | test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); |
a6310928 WD |
125 | if (!dramsize) { |
126 | sdram_start(1); | |
6d0f6bcf | 127 | test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); |
a6310928 | 128 | } |
49822e23 WD |
129 | if (test1 > test2) { |
130 | sdram_start(0); | |
131 | dramsize2 = test1; | |
132 | } else { | |
133 | dramsize2 = test2; | |
134 | } | |
135 | ||
136 | /* memory smaller than 1MB is impossible */ | |
137 | if (dramsize2 < (1 << 20)) { | |
138 | dramsize2 = 0; | |
139 | } | |
140 | ||
141 | /* set SDRAM CS1 size according to the amount of RAM found */ | |
142 | if (dramsize2 > 0) { | |
143 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize | |
144 | | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); | |
145 | } else { | |
146 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ | |
147 | } | |
148 | ||
6d0f6bcf | 149 | #else /* CONFIG_SYS_RAMBOOT */ |
49822e23 WD |
150 | |
151 | /* retrieve size of memory connected to SDRAM CS0 */ | |
152 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; | |
153 | if (dramsize >= 0x13) { | |
154 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
155 | } else { | |
156 | dramsize = 0; | |
157 | } | |
158 | ||
159 | /* retrieve size of memory connected to SDRAM CS1 */ | |
160 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; | |
161 | if (dramsize2 >= 0x13) { | |
162 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | |
163 | } else { | |
164 | dramsize2 = 0; | |
165 | } | |
166 | ||
6d0f6bcf | 167 | #endif /* CONFIG_SYS_RAMBOOT */ |
49822e23 WD |
168 | |
169 | return dramsize + dramsize2; | |
170 | } | |
efa329cb | 171 | |
efa329cb WD |
172 | int checkboard (void) |
173 | { | |
efa329cb | 174 | puts ("Board: MicroSys PM520 \n"); |
efa329cb WD |
175 | return 0; |
176 | } | |
177 | ||
178 | void flash_preinit(void) | |
179 | { | |
180 | /* | |
181 | * Now, when we are in RAM, enable flash write | |
182 | * access for detection process. | |
183 | * Note that CS_BOOT cannot be cleared when | |
184 | * executing in flash. | |
185 | */ | |
efa329cb WD |
186 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
187 | } | |
188 | ||
49822e23 | 189 | void flash_afterinit(ulong start, ulong size) |
efa329cb | 190 | { |
49822e23 WD |
191 | #if defined(CONFIG_BOOT_ROM) |
192 | /* adjust mapping */ | |
193 | *(vu_long *)MPC5XXX_CS1_START = | |
194 | START_REG(start); | |
195 | *(vu_long *)MPC5XXX_CS1_STOP = | |
196 | STOP_REG(start, size); | |
197 | #else | |
198 | /* adjust mapping */ | |
199 | *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = | |
200 | START_REG(start); | |
201 | *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = | |
202 | STOP_REG(start, size); | |
203 | #endif | |
204 | } | |
205 | ||
206 | ||
207 | extern flash_info_t flash_info[]; /* info for FLASH chips */ | |
208 | ||
209 | int misc_init_r (void) | |
210 | { | |
49822e23 WD |
211 | /* adjust flash start */ |
212 | gd->bd->bi_flashstart = flash_info[0].start[0]; | |
213 | return (0); | |
efa329cb WD |
214 | } |
215 | ||
216 | #ifdef CONFIG_PCI | |
217 | static struct pci_controller hose; | |
218 | ||
219 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
220 | ||
221 | void pci_init_board(void) | |
222 | { | |
223 | pci_mpc5xxx_init(&hose); | |
224 | } | |
225 | #endif | |
49822e23 | 226 | |
d39b5741 | 227 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
49822e23 WD |
228 | |
229 | void init_ide_reset (void) | |
230 | { | |
231 | debug ("init_ide_reset\n"); | |
232 | ||
233 | } | |
234 | ||
235 | void ide_set_reset (int idereset) | |
236 | { | |
237 | debug ("ide_reset(%d)\n", idereset); | |
238 | ||
239 | } | |
d39b5741 | 240 | #endif |
49822e23 | 241 | |
3fe00109 | 242 | #if defined(CONFIG_CMD_DOC) |
49822e23 WD |
243 | void doc_init (void) |
244 | { | |
6d0f6bcf | 245 | doc_probe (CONFIG_SYS_DOC_BASE); |
49822e23 WD |
246 | } |
247 | #endif | |
19403633 BW |
248 | |
249 | int board_eth_init(bd_t *bis) | |
250 | { | |
e1d7480b | 251 | cpu_eth_init(bis); /* Built in FEC comes first */ |
19403633 BW |
252 | return pci_eth_init(bis); |
253 | } |