[people/ms/u-boot.git] / board / pm520 / pm520.c

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <netdev.h>

#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m16a2-75.h"
#endif

DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *            is something else than 0x00000000.
 */

#if defined(CONFIG_MPC5200)
phys_size_t initdram (int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else {
		dramsize2 = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20)) {
		dramsize2 = 0;
	}

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CONFIG_SYS_RAMBOOT */

	return dramsize + dramsize2;
}

#elif defined(CONFIG_MGT5100)

phys_size_t initdram (int board_type)
{
	ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup and enable SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;

	/* address select register */
	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
	__asm__ volatile ("sync");

	/* find RAM size */
	sdram_start(0);
	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* set SDRAM end address according to size */
	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);

#else /* CONFIG_SYS_RAMBOOT */

	/* Retrieve amount of SDRAM available */
	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);

#endif /* CONFIG_SYS_RAMBOOT */

	return dramsize;
}

#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

int checkboard (void)
{
#if defined(CONFIG_MPC5200)
	puts ("Board: MicroSys PM520 \n");
#elif defined(CONFIG_MGT5100)
	puts ("Board: MicroSys PM510 \n");
#endif
	return 0;
}

void flash_preinit(void)
{
	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
#if defined(CONFIG_MGT5100)
	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
#endif
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}

void flash_afterinit(ulong start, ulong size)
{
#if defined(CONFIG_BOOT_ROM)
	/* adjust mapping */
	*(vu_long *)MPC5XXX_CS1_START =
			START_REG(start);
	*(vu_long *)MPC5XXX_CS1_STOP =
			STOP_REG(start, size);
#else
	/* adjust mapping */
	*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
			START_REG(start);
	*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
			STOP_REG(start, size);
#endif
}


extern flash_info_t flash_info[];	/* info for FLASH chips */

int misc_init_r (void)
{
	/* adjust flash start */
	gd->bd->bi_flashstart = flash_info[0].start[0];
	return (0);
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)

void init_ide_reset (void)
{
	debug ("init_ide_reset\n");

}

void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

}
#endif

#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
	doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif

int board_eth_init(bd_t *bis)
{
	cpu_eth_init(bis); /* Built in FEC comes first */
	return pci_eth_init(bis);
}
Commit	Line	Data
efa329cb WD	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
49822e23 WD	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
efa329cb WD	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <mpc5xxx.h>
	29	#include <pci.h>
19403633	30	#include <netdev.h>
efa329cb	31
49822e23 WD	32	#if defined(CONFIG_MPC5200_DDR)
	33	#include "mt46v16m16-75.h"
	34	#else
	35	#include "mt48lc16m16a2-75.h"
	36	#endif
efa329cb	37
d87080b7 WD	38	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	39
6d0f6bcf	40	#ifndef CONFIG_SYS_RAMBOOT
efa329cb WD	41	static void sdram_start (int hi_addr)
	42	{
	43	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	44
	45	/* unlock mode register */
49822e23 WD	46	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	47	__asm__ volatile ("sync");
	48
efa329cb	49	/* precharge all banks */
49822e23 WD	50	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	51	__asm__ volatile ("sync");
	52
	53	#if SDRAM_DDR
	54	/* set mode register: extended mode */
	55	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	56	__asm__ volatile ("sync");
	57
	58	/* set mode register: reset DLL */
	59	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	60	__asm__ volatile ("sync");
efa329cb	61	#endif
49822e23	62
efa329cb	63	/* precharge all banks */
49822e23 WD	64	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	65	__asm__ volatile ("sync");
	66
efa329cb	67	/* auto refresh */
49822e23 WD	68	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	69	__asm__ volatile ("sync");
	70
efa329cb	71	/* set mode register */
49822e23 WD	72	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	73	__asm__ volatile ("sync");
	74
efa329cb	75	/* normal operation */
49822e23 WD	76	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
49822e23 WD	77	__asm__ volatile ("sync");
efa329cb WD	78	}
	79	#endif
	80
49822e23 WD	81	/*
49822e23 WD	82	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	83	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
49822e23 WD	84	* is something else than 0x00000000.
	85	*/
	86
	87	#if defined(CONFIG_MPC5200)
9973e3c6	88	phys_size_t initdram (int board_type)
efa329cb WD	89	{
efa329cb WD	90	ulong dramsize = 0;
49822e23	91	ulong dramsize2 = 0;
6d0f6bcf	92	#ifndef CONFIG_SYS_RAMBOOT
efa329cb WD	93	ulong test1, test2;
efa329cb WD	94
49822e23	95	/* setup SDRAM chip selects */
efa329cb WD	96	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
efa329cb WD	97	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
49822e23	98	__asm__ volatile ("sync");
efa329cb WD	99
efa329cb WD	100	/* setup config registers */
49822e23 WD	101	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	102	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	103	__asm__ volatile ("sync");
	104
	105	#if SDRAM_DDR
	106	/* set tap delay */
	107	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	108	__asm__ volatile ("sync");
	109	#endif
	110
	111	/* find RAM size using SDRAM CS0 only */
	112	sdram_start(0);
6d0f6bcf	113	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
49822e23	114	sdram_start(1);
6d0f6bcf	115	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
49822e23 WD	116	if (test1 > test2) {
	117	sdram_start(0);
	118	dramsize = test1;
	119	} else {
	120	dramsize = test2;
	121	}
	122
	123	/* memory smaller than 1MB is impossible */
	124	if (dramsize < (1 << 20)) {
	125	dramsize = 0;
	126	}
	127
	128	/* set SDRAM CS0 size according to the amount of RAM found */
	129	if (dramsize > 0) {
	130	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	131	} else {
	132	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	133	}
	134
	135	/* let SDRAM CS1 start right after CS0 */
	136	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
	137
	138	/* find RAM size using SDRAM CS1 only */
07cc0999	139	if (!dramsize)
a6310928	140	sdram_start(0);
6d0f6bcf	141	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
a6310928 WD	142	if (!dramsize) {
a6310928 WD	143	sdram_start(1);
6d0f6bcf	144	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
a6310928	145	}
49822e23 WD	146	if (test1 > test2) {
	147	sdram_start(0);
	148	dramsize2 = test1;
	149	} else {
	150	dramsize2 = test2;
	151	}
	152
	153	/* memory smaller than 1MB is impossible */
	154	if (dramsize2 < (1 << 20)) {
	155	dramsize2 = 0;
	156	}
	157
	158	/* set SDRAM CS1 size according to the amount of RAM found */
	159	if (dramsize2 > 0) {
	160	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	161	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	162	} else {
	163	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	164	}
	165
6d0f6bcf	166	#else /* CONFIG_SYS_RAMBOOT */
49822e23 WD	167
	168	/* retrieve size of memory connected to SDRAM CS0 */
	169	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	170	if (dramsize >= 0x13) {
	171	dramsize = (1 << (dramsize - 0x13)) << 20;
	172	} else {
	173	dramsize = 0;
	174	}
	175
	176	/* retrieve size of memory connected to SDRAM CS1 */
	177	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	178	if (dramsize2 >= 0x13) {
	179	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	180	} else {
	181	dramsize2 = 0;
	182	}
	183
6d0f6bcf	184	#endif /* CONFIG_SYS_RAMBOOT */
49822e23 WD	185
	186	return dramsize + dramsize2;
	187	}
efa329cb WD	188
efa329cb WD	189	#elif defined(CONFIG_MGT5100)
49822e23	190
9973e3c6	191	phys_size_t initdram (int board_type)
49822e23 WD	192	{
49822e23 WD	193	ulong dramsize = 0;
6d0f6bcf	194	#ifndef CONFIG_SYS_RAMBOOT
49822e23 WD	195	ulong test1, test2;
	196
	197	/* setup and enable SDRAM chip selects */
efa329cb WD	198	(vu_long )MPC5XXX_SDRAM_START = 0x00000000;
	199	(vu_long )MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
	200	(vu_long )MPC5XXX_ADDECR \|= (1 << 22); /* Enable SDRAM */
49822e23	201	__asm__ volatile ("sync");
efa329cb WD	202
efa329cb WD	203	/* setup config registers */
49822e23 WD	204	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
49822e23 WD	205	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
efa329cb WD	206
efa329cb WD	207	/* address select register */
49822e23 WD	208	(vu_long )MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
	209	__asm__ volatile ("sync");
	210
	211	/* find RAM size */
efa329cb	212	sdram_start(0);
6d0f6bcf	213	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
efa329cb	214	sdram_start(1);
6d0f6bcf	215	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
efa329cb WD	216	if (test1 > test2) {
	217	sdram_start(0);
	218	dramsize = test1;
	219	} else {
	220	dramsize = test2;
	221	}
49822e23 WD	222
49822e23 WD	223	/* set SDRAM end address according to size */
efa329cb	224	(vu_long )MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
efa329cb	225
6d0f6bcf	226	#else /* CONFIG_SYS_RAMBOOT */
49822e23 WD	227
49822e23 WD	228	/* Retrieve amount of SDRAM available */
efa329cb	229	dramsize = (((vu_long )MPC5XXX_SDRAM_STOP + 1) << 15);
49822e23	230
6d0f6bcf	231	#endif /* CONFIG_SYS_RAMBOOT */
49822e23	232
efa329cb WD	233	return dramsize;
	234	}
	235
49822e23 WD	236	#else
	237	#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
	238	#endif
	239
efa329cb WD	240	int checkboard (void)
	241	{
	242	#if defined(CONFIG_MPC5200)
	243	puts ("Board: MicroSys PM520 \n");
	244	#elif defined(CONFIG_MGT5100)
	245	puts ("Board: MicroSys PM510 \n");
	246	#endif
	247	return 0;
	248	}
	249
	250	void flash_preinit(void)
	251	{
	252	/*
	253	* Now, when we are in RAM, enable flash write
	254	* access for detection process.
	255	* Note that CS_BOOT cannot be cleared when
	256	* executing in flash.
	257	*/
	258	#if defined(CONFIG_MGT5100)
	259	(vu_long )MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
	260	(vu_long )MPC5XXX_ADDECR \|= (1 << 16); /* enable CS0 */
	261	#endif
	262	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	263	}
	264
49822e23	265	void flash_afterinit(ulong start, ulong size)
efa329cb	266	{
49822e23 WD	267	#if defined(CONFIG_BOOT_ROM)
	268	/* adjust mapping */
	269	(vu_long )MPC5XXX_CS1_START =
	270	START_REG(start);
	271	(vu_long )MPC5XXX_CS1_STOP =
	272	STOP_REG(start, size);
	273	#else
	274	/* adjust mapping */
	275	(vu_long )MPC5XXX_BOOTCS_START = (vu_long )MPC5XXX_CS0_START =
	276	START_REG(start);
	277	(vu_long )MPC5XXX_BOOTCS_STOP = (vu_long )MPC5XXX_CS0_STOP =
	278	STOP_REG(start, size);
	279	#endif
	280	}
	281
	282
	283	extern flash_info_t flash_info[]; /* info for FLASH chips */
	284
	285	int misc_init_r (void)
	286	{
49822e23 WD	287	/* adjust flash start */
	288	gd->bd->bi_flashstart = flash_info[0].start[0];
	289	return (0);
efa329cb WD	290	}
	291
	292	#ifdef CONFIG_PCI
	293	static struct pci_controller hose;
	294
	295	extern void pci_mpc5xxx_init(struct pci_controller *);
	296
	297	void pci_init_board(void)
	298	{
	299	pci_mpc5xxx_init(&hose);
	300	}
	301	#endif
49822e23	302
d39b5741	303	#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
49822e23 WD	304
	305	void init_ide_reset (void)
	306	{
	307	debug ("init_ide_reset\n");
	308
	309	}
	310
	311	void ide_set_reset (int idereset)
	312	{
	313	debug ("ide_reset(%d)\n", idereset);
	314
	315	}
d39b5741	316	#endif
49822e23	317
3fe00109	318	#if defined(CONFIG_CMD_DOC)
49822e23 WD	319	void doc_init (void)
49822e23 WD	320	{
6d0f6bcf	321	doc_probe (CONFIG_SYS_DOC_BASE);
49822e23 WD	322	}
49822e23 WD	323	#endif
19403633 BW	324
	325	int board_eth_init(bd_t *bis)
	326	{
e1d7480b	327	cpu_eth_init(bis); /* Built in FEC comes first */
19403633 BW	328	return pci_eth_init(bis);
19403633 BW	329	}