[people/ms/u-boot.git] / board / pm856 / pm856.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2003,Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <ioports.h>
#include <spd.h>
#include <miiphy.h>

#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

extern long int spd_sdram(void);

void local_bus_init(void);
long int fixed_sdram(void);

/*
 * I/O Port configuration table
 *
 * if conf is 1, then that port pin will be configured at boot time
 * according to the five values podr/pdir/ppar/psor/pdat for that entry
 */

const iop_conf_t iop_conf_tab[4][32] = {

    /* Port A configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* FREERUN */
	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
    },

    /* Port B configuration */
    {   /*            conf ppar psor pdir podr pdat */
	/* PB31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
	/* PB30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
	/* PB29 */ {   0,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
	/* PB28 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
	/* PB27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
	/* PB26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
	/* PB25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
	/* PB24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
	/* PB23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
	/* PB22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
	/* PB21 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
	/* PB20 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
	/* PB19 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
	/* PB18 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
	/* PB17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
	/* PB16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
	/* PB15 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
	/* PB14 */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
	/* PB13 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:COL */
	/* PB12 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
	/* PB11 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB10 */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB9  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB8  */ {   1,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
	/* PB7  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB6  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB5  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB4  */ {   1,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    },

    /* Port C */
    {   /*            conf ppar psor pdir podr pdat */
	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
	/* PC19 */ {   0,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
	/* PC17 */ {   1,   1,   0,   0,   0,   0   }, /* PC17 */
	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
	/* PC15 */ {   0,   1,   0,   0,   0,   0   }, /* PC15 */
	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
	/* PC13 */ {   0,   1,   0,   0,   0,   0   }, /* PC13 */
	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
	/* PC10 */ {   0,   0,   0,   1,   0,   0   }, /* FETHMDC */
	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FETHMDIO */
	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
    },

    /* Port D */
    {   /*            conf ppar psor pdir podr pdat */
	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* PD28 */
	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* PD27 */
	/* PD26 */ {   1,   1,   0,   1,   0,   0   }, /* PD26 */
	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
    }
};


int board_early_init_f (void)
{
    return 0;
}

void reset_phy (void)
{
}


int checkboard (void)
{
	puts("Board: MicroSys PM856\n");

#ifdef CONFIG_PCI
	printf("    PCI1: 32 bit, %d MHz (compiled)\n",
	       CONFIG_SYS_CLK_FREQ / 1000000);
#else
	printf("    PCI1: disabled\n");
#endif

	/*
	 * Initialize local bus.
	 */
	local_bus_init();

	return 0;
}


long int
initdram(int board_type)
{
	long dram_size = 0;
	extern long spd_sdram (void);

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	    int i,x;

	    x = 10;

	    /*
	     * Work around to stabilize DDR DLL
	     */
	    gur->ddrdllcr = 0x81000000;
	    asm("sync;isync;msync");
	    udelay (200);
	    while (gur->ddrdllcr != 0x81000100)
	    {
	    	gur->devdisr = gur->devdisr | 0x00010000;
		asm("sync;isync;msync");
		for (i=0; i<x; i++)
		    ;
		gur->devdisr = gur->devdisr & 0xfff7ffff;
		asm("sync;isync;msync");
		x++;
	    }
	}
#endif

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif

#if defined(CONFIG_DDR_ECC)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	puts("    DDR: ");
	return dram_size;
}


/*
 * Initialize Local Bus
 */

void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	get_sys_info(&sysinfo);
	clkdiv = lbc->lcrr & 0x0f;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	if (lbc_hz < 66) {
		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */

	} else if (lbc_hz >= 133) {
		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */

	} else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		uint pvr = get_pvr();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
		udelay(200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm("sync;isync;msync");
	}
}

#if defined(CFG_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) CFG_MEMTEST_START;
	uint *pend = (uint *) CFG_MEMTEST_END;
	uint *p;

	printf("SDRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("SDRAM test passed.\n");
	return 0;
}
#endif


#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
  #ifndef CFG_RAMBOOT
	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);

	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
	ddr->sdram_mode = CFG_DDR_MODE;
	ddr->sdram_interval = CFG_DDR_INTERVAL;
    #if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
    #endif
	asm("sync;isync;msync");
	udelay(500);
    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
    #else
	ddr->sdram_cfg = CFG_DDR_CONTROL;
    #endif
	asm("sync; isync; msync");
	udelay(500);
  #endif
	return CFG_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc85xxads_config_table[] = {
    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
      PCI_IDSEL_NUMBER, PCI_ANY_ID,
      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
				   PCI_ENET0_MEMADDR,
				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
      } },
    { }
};
#endif


static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_mpc85xxads_config_table,
#endif
};

#endif	/* CONFIG_PCI */


void
pci_init_board(void)
{
#ifdef CONFIG_PCI
	pci_mpc85xx_init(&hose);
#endif /* CONFIG_PCI */
}
Commit	Line	Data
b20d0032 WD	1	/*
	2	* Copyright 2004 Freescale Semiconductor.
	3	* (C) Copyright 2003,Motorola Inc.
	4	* Xianghua Xiao, (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27
	28	#include <common.h>
	29	#include <pci.h>
	30	#include <asm/processor.h>
	31	#include <asm/immap_85xx.h>
	32	#include <ioports.h>
	33	#include <spd.h>
	34	#include <miiphy.h>
	35
	36	#if defined(CONFIG_DDR_ECC)
	37	extern void ddr_enable_ecc(unsigned int dram_size);
	38	#endif
	39
	40	extern long int spd_sdram(void);
	41
	42	void local_bus_init(void);
	43	long int fixed_sdram(void);
	44
	45	/*
	46	* I/O Port configuration table
	47	*
	48	* if conf is 1, then that port pin will be configured at boot time
	49	* according to the five values podr/pdir/ppar/psor/pdat for that entry
	50	*/
	51
	52	const iop_conf_t iop_conf_tab[4][32] = {
	53
	54	/* Port A configuration */
	55	{ /* conf ppar psor pdir podr pdat */
	56	/* PA31 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxENB */
	57	/* PA30 / { 0, 1, 0, 0, 0, 0 }, / FCC1 TxClav */
	58	/* PA29 / { 0, 1, 0, 1, 0, 0 }, / FCC1 TxSOC */
	59	/* PA28 / { 0, 1, 0, 1, 0, 0 }, / FCC1 RxENB */
	60	/* PA27 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxSOC */
	61	/* PA26 / { 0, 1, 0, 0, 0, 0 }, / FCC1 RxClav */
	62	/* PA25 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[0] */
	63	/* PA24 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[1] */
	64	/* PA23 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[2] */
65	/* PA22 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[3] */
66	/* PA21 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[4] */
67	/* PA20 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[5] */
68	/* PA19 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[6] */
69	/* PA18 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXD[7] */
70	/* PA17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[7] */
71	/* PA16 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[6] */
72	/* PA15 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[5] */
73	/* PA14 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[4] */
74	/* PA13 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[3] */
75	/* PA12 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[2] */
76	/* PA11 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[1] */
77	/* PA10 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXD[0] */
78	/* PA9 / { 0, 1, 1, 1, 0, 0 }, / FCC1 L1TXD */
79	/* PA8 / { 0, 1, 1, 0, 0, 0 }, / FCC1 L1RXD */
80	/* PA7 / { 0, 0, 0, 1, 0, 0 }, / PA7 */
81	/* PA6 / { 0, 1, 1, 1, 0, 0 }, / TDM A1 L1RSYNC */
82	/* PA5 / { 0, 0, 0, 1, 0, 0 }, / PA5 */
83	/* PA4 / { 0, 0, 0, 1, 0, 0 }, / PA4 */
84	/* PA3 / { 0, 0, 0, 1, 0, 0 }, / PA3 */
85	/* PA2 / { 0, 0, 0, 1, 0, 0 }, / PA2 */
86	/* PA1 / { 0, 0, 0, 0, 0, 0 }, / FREERUN */
87	/* PA0 / { 0, 0, 0, 1, 0, 0 } / PA0 */
88	},
89
90	/* Port B configuration */
91	{ /* conf ppar psor pdir podr pdat */
92	/* PB31 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TX_ER */
93	/* PB30 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RX_DV */
94	/* PB29 / { 0, 1, 1, 1, 0, 0 }, / FCC2 MII TX_EN */
95	/* PB28 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RX_ER */
96	/* PB27 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII COL */
97	/* PB26 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII CRS */
98	/* PB25 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[3] */
99	/* PB24 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[2] */
100	/* PB23 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[1] */
101	/* PB22 / { 0, 1, 0, 1, 0, 0 }, / FCC2 MII TxD[0] */
102	/* PB21 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[0] */
103	/* PB20 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[1] */
104	/* PB19 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[2] */
105	/* PB18 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RxD[3] */
106	/* PB17 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RX_DIV */
107	/* PB16 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RX_ERR */
108	/* PB15 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TX_ERR */
109	/* PB14 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TX_EN */
110	/* PB13 / { 1, 1, 0, 0, 0, 0 }, / FCC3:COL */
111	/* PB12 / { 1, 1, 0, 0, 0, 0 }, / FCC3:CRS */
112	/* PB11 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RXD */
113	/* PB10 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RXD */
114	/* PB9 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RXD */
115	/* PB8 / { 1, 1, 0, 0, 0, 0 }, / FCC3:RXD */
116	/* PB7 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TXD */
117	/* PB6 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TXD */
118	/* PB5 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TXD */
119	/* PB4 / { 1, 1, 0, 1, 0, 0 }, / FCC3:TXD */
120	/* PB3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
121	/* PB2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
122	/* PB1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
123	/* PB0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
124	},
125
126	/* Port C */
127	{ /* conf ppar psor pdir podr pdat */
128	/* PC31 / { 0, 0, 0, 1, 0, 0 }, / PC31 */
129	/* PC30 / { 0, 0, 0, 1, 0, 0 }, / PC30 */
130	/* PC29 / { 0, 1, 1, 0, 0, 0 }, / SCC1 EN CLSN /
131	/* PC28 / { 0, 0, 0, 1, 0, 0 }, / PC28 */
132	/* PC27 / { 0, 0, 0, 1, 0, 0 }, / UART Clock in */
133	/* PC26 / { 0, 0, 0, 1, 0, 0 }, / PC26 */
134	/* PC25 / { 0, 0, 0, 1, 0, 0 }, / PC25 */
135	/* PC24 / { 0, 0, 0, 1, 0, 0 }, / PC24 */
136	/* PC23 / { 0, 1, 0, 1, 0, 0 }, / ATMTFCLK */
137	/* PC22 / { 0, 1, 0, 0, 0, 0 }, / ATMRFCLK */
138	/* PC21 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN RXCLK */
139	/* PC20 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN TXCLK */
140	/* PC19 / { 0, 1, 0, 0, 0, 0 }, / FCC2 MII RX_CLK CLK13 */
141	/* PC18 / { 1, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK14) */
142	/* PC17 / { 1, 1, 0, 0, 0, 0 }, / PC17 */
143	/* PC16 / { 0, 1, 0, 0, 0, 0 }, / FCC Tx Clock (CLK16) */
144	/* PC15 / { 0, 1, 0, 0, 0, 0 }, / PC15 */
145	/* PC14 / { 0, 1, 0, 0, 0, 0 }, / SCC1 EN CD /
146	/* PC13 / { 0, 1, 0, 0, 0, 0 }, / PC13 */
147	/* PC12 / { 0, 1, 0, 1, 0, 0 }, / PC12 */
148	/* PC11 / { 0, 0, 0, 1, 0, 0 }, / LXT971 transmit control */
149	/* PC10 / { 0, 0, 0, 1, 0, 0 }, / FETHMDC */
150	/* PC9 / { 0, 0, 0, 0, 0, 0 }, / FETHMDIO */
151	/* PC8 / { 0, 0, 0, 1, 0, 0 }, / PC8 */
152	/* PC7 / { 0, 0, 0, 1, 0, 0 }, / PC7 */
153	/* PC6 / { 0, 0, 0, 1, 0, 0 }, / PC6 */
154	/* PC5 / { 0, 0, 0, 1, 0, 0 }, / PC5 */
155	/* PC4 / { 0, 0, 0, 1, 0, 0 }, / PC4 */
156	/* PC3 / { 0, 0, 0, 1, 0, 0 }, / PC3 */
157	/* PC2 / { 0, 0, 0, 1, 0, 1 }, / ENET FDE */
158	/* PC1 / { 0, 0, 0, 1, 0, 0 }, / ENET DSQE */
159	/* PC0 / { 0, 0, 0, 1, 0, 0 }, / ENET LBK */
160	},
161
162	/* Port D */
163	{ /* conf ppar psor pdir podr pdat */
164	/* PD31 / { 1, 1, 0, 0, 0, 0 }, / SCC1 EN RxD */
165	/* PD30 / { 1, 1, 1, 1, 0, 0 }, / SCC1 EN TxD */
166	/* PD29 / { 1, 1, 0, 1, 0, 0 }, / SCC1 EN TENA */
167	/* PD28 / { 1, 1, 0, 0, 0, 0 }, / PD28 */
168	/* PD27 / { 1, 1, 0, 1, 0, 0 }, / PD27 */
169	/* PD26 / { 1, 1, 0, 1, 0, 0 }, / PD26 */
170	/* PD25 / { 0, 0, 0, 1, 0, 0 }, / PD25 */
171	/* PD24 / { 0, 0, 0, 1, 0, 0 }, / PD24 */
172	/* PD23 / { 0, 0, 0, 1, 0, 0 }, / PD23 */
173	/* PD22 / { 0, 0, 0, 1, 0, 0 }, / PD22 */
174	/* PD21 / { 0, 0, 0, 1, 0, 0 }, / PD21 */
175	/* PD20 / { 0, 0, 0, 1, 0, 0 }, / PD20 */
176	/* PD19 / { 0, 0, 0, 1, 0, 0 }, / PD19 */
177	/* PD18 / { 0, 0, 0, 1, 0, 0 }, / PD18 */
178	/* PD17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXPRTY */
179	/* PD16 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXPRTY */
180	/* PD15 / { 0, 1, 1, 0, 1, 0 }, / I2C SDA */
181	/* PD14 / { 0, 0, 0, 1, 0, 0 }, / LED */
182	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
183	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
184	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
185	/* PD10 / { 0, 0, 0, 0, 0, 0 }, / PD10 */
186	/* PD9 / { 0, 1, 0, 1, 0, 0 }, / SMC1 TXD */
187	/* PD8 / { 0, 1, 0, 0, 0, 0 }, / SMC1 RXD */
188	/* PD7 / { 0, 0, 0, 1, 0, 1 }, / PD7 */
189	/* PD6 / { 0, 0, 0, 1, 0, 1 }, / PD6 */
190	/* PD5 / { 0, 0, 0, 1, 0, 1 }, / PD5 */
191	/* PD4 / { 0, 0, 0, 1, 0, 1 }, / PD4 */
192	/* PD3 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
193	/* PD2 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
194	/* PD1 / { 0, 0, 0, 0, 0, 0 }, / pin doesn't exist */
195	/* PD0 / { 0, 0, 0, 0, 0, 0 } / pin doesn't exist */
196	}
197	};
198
199
200	int board_early_init_f (void)
201	{
202	return 0;
203	}
204
205	void reset_phy (void)
206	{
207	}
208
209
210	int checkboard (void)
211	{
212	puts("Board: MicroSys PM856\n");
213
214	#ifdef CONFIG_PCI
215	printf(" PCI1: 32 bit, %d MHz (compiled)\n",
216	CONFIG_SYS_CLK_FREQ / 1000000);
217	#else
218	printf(" PCI1: disabled\n");
219	#endif
220
221	/*
222	* Initialize local bus.
223	*/
224	local_bus_init();
225
226	return 0;
227	}
228
229
230	long int
231	initdram(int board_type)
232	{
233	long dram_size = 0;
234	extern long spd_sdram (void);
b20d0032 WD	235
	236	puts("Initializing\n");
	237
	238	#if defined(CONFIG_DDR_DLL)
	239	{
f59b55a5	240	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
b20d0032 WD	241	int i,x;
	242
	243	x = 10;
	244
	245	/*
	246	* Work around to stabilize DDR DLL
	247	*/
	248	gur->ddrdllcr = 0x81000000;
	249	asm("sync;isync;msync");
	250	udelay (200);
	251	while (gur->ddrdllcr != 0x81000100)
	252	{
	253	gur->devdisr = gur->devdisr \| 0x00010000;
	254	asm("sync;isync;msync");
	255	for (i=0; i<x; i++)
	256	;
	257	gur->devdisr = gur->devdisr & 0xfff7ffff;
	258	asm("sync;isync;msync");
	259	x++;
	260	}
	261	}
	262	#endif
	263
	264	#if defined(CONFIG_SPD_EEPROM)
	265	dram_size = spd_sdram ();
	266	#else
	267	dram_size = fixed_sdram ();
	268	#endif
	269
	270	#if defined(CONFIG_DDR_ECC)
	271	/*
	272	* Initialize and enable DDR ECC.
	273	*/
	274	ddr_enable_ecc(dram_size);
	275	#endif
	276
	277	puts(" DDR: ");
	278	return dram_size;
	279	}
	280
	281
	282	/*
	283	* Initialize Local Bus
	284	*/
	285
	286	void
	287	local_bus_init(void)
	288	{
f59b55a5	289	volatile ccsr_gur_t gur = (void )(CFG_MPC85xx_GUTS_ADDR);
04db4008	290	volatile ccsr_lbc_t lbc = (void )(CFG_MPC85xx_LBC_ADDR);
b20d0032 WD	291
	292	uint clkdiv;
	293	uint lbc_hz;
	294	sys_info_t sysinfo;
	295
	296	/*
	297	* Errata LBC11.
	298	* Fix Local Bus clock glitch when DLL is enabled.
	299	*
	300	* If localbus freq is < 66Mhz, DLL bypass mode must be used.
	301	* If localbus freq is > 133Mhz, DLL can be safely enabled.
	302	* Between 66 and 133, the DLL is enabled with an override workaround.
	303	*/
	304
	305	get_sys_info(&sysinfo);
	306	clkdiv = lbc->lcrr & 0x0f;
	307	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	308
	309	if (lbc_hz < 66) {
	310	lbc->lcrr = CFG_LBC_LCRR \| 0x80000000; /* DLL Bypass */
	311
	312	} else if (lbc_hz >= 133) {
	313	lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
	314
	315	} else {
	316	/*
	317	* On REV1 boards, need to change CLKDIV before enable DLL.
	318	* Default CLKDIV is 8, change it to 4 temporarily.
	319	*/
	320	uint pvr = get_pvr();
	321	uint temp_lbcdll = 0;
	322
	323	if (pvr == PVR_85xx_REV1) {
	324	/* FIXME: Justify the high bit here. */
	325	lbc->lcrr = 0x10000004;
	326	}
	327
	328	lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
	329	udelay(200);
	330
	331	/*
	332	* Sample LBC DLL ctrl reg, upshift it to set the
	333	* override bits.
	334	*/
	335	temp_lbcdll = gur->lbcdllcr;
	336	gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) \| 0x80000000);
	337	asm("sync;isync;msync");
	338	}
	339	}
	340
	341	#if defined(CFG_DRAM_TEST)
	342	int testdram (void)
	343	{
	344	uint pstart = (uint ) CFG_MEMTEST_START;
	345	uint pend = (uint ) CFG_MEMTEST_END;
	346	uint *p;
	347
	348	printf("SDRAM test phase 1:\n");
	349	for (p = pstart; p < pend; p++)
	350	*p = 0xaaaaaaaa;
	351
	352	for (p = pstart; p < pend; p++) {
	353	if (*p != 0xaaaaaaaa) {
	354	printf ("SDRAM test fails at: %08x\n", (uint) p);
355	return 1;
356	}
357	}
358
359	printf("SDRAM test phase 2:\n");
360	for (p = pstart; p < pend; p++)
361	*p = 0x55555555;
362
363	for (p = pstart; p < pend; p++) {
364	if (*p != 0x55555555) {
365	printf ("SDRAM test fails at: %08x\n", (uint) p);
366	return 1;
367	}
368	}
369
370	printf("SDRAM test passed.\n");
371	return 0;
372	}
373	#endif
374
375
376	#if !defined(CONFIG_SPD_EEPROM)
377	/*************************************************************************
378	* fixed sdram init -- doesn't use serial presence detect.
379	************************************************************************/
380	long int fixed_sdram (void)
381	{
382	#ifndef CFG_RAMBOOT
04db4008	383	volatile ccsr_ddr_t ddr= (void )(CFG_MPC85xx_DDR_ADDR);
b20d0032 WD	384
	385	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
	386	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
	387	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
	388	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
	389	ddr->sdram_mode = CFG_DDR_MODE;
	390	ddr->sdram_interval = CFG_DDR_INTERVAL;
	391	#if defined (CONFIG_DDR_ECC)
	392	ddr->err_disable = 0x0000000D;
	393	ddr->err_sbe = 0x00ff0000;
	394	#endif
	395	asm("sync;isync;msync");
	396	udelay(500);
	397	#if defined (CONFIG_DDR_ECC)
	398	/* Enable ECC checking */
	399	ddr->sdram_cfg = (CFG_DDR_CONTROL \| 0x20000000);
	400	#else
	401	ddr->sdram_cfg = CFG_DDR_CONTROL;
	402	#endif
	403	asm("sync; isync; msync");
	404	udelay(500);
	405	#endif
	406	return CFG_SDRAM_SIZE * 1024 * 1024;
	407	}
	408	#endif /* !defined(CONFIG_SPD_EEPROM) */
	409
	410
	411	#if defined(CONFIG_PCI)
	412	/*
	413	* Initialize PCI Devices, report devices found.
	414	*/
	415
	416	#ifndef CONFIG_PCI_PNP
	417	static struct pci_config_table pci_mpc85xxads_config_table[] = {
	418	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	419	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	420	pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
	421	PCI_ENET0_MEMADDR,
	422	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER
	423	} },
	424	{ }
	425	};
	426	#endif
	427
	428
	429	static struct pci_controller hose = {
	430	#ifndef CONFIG_PCI_PNP
	431	config_table: pci_mpc85xxads_config_table,
	432	#endif
	433	};
	434
	435	#endif /* CONFIG_PCI */
	436
	437
	438	void
	439	pci_init_board(void)
	440	{
	441	#ifdef CONFIG_PCI
b20d0032 WD	442	pci_mpc85xx_init(&hose);
	443	#endif /* CONFIG_PCI */
	444	}