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Commit | Line | Data |
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899620c2 SR |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | ||
25 | #include <common.h> | |
9462732a SR |
26 | #include <libfdt.h> |
27 | #include <fdt_support.h> | |
899620c2 SR |
28 | #include <spd_sdram.h> |
29 | #include <ppc4xx_enet.h> | |
1c2ce226 | 30 | #include <miiphy.h> |
9462732a | 31 | #include <asm/processor.h> |
a760b020 | 32 | #include <asm/4xx_pci.h> |
899620c2 SR |
33 | |
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
36 | extern int alpr_fpga_init(void); | |
37 | ||
38 | int board_early_init_f (void) | |
39 | { | |
1c2ce226 SR |
40 | /*------------------------------------------------------------------------- |
41 | * Initialize EBC CONFIG | |
42 | *-------------------------------------------------------------------------*/ | |
d1c3b275 | 43 | mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | |
5bc528fa SR |
44 | EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | |
45 | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | | |
46 | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | | |
47 | EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); | |
899620c2 SR |
48 | |
49 | /*-------------------------------------------------------------------- | |
50 | * Setup the interrupt controller polarities, triggers, etc. | |
51 | *-------------------------------------------------------------------*/ | |
5de85140 SR |
52 | /* |
53 | * Because of the interrupt handling rework to handle 440GX interrupts | |
54 | * with the common code, we needed to change names of the UIC registers. | |
55 | * Here the new relationship: | |
56 | * | |
57 | * U-Boot name 440GX name | |
58 | * ----------------------- | |
59 | * UIC0 UICB0 | |
60 | * UIC1 UIC0 | |
61 | * UIC2 UIC1 | |
62 | * UIC3 UIC2 | |
63 | */ | |
952e7760 SR |
64 | mtdcr (UIC1SR, 0xffffffff); /* clear all */ |
65 | mtdcr (UIC1ER, 0x00000000); /* disable all */ | |
66 | mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ | |
67 | mtdcr (UIC1PR, 0xfffffe03); /* per manual */ | |
68 | mtdcr (UIC1TR, 0x01c00000); /* per manual */ | |
69 | mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ | |
70 | mtdcr (UIC1SR, 0xffffffff); /* clear all */ | |
71 | ||
72 | mtdcr (UIC2SR, 0xffffffff); /* clear all */ | |
73 | mtdcr (UIC2ER, 0x00000000); /* disable all */ | |
74 | mtdcr (UIC2CR, 0x00000000); /* all non-critical */ | |
75 | mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ | |
76 | mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ | |
77 | mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ | |
78 | mtdcr (UIC2SR, 0xffffffff); /* clear all */ | |
79 | ||
80 | mtdcr (UIC3SR, 0xffffffff); /* clear all */ | |
81 | mtdcr (UIC3ER, 0x00000000); /* disable all */ | |
82 | mtdcr (UIC3CR, 0x00000000); /* all non-critical */ | |
83 | mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ | |
84 | mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ | |
85 | mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ | |
86 | mtdcr (UIC3SR, 0xffffffff); /* clear all */ | |
87 | ||
88 | mtdcr (UIC0SR, 0xfc000000); /* clear all */ | |
89 | mtdcr (UIC0ER, 0x00000000); /* disable all */ | |
90 | mtdcr (UIC0CR, 0x00000000); /* all non-critical */ | |
91 | mtdcr (UIC0PR, 0xfc000000); /* */ | |
92 | mtdcr (UIC0TR, 0x00000000); /* */ | |
93 | mtdcr (UIC0VR, 0x00000001); /* */ | |
1c2ce226 | 94 | |
f16c1da9 | 95 | /* Setup shutdown/SSD empty interrupt as inputs */ |
6d0f6bcf JCPV |
96 | out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); |
97 | out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); | |
f16c1da9 | 98 | |
1c2ce226 | 99 | /* Setup GPIO/IRQ multiplexing */ |
d1c3b275 | 100 | mtsdr(SDR0_PFC0, 0x01a33e00); |
899620c2 SR |
101 | |
102 | return 0; | |
103 | } | |
104 | ||
1c2ce226 SR |
105 | int last_stage_init(void) |
106 | { | |
107 | unsigned short reg; | |
108 | ||
109 | /* | |
110 | * Configure LED's of both Marvell 88E1111 PHY's | |
111 | * | |
112 | * This has to be done after the 4xx ethernet driver is loaded, | |
113 | * so "last_stage_init()" is the right place. | |
114 | */ | |
115 | miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®); | |
116 | reg |= 0x0001; | |
117 | miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg); | |
118 | miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®); | |
119 | reg |= 0x0001; | |
120 | miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | static int board_rev(void) | |
126 | { | |
1c2ce226 | 127 | /* Setup as input */ |
6d0f6bcf JCPV |
128 | out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); |
129 | out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); | |
1c2ce226 | 130 | |
f16c1da9 | 131 | return (in32(GPIO0_IR) >> 16) & 0x3; |
1c2ce226 SR |
132 | } |
133 | ||
899620c2 SR |
134 | int checkboard (void) |
135 | { | |
136 | char *s = getenv ("serial#"); | |
137 | ||
138 | printf ("Board: ALPR"); | |
139 | if (s != NULL) { | |
140 | puts (", serial# "); | |
141 | puts (s); | |
142 | } | |
1c2ce226 | 143 | printf(" (Rev. %d)\n", board_rev()); |
899620c2 SR |
144 | |
145 | return (0); | |
146 | } | |
147 | ||
466fff1a | 148 | #if defined(CONFIG_PCI) |
a760b020 SR |
149 | /* |
150 | * Override weak pci_pre_init() | |
151 | */ | |
152 | int pci_pre_init(struct pci_controller *hose) | |
899620c2 | 153 | { |
a760b020 | 154 | if (__pci_pre_init(hose) == 0) |
899620c2 | 155 | return 0; |
899620c2 SR |
156 | |
157 | /* FPGA Init */ | |
a760b020 | 158 | alpr_fpga_init(); |
899620c2 SR |
159 | |
160 | return 1; | |
161 | } | |
899620c2 | 162 | |
899620c2 | 163 | /************************************************************************* |
9a81c612 | 164 | * Override weak is_pci_host() |
899620c2 SR |
165 | * |
166 | * This routine is called to determine if a pci scan should be | |
167 | * performed. With various hardware environments (especially cPCI and | |
168 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
169 | * bit in the strap register, or generic host/adapter assumptions. | |
170 | * | |
171 | * Rather than hard-code a bad assumption in the general 440 code, the | |
172 | * 440 pci code requires the board to decide at runtime. | |
173 | * | |
174 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
175 | * | |
176 | * | |
177 | ************************************************************************/ | |
1c2ce226 SR |
178 | static void wait_for_pci_ready(void) |
179 | { | |
180 | /* | |
181 | * Configure EREADY as input | |
182 | */ | |
6d0f6bcf | 183 | out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY); |
1c2ce226 SR |
184 | udelay(1000); |
185 | ||
186 | for (;;) { | |
6d0f6bcf | 187 | if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY) |
1c2ce226 SR |
188 | return; |
189 | } | |
190 | ||
191 | } | |
192 | ||
899620c2 SR |
193 | int is_pci_host(struct pci_controller *hose) |
194 | { | |
1c2ce226 SR |
195 | wait_for_pci_ready(); |
196 | return 1; /* return 1 for host controller */ | |
899620c2 SR |
197 | } |
198 | #endif /* defined(CONFIG_PCI) */ | |
199 | ||
200 | /************************************************************************* | |
201 | * pci_master_init | |
202 | * | |
203 | ************************************************************************/ | |
6d0f6bcf | 204 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) |
899620c2 SR |
205 | void pci_master_init(struct pci_controller *hose) |
206 | { | |
899620c2 SR |
207 | /*--------------------------------------------------------------------------+ |
208 | | PowerPC440 PCI Master configuration. | |
209 | | Map PLB/processor addresses to PCI memory space. | |
210 | | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF | |
211 | | Use byte reversed out routines to handle endianess. | |
212 | | Make this region non-prefetchable. | |
213 | +--------------------------------------------------------------------------*/ | |
ddc922ff NG |
214 | out32r( PCIL0_POM0SA, 0 ); /* disable */ |
215 | out32r( PCIL0_POM1SA, 0 ); /* disable */ | |
216 | out32r( PCIL0_POM2SA, 0 ); /* disable */ | |
217 | ||
218 | out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ | |
219 | out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */ | |
220 | out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ | |
221 | out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ | |
222 | out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ | |
223 | ||
224 | out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ | |
225 | out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */ | |
226 | out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ | |
227 | out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ | |
228 | out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ | |
899620c2 | 229 | } |
6d0f6bcf | 230 | #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ |