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899620c2 | 1 | /* |
5bc528fa SR |
2 | * (C) Copyright 2006 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5bc528fa | 6 | */ |
899620c2 | 7 | |
25ddd1fb | 8 | #include <asm-offsets.h> |
899620c2 | 9 | #include <ppc_asm.tmpl> |
cf6eb6da | 10 | #include <asm/mmu.h> |
899620c2 | 11 | #include <config.h> |
550650dd | 12 | #include <asm/ppc4xx.h> |
899620c2 | 13 | |
899620c2 SR |
14 | /************************************************************************** |
15 | * TLB TABLE | |
16 | * | |
17 | * This table is used by the cpu boot code to setup the initial tlb | |
18 | * entries. Rather than make broad assumptions in the cpu source tree, | |
19 | * this table lets each board set things up however they like. | |
20 | * | |
21 | * Pointer to the table is returned in r1 | |
22 | * | |
23 | *************************************************************************/ | |
24 | ||
5bc528fa SR |
25 | .section .bootpg,"ax" |
26 | .globl tlbtab | |
899620c2 SR |
27 | |
28 | tlbtab: | |
5bc528fa | 29 | tlbtab_start |
cf6eb6da SR |
30 | tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG ) |
31 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) | |
32 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) | |
33 | tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) | |
511e4f9e | 34 | #ifdef CONFIG_4xx_DCACHE |
cf6eb6da | 35 | tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G) |
511e4f9e | 36 | #else |
cf6eb6da | 37 | tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG) |
511e4f9e PV |
38 | #endif |
39 | ||
6d0f6bcf | 40 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
511e4f9e | 41 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
cf6eb6da | 42 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) |
511e4f9e | 43 | #endif |
cf6eb6da | 44 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) |
5bc528fa SR |
45 | |
46 | /* PCI */ | |
cf6eb6da SR |
47 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG) |
48 | tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG) | |
49 | tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG) | |
5bc528fa SR |
50 | |
51 | /* NAND */ | |
cf6eb6da | 52 | tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG) |
5bc528fa | 53 | tlbtab_end |