[people/ms/u-boot.git] / board / prodrive / pdnb3 / pdnb3.c

/*
 * (C) Copyright 2006
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <malloc.h>
#include <asm/arch/ixp425.h>

DECLARE_GLOBAL_DATA_PTR;

/* Prototypes */
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);

/* predefine these here for FPGA programming (before including fpga.c) */
#define SET_FPGA(data)	*IXP425_GPIO_GPOUTR = (data)
#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
#define OLD_VAL		old_val

static unsigned long old_val = 0;

/*
 * include common fpga code (for prodrive boards)
 */
#include "../common/fpga.c"

/*
 * Miscelaneous platform dependent initialisations
 */
int board_init(void)
{
	/* arch number of PDNB3 */
	gd->bd->bi_arch_number = MACH_TYPE_PDNB3;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0x00000100;

	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);

	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);

	/*
	 * Setup GPIO's for FPGA programming
	 */
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);

	/*
	 * Setup GPIO's for interrupts
	 */
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);

	/*
	 * Setup GPIO's for 33MHz clock output
	 */
	*IXP425_GPIO_GPCLKR = 0x01FF0000;
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);

	/*
	 * Setup other chip select's
	 */
	*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;

	return 0;
}

/*
 * Check Board Identity
 */
int checkboard(void)
{
	char *s = getenv("serial#");

	puts("Board: PDNB3");

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

int dram_init(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;

	return (0);
}

int do_fpga_boot(unsigned char *fpgadata)
{
	unsigned char *dst;
	int status;
	int index;
	int i;
	ulong len = CONFIG_SYS_MALLOC_LEN;

	/*
	 * Setup GPIO's for FPGA programming
	 */
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);

	/*
	 * Save value so no readback is required upon programming
	 */
	old_val = *IXP425_GPIO_GPOUTR;

	/*
	 * First try to decompress fpga image (gzip compressed?)
	 */
	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf("Error: Image has to be gzipp'ed!\n");
		return -1;
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=5; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc('\n');

	free(dst);

	/*
	 * Reset FPGA
	 */
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
	udelay(10);
	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);

	return (0);
}

int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong addr;

	if (argc < 2)
		return cmd_usage(cmdtp);

	addr = simple_strtoul(argv[1], NULL, 16);

	return do_fpga_boot((unsigned char *)addr);
}

U_BOOT_CMD(
	fpga,     2,     0,      do_fpga,
	"boot FPGA",
	"address size\n    - boot FPGA with gzipped image at <address>"
);

#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
extern struct pci_controller hose;
extern void pci_ixp_init(struct pci_controller * hose);

void pci_init_board(void)
{
	extern void pci_ixp_init (struct pci_controller *hose);

	pci_ixp_init(&hose);
}
#endif
Commit	Line	Data
ba94a1bb WD	1	/*
	2	* (C) Copyright 2006
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <command.h>
	26	#include <malloc.h>
	27	#include <asm/arch/ixp425.h>
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	/* Prototypes */
54841ab5	32	int do_reset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[]);
ba94a1bb WD	33
	34	/* predefine these here for FPGA programming (before including fpga.c) */
	35	#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
6d0f6bcf JCPV	36	#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
6d0f6bcf JCPV	37	#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
ba94a1bb WD	38	#define OLD_VAL old_val
	39
	40	static unsigned long old_val = 0;
	41
	42	/*
	43	* include common fpga code (for prodrive boards)
	44	*/
	45	#include "../common/fpga.c"
	46
	47	/*
	48	* Miscelaneous platform dependent initialisations
	49	*/
ba94a1bb WD	50	int board_init(void)
	51	{
	52	/* arch number of PDNB3 */
	53	gd->bd->bi_arch_number = MACH_TYPE_PDNB3;
	54
	55	/* adress of boot parameters */
	56	gd->bd->bi_boot_params = 0x00000100;
	57
6d0f6bcf JCPV	58	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
6d0f6bcf JCPV	59	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
ba94a1bb	60
6d0f6bcf JCPV	61	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
6d0f6bcf JCPV	62	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
ba94a1bb WD	63
	64	/*
	65	* Setup GPIO's for FPGA programming
	66	*/
6d0f6bcf JCPV	67	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
	68	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
	69	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
	70	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
	71	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
	72	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
	73	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
	74	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
ba94a1bb WD	75
	76	/*
	77	* Setup GPIO's for interrupts
	78	*/
6d0f6bcf JCPV	79	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
	80	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
	81	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
	82	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
	83	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
	84	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
	85	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
	86	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
ba94a1bb WD	87
	88	/*
	89	* Setup GPIO's for 33MHz clock output
	90	*/
	91	*IXP425_GPIO_GPCLKR = 0x01FF0000;
6d0f6bcf	92	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
ba94a1bb WD	93
	94	/*
	95	* Setup other chip select's
	96	*/
6d0f6bcf	97	*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
ba94a1bb WD	98
	99	return 0;
	100	}
	101
	102	/*
	103	* Check Board Identity
	104	*/
	105	int checkboard(void)
	106	{
	107	char *s = getenv("serial#");
	108
	109	puts("Board: PDNB3");
	110
	111	if (s != NULL) {
	112	puts(", serial# ");
	113	puts(s);
	114	}
	115	putc('\n');
	116
	117	return (0);
	118	}
	119
	120	int dram_init(void)
	121	{
	122	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	123	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	124
	125	return (0);
	126	}
	127
	128	int do_fpga_boot(unsigned char *fpgadata)
	129	{
	130	unsigned char *dst;
	131	int status;
	132	int index;
	133	int i;
6d0f6bcf	134	ulong len = CONFIG_SYS_MALLOC_LEN;
ba94a1bb WD	135
	136	/*
	137	* Setup GPIO's for FPGA programming
	138	*/
6d0f6bcf JCPV	139	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
	140	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
	141	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
ba94a1bb WD	142
	143	/*
	144	* Save value so no readback is required upon programming
	145	*/
	146	old_val = *IXP425_GPIO_GPOUTR;
	147
	148	/*
	149	* First try to decompress fpga image (gzip compressed?)
	150	*/
6d0f6bcf JCPV	151	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
6d0f6bcf JCPV	152	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
ba94a1bb WD	153	printf("Error: Image has to be gzipp'ed!\n");
	154	return -1;
	155	}
	156
	157	status = fpga_boot(dst, len);
	158	if (status != 0) {
	159	printf("\nFPGA: Booting failed ");
	160	switch (status) {
	161	case ERROR_FPGA_PRG_INIT_LOW:
	162	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	163	break;
	164	case ERROR_FPGA_PRG_INIT_HIGH:
	165	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	166	break;
	167	case ERROR_FPGA_PRG_DONE:
	168	printf("(Timeout: DONE not high after programming FPGA)\n ");
	169	break;
	170	}
	171
	172	/* display infos on fpgaimage */
	173	index = 15;
	174	for (i=0; i<4; i++) {
	175	len = dst[index];
	176	printf("FPGA: %s\n", &(dst[index+1]));
	177	index += len+3;
	178	}
	179	putc ('\n');
	180	/* delayed reboot */
	181	for (i=5; i>0; i--) {
	182	printf("Rebooting in %2d seconds \r",i);
	183	for (index=0;index<1000;index++)
	184	udelay(1000);
	185	}
	186	putc('\n');
	187	do_reset(NULL, 0, 0, NULL);
	188	}
	189
	190	puts("FPGA: ");
	191
	192	/* display infos on fpgaimage */
	193	index = 15;
	194	for (i=0; i<4; i++) {
	195	len = dst[index];
	196	printf("%s ", &(dst[index+1]));
	197	index += len+3;
	198	}
	199	putc('\n');
	200
	201	free(dst);
	202
	203	/*
	204	* Reset FPGA
	205	*/
6d0f6bcf	206	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
ba94a1bb	207	udelay(10);
6d0f6bcf	208	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
ba94a1bb WD	209
	210	return (0);
	211	}
	212
54841ab5	213	int do_fpga(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
ba94a1bb WD	214	{
	215	ulong addr;
	216
47e26b1b WD	217	if (argc < 2)
47e26b1b WD	218	return cmd_usage(cmdtp);
ba94a1bb WD	219
	220	addr = simple_strtoul(argv[1], NULL, 16);
	221
	222	return do_fpga_boot((unsigned char *)addr);
	223	}
	224
	225	U_BOOT_CMD(
	226	fpga, 2, 0, do_fpga,
2fb2604d	227	"boot FPGA",
a89c33db	228	"address size\n - boot FPGA with gzipped image at <address>"
ba94a1bb WD	229	);
ba94a1bb WD	230
3fe00109	231	#if defined(CONFIG_CMD_PCI) \|\| defined(CONFIG_PCI)
ba94a1bb WD	232	extern struct pci_controller hose;
	233	extern void pci_ixp_init(struct pci_controller * hose);
	234
	235	void pci_init_board(void)
	236	{
	237	extern void pci_ixp_init (struct pci_controller *hose);
	238
	239	pci_ixp_init(&hose);
	240	}
	241	#endif