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ba94a1bb WD |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <command.h> | |
26 | #include <malloc.h> | |
27 | #include <asm/arch/ixp425.h> | |
28 | ||
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
ba94a1bb WD |
31 | /* predefine these here for FPGA programming (before including fpga.c) */ |
32 | #define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data) | |
6d0f6bcf JCPV |
33 | #define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE) |
34 | #define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT) | |
ba94a1bb WD |
35 | #define OLD_VAL old_val |
36 | ||
37 | static unsigned long old_val = 0; | |
38 | ||
39 | /* | |
40 | * include common fpga code (for prodrive boards) | |
41 | */ | |
42 | #include "../common/fpga.c" | |
43 | ||
44 | /* | |
45 | * Miscelaneous platform dependent initialisations | |
46 | */ | |
ba94a1bb WD |
47 | int board_init(void) |
48 | { | |
49 | /* arch number of PDNB3 */ | |
50 | gd->bd->bi_arch_number = MACH_TYPE_PDNB3; | |
51 | ||
52 | /* adress of boot parameters */ | |
53 | gd->bd->bi_boot_params = 0x00000100; | |
54 | ||
6d0f6bcf JCPV |
55 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); |
56 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET); | |
ba94a1bb | 57 | |
6d0f6bcf JCPV |
58 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING); |
59 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING); | |
ba94a1bb WD |
60 | |
61 | /* | |
62 | * Setup GPIO's for FPGA programming | |
63 | */ | |
6d0f6bcf JCPV |
64 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); |
65 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); | |
66 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); | |
67 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG); | |
68 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK); | |
69 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA); | |
70 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT); | |
71 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE); | |
ba94a1bb WD |
72 | |
73 | /* | |
74 | * Setup GPIO's for interrupts | |
75 | */ | |
6d0f6bcf JCPV |
76 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); |
77 | GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); | |
78 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); | |
79 | GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); | |
80 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT); | |
81 | GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT); | |
82 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT); | |
83 | GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT); | |
ba94a1bb WD |
84 | |
85 | /* | |
86 | * Setup GPIO's for 33MHz clock output | |
87 | */ | |
88 | *IXP425_GPIO_GPCLKR = 0x01FF0000; | |
6d0f6bcf | 89 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M); |
ba94a1bb WD |
90 | |
91 | /* | |
92 | * Setup other chip select's | |
93 | */ | |
6d0f6bcf | 94 | *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1; |
ba94a1bb WD |
95 | |
96 | return 0; | |
97 | } | |
98 | ||
99 | /* | |
100 | * Check Board Identity | |
101 | */ | |
102 | int checkboard(void) | |
103 | { | |
f0c0b3a9 WD |
104 | char buf[64]; |
105 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
ba94a1bb WD |
106 | |
107 | puts("Board: PDNB3"); | |
108 | ||
f0c0b3a9 | 109 | if (i > 0) { |
ba94a1bb | 110 | puts(", serial# "); |
f0c0b3a9 | 111 | puts(buf); |
ba94a1bb WD |
112 | } |
113 | putc('\n'); | |
114 | ||
115 | return (0); | |
116 | } | |
117 | ||
118 | int dram_init(void) | |
119 | { | |
120 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
121 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
122 | ||
123 | return (0); | |
124 | } | |
125 | ||
126 | int do_fpga_boot(unsigned char *fpgadata) | |
127 | { | |
128 | unsigned char *dst; | |
129 | int status; | |
130 | int index; | |
131 | int i; | |
6d0f6bcf | 132 | ulong len = CONFIG_SYS_MALLOC_LEN; |
ba94a1bb WD |
133 | |
134 | /* | |
135 | * Setup GPIO's for FPGA programming | |
136 | */ | |
6d0f6bcf JCPV |
137 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); |
138 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); | |
139 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); | |
ba94a1bb WD |
140 | |
141 | /* | |
142 | * Save value so no readback is required upon programming | |
143 | */ | |
144 | old_val = *IXP425_GPIO_GPOUTR; | |
145 | ||
146 | /* | |
147 | * First try to decompress fpga image (gzip compressed?) | |
148 | */ | |
6d0f6bcf JCPV |
149 | dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); |
150 | if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { | |
ba94a1bb WD |
151 | printf("Error: Image has to be gzipp'ed!\n"); |
152 | return -1; | |
153 | } | |
154 | ||
155 | status = fpga_boot(dst, len); | |
156 | if (status != 0) { | |
157 | printf("\nFPGA: Booting failed "); | |
158 | switch (status) { | |
159 | case ERROR_FPGA_PRG_INIT_LOW: | |
160 | printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); | |
161 | break; | |
162 | case ERROR_FPGA_PRG_INIT_HIGH: | |
163 | printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); | |
164 | break; | |
165 | case ERROR_FPGA_PRG_DONE: | |
166 | printf("(Timeout: DONE not high after programming FPGA)\n "); | |
167 | break; | |
168 | } | |
169 | ||
170 | /* display infos on fpgaimage */ | |
171 | index = 15; | |
172 | for (i=0; i<4; i++) { | |
173 | len = dst[index]; | |
174 | printf("FPGA: %s\n", &(dst[index+1])); | |
175 | index += len+3; | |
176 | } | |
177 | putc ('\n'); | |
178 | /* delayed reboot */ | |
179 | for (i=5; i>0; i--) { | |
180 | printf("Rebooting in %2d seconds \r",i); | |
181 | for (index=0;index<1000;index++) | |
182 | udelay(1000); | |
183 | } | |
184 | putc('\n'); | |
185 | do_reset(NULL, 0, 0, NULL); | |
186 | } | |
187 | ||
188 | puts("FPGA: "); | |
189 | ||
190 | /* display infos on fpgaimage */ | |
191 | index = 15; | |
192 | for (i=0; i<4; i++) { | |
193 | len = dst[index]; | |
194 | printf("%s ", &(dst[index+1])); | |
195 | index += len+3; | |
196 | } | |
197 | putc('\n'); | |
198 | ||
199 | free(dst); | |
200 | ||
201 | /* | |
202 | * Reset FPGA | |
203 | */ | |
6d0f6bcf | 204 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET); |
ba94a1bb | 205 | udelay(10); |
6d0f6bcf | 206 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); |
ba94a1bb WD |
207 | |
208 | return (0); | |
209 | } | |
210 | ||
54841ab5 | 211 | int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
ba94a1bb WD |
212 | { |
213 | ulong addr; | |
214 | ||
47e26b1b WD |
215 | if (argc < 2) |
216 | return cmd_usage(cmdtp); | |
ba94a1bb WD |
217 | |
218 | addr = simple_strtoul(argv[1], NULL, 16); | |
219 | ||
220 | return do_fpga_boot((unsigned char *)addr); | |
221 | } | |
222 | ||
223 | U_BOOT_CMD( | |
224 | fpga, 2, 0, do_fpga, | |
2fb2604d | 225 | "boot FPGA", |
a89c33db | 226 | "address size\n - boot FPGA with gzipped image at <address>" |
ba94a1bb WD |
227 | ); |
228 | ||
3fe00109 | 229 | #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) |
ba94a1bb WD |
230 | extern struct pci_controller hose; |
231 | extern void pci_ixp_init(struct pci_controller * hose); | |
232 | ||
233 | void pci_init_board(void) | |
234 | { | |
235 | extern void pci_ixp_init (struct pci_controller *hose); | |
236 | ||
237 | pci_ixp_init(&hose); | |
238 | } | |
239 | #endif |