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60fbe254 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <command.h> | |
26 | #include <asm/inca-ip.h> | |
27 | #include <asm/regdef.h> | |
28 | #include <asm/mipsregs.h> | |
29 | #include <asm/addrspace.h> | |
30 | #include <asm/cacheops.h> | |
31 | ||
32 | #include "sconsole.h" | |
33 | ||
34 | #define cache_unroll(base,op) \ | |
35 | __asm__ __volatile__(" \ | |
36 | .set noreorder; \ | |
37 | .set mips3; \ | |
8bde7f77 | 38 | cache %1, (%0); \ |
60fbe254 WD |
39 | .set mips0; \ |
40 | .set reorder" \ | |
41 | : \ | |
42 | : "r" (base), \ | |
43 | "i" (op)); | |
44 | ||
45 | typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs); | |
46 | ||
47 | extern void asc_serial_init (void); | |
48 | extern void asc_serial_putc (char); | |
49 | extern void asc_serial_puts (const char *); | |
50 | extern int asc_serial_getc (void); | |
51 | extern int asc_serial_tstc (void); | |
52 | extern void asc_serial_setbrg (void); | |
53 | ||
86d82762 WD |
54 | static void sdram_timing_init (ulong size) |
55 | { | |
56 | register uint pass; | |
57 | register uint done; | |
58 | register uint count; | |
59 | register uint p0, p1, p2, p3, p4; | |
60 | register uint addr; | |
61 | ||
62 | #define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3; | |
63 | #define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3; | |
64 | ||
65 | done = 0; | |
66 | p0 = 2; | |
67 | while (p0 < 4 && done == 0) { | |
68 | p1 = 0; | |
69 | while (p1 < 2 && done == 0) { | |
70 | p2 = 0; | |
71 | while (p2 < 2 && done == 0) { | |
72 | p3 = 0; | |
73 | while (p3 < 16 && done == 0) { | |
74 | count = 0; | |
75 | p4 = 0; | |
76 | while (p4 < 32 && done == 0) { | |
77 | WRITE_MC_IOGP_1; | |
78 | ||
79 | for (addr = KSEG1 + 0x4000; | |
80 | addr < KSEG1ADDR (size); | |
81 | addr = addr + 4) { | |
82 | *(uint *) addr = 0xaa55aa55; | |
83 | } | |
84 | ||
85 | pass = 1; | |
86 | ||
87 | for (addr = KSEG1 + 0x4000; | |
88 | addr < KSEG1ADDR (size) && pass == 1; | |
89 | addr = addr + 4) { | |
90 | if (*(uint *) addr != 0xaa55aa55) | |
91 | pass = 0; | |
92 | } | |
93 | ||
94 | if (pass == 1) { | |
95 | count++; | |
96 | } else { | |
97 | count = 0; | |
98 | } | |
99 | ||
100 | if (count == 32) { | |
101 | WRITE_MC_IOGP_2; | |
102 | done = 1; | |
103 | } | |
104 | p4++; | |
105 | } | |
106 | p3++; | |
107 | } | |
108 | p2++; | |
109 | } | |
110 | p1++; | |
111 | } | |
112 | p0++; | |
113 | if (p0 == 1) | |
114 | p0++; | |
115 | } | |
116 | } | |
60fbe254 WD |
117 | |
118 | long int initdram(int board_type) | |
119 | { | |
120 | /* The only supported number of SDRAM banks is 4. | |
121 | */ | |
122 | #define CFG_NB 4 | |
123 | ||
124 | ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; | |
125 | ulong cfgdw = *INCA_IP_SDRAM_MC_CFGDW; | |
126 | int cols = cfgpb0 & 0xF; | |
127 | int rows = (cfgpb0 & 0xF0) >> 4; | |
128 | int dw = cfgdw & 0xF; | |
129 | ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; | |
86d82762 WD |
130 | void (* sdram_init) (ulong); |
131 | ||
132 | sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init); | |
133 | ||
134 | sdram_init(0x10000); | |
60fbe254 WD |
135 | |
136 | return size; | |
137 | } | |
138 | ||
139 | int checkboard (void) | |
140 | { | |
141 | ||
142 | unsigned long chipid = *(unsigned long *)0xB800C800; | |
143 | ||
144 | printf ("Board: Purple PLB 2800 chip version %ld, ", chipid & 0xF); | |
145 | ||
146 | printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000); | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | int misc_init_r (void) | |
152 | { | |
153 | asc_serial_init (); | |
154 | ||
155 | sconsole_putc = asc_serial_putc; | |
156 | sconsole_puts = asc_serial_puts; | |
157 | sconsole_getc = asc_serial_getc; | |
158 | sconsole_tstc = asc_serial_tstc; | |
159 | sconsole_setbrg = asc_serial_setbrg; | |
160 | ||
161 | sconsole_flush (); | |
162 | return (0); | |
163 | } | |
164 | ||
165 | /******************************************************************************* | |
166 | * | |
167 | * copydwords - copy one buffer to another a long at a time | |
168 | * | |
169 | * This routine copies the first <nlongs> longs from <source> to <destination>. | |
170 | */ | |
171 | static void copydwords (ulong *source, ulong *destination, ulong nlongs) | |
172 | { | |
173 | ulong temp,temp1; | |
174 | ulong *dstend = destination + nlongs; | |
175 | ||
176 | while (destination < dstend) | |
177 | { | |
178 | temp = *source++; | |
179 | /* dummy read from sdram */ | |
180 | temp1 = *(ulong *)0xa0000000; | |
181 | /* avoid optimization from compliler */ | |
182 | *(ulong *)0xbf0081f8 = temp1 + temp; | |
183 | *destination++ = temp; | |
184 | ||
8bde7f77 | 185 | } |
60fbe254 WD |
186 | } |
187 | ||
188 | /******************************************************************************* | |
189 | * | |
190 | * copyLongs - copy one buffer to another a long at a time | |
191 | * | |
192 | * This routine copies the first <nlongs> longs from <source> to <destination>. | |
193 | */ | |
194 | static void copyLongs (ulong *source, ulong *destination, ulong nlongs) | |
195 | { | |
196 | FUNCPTR absEntry; | |
197 | ||
198 | absEntry = (FUNCPTR)(0xbf008000+((ulong)copydwords & 0x7)); | |
199 | absEntry(source, destination, nlongs); | |
200 | } | |
201 | ||
202 | /******************************************************************************* | |
203 | * | |
204 | * programLoad - load program into ram | |
205 | * | |
206 | * This routine load copydwords into ram | |
207 | * | |
208 | */ | |
209 | static void programLoad(void) | |
210 | { | |
211 | FUNCPTR absEntry; | |
212 | ulong *src,*dst; | |
213 | ||
214 | src = (ulong *)(TEXT_BASE + 0x428); | |
215 | dst = (ulong *)0xbf0081d0; | |
216 | ||
8bde7f77 WD |
217 | absEntry = (FUNCPTR)(TEXT_BASE + 0x400); |
218 | absEntry(src,dst,0x6); | |
60fbe254 WD |
219 | |
220 | src = (ulong *)((ulong)copydwords & 0xfffffff8); | |
221 | dst = (ulong *)0xbf008000; | |
222 | ||
223 | absEntry(src,dst,0x38); | |
224 | } | |
225 | ||
226 | /******************************************************************************* | |
227 | * | |
228 | * copy_code - copy u-boot image from flash to RAM | |
229 | * | |
230 | * This routine is needed to solve flash problems on this board | |
231 | * | |
232 | */ | |
233 | void copy_code (ulong dest_addr) | |
234 | { | |
3b57fe0a | 235 | extern long uboot_end_data; |
60fbe254 WD |
236 | unsigned long start; |
237 | unsigned long end; | |
238 | ||
239 | /* load copydwords into ram | |
240 | */ | |
241 | programLoad(); | |
242 | ||
243 | /* copy u-boot code | |
244 | */ | |
245 | copyLongs((ulong *)CFG_MONITOR_BASE, | |
246 | (ulong *)dest_addr, | |
3b57fe0a | 247 | ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4); |
60fbe254 WD |
248 | |
249 | ||
250 | /* flush caches | |
251 | */ | |
252 | ||
253 | start = KSEG0; | |
254 | end = start + CFG_DCACHE_SIZE; | |
255 | while(start < end) { | |
256 | cache_unroll(start,Index_Writeback_Inv_D); | |
257 | start += CFG_CACHELINE_SIZE; | |
258 | } | |
259 | ||
260 | start = KSEG0; | |
261 | end = start + CFG_ICACHE_SIZE; | |
262 | while(start < end) { | |
263 | cache_unroll(start,Index_Invalidate_I); | |
264 | start += CFG_CACHELINE_SIZE; | |
265 | } | |
266 | } |