projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 70a2047f WD |
1 | Notes on the Vibren PXA255 IDP. |
| 2 | ||
| 3 | Chip select usage: | |
| 4 | ||
| 5 | CS0 - flash | |
| 6 | CS1 - alt flash (Mdoc or main flash) | |
| 7 | CS2 - high speed expansion bus | |
| 8 | CS3 - Media Q, low speed exp bus | |
| 9 | CS4 - low speed exp bus | |
| 10 | CS5 - low speed exp bus | |
| 11 | - IDE: offset 0x03000000 (abs: 0x17000000) | |
| 12 | - Eth: offset 0x03400000 (abs: 0x17400000) | |
| 13 | - core voltage latch: offset 0x03800000 (abs: 0x17800000) | |
| 14 | - CPLD: offset 0x03C00000 (abs: 0x17C00000) | |
| 15 | ||
| 16 | PCMCIA Power control | |
| 17 | ||
| 18 | MAX1602EE w/ code pulled high (Cirrus code) | |
| 19 | vx = 5v | |
| 20 | vy = 3v | |
| 21 | ||
| 22 | Bit pattern | |
| 23 | PWR 3,2,1,0 | |
| 24 | vcc vpp A1VCC A0VCC A1VPP A0VPP | |
| 25 | ===================================================== | |
| 26 | 0 0 0 0 0 0 0x0 | |
| 27 | 3 (vy) 0 1 0 1 1 0xB | |
| 28 | 3 (vy) 3 (vy) 1 0 0 1 0x9 | |
| 29 | 3 (vy) 12(12in) 1 0 1 0 0xA | |
| 30 | 5 (vx) 0 0 1 1 1 0x7 | |
| 31 | 5 (vx) 5 (vx) 0 1 0 1 0x5 | |
| 32 | 5 (vx 12(12in) 0 1 1 0 0x6 | |
| 33 | ||
| 34 | Display power sequencing: | |
| 35 | ||
| 36 | - VDD applied | |
| 37 | - within 1sec, activate scanning signals | |
| 38 | - wait at least 50mS - scanning signals must be active before activating DISP | |
| 39 | ||
| 40 | Signal mapping: | |
| 41 | Schematic LV8V31 signal name | |
| 42 | ========================================= | |
| 43 | LCD_ENAVLCD DISP | |
| 44 | LCD_PWR Applies VDD to board | |
| 45 | ||
| 46 | Both of the above signals are controlled by the CPLD |