]>
Commit | Line | Data |
---|---|---|
6a7b52bc WW |
1 | /* |
2 | * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <asm/io.h> | |
9 | #include <asm/addrspace.h> | |
10 | #include <asm/types.h> | |
11 | #include <mach/ar71xx_regs.h> | |
12 | #include <mach/ddr.h> | |
04583c68 | 13 | #include <mach/ath79.h> |
6a7b52bc WW |
14 | #include <debug_uart.h> |
15 | ||
16 | DECLARE_GLOBAL_DATA_PTR; | |
17 | ||
18 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT | |
19 | void board_debug_uart_init(void) | |
20 | { | |
21 | void __iomem *regs; | |
22 | u32 val; | |
23 | ||
24 | regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, | |
25 | MAP_NOCACHE); | |
26 | ||
27 | /* | |
28 | * GPIO9 as input, GPIO10 as output | |
29 | */ | |
30 | val = readl(regs + AR71XX_GPIO_REG_OE); | |
31 | val &= ~AR933X_GPIO(9); | |
32 | val |= AR933X_GPIO(10); | |
33 | writel(val, regs + AR71XX_GPIO_REG_OE); | |
34 | ||
35 | /* | |
36 | * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO | |
37 | */ | |
38 | val = readl(regs + AR71XX_GPIO_REG_FUNC); | |
39 | val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE; | |
40 | writel(val, regs + AR71XX_GPIO_REG_FUNC); | |
41 | } | |
42 | #endif | |
43 | ||
44 | int board_early_init_f(void) | |
45 | { | |
46 | #ifdef CONFIG_DEBUG_UART | |
47 | debug_uart_init(); | |
48 | #endif | |
49 | ddr_init(); | |
04583c68 | 50 | ath79_eth_reset(); |
6a7b52bc WW |
51 | return 0; |
52 | } |