[thirdparty/u-boot.git] / board / quantum / quantum.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */


#include <common.h>
#include <mpc8xx.h>
#include "fpga.h"

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);
unsigned long flash_init (void);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFCC25

const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 00h in UPMA RAM)
	 */
	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Burst Read. (Offset 08h in UPMA RAM)
	 */
	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Single Write. (Offset 18h in UPMA RAM)
	 */
	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Burst Write. (Offset 20h in UPMA RAM)
	 */
	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Refresh. (Offset 30h in UPMA RAM)
	 * (Initialization code at 0x36)
	 */
	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
	0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,

	/*
	 * Exception. (Offset 3Ch in UPMA RAM)
	 */
	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	char buf[64];
	int i;
	int l = getenv_f("serial#", buf, sizeof(buf));

	puts ("Board QUANTUM, Serial No: ");

	for (i = 0; i < l; ++i) {
		if (buf[i] == ' ')
			break;
		putc (buf[i]);
	}
	putc ('\n');
	return (0);		/* success */
}

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size9;

	upmconfig (UPMA, (uint *) sdram_table,
		   sizeof (sdram_table) / sizeof (uint));

	/* Refresh clock prescalar */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

	memctl->memc_mar = 0x00000088;

	/* Map controller banks 1 to the SDRAM bank */
	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;

	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
	udelay (1);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/* Check Bank 0 Memory Size,
	 * 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
			   SDRAM_MAX_SIZE);
	/*
	 * Final mapping:
	 */
	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
	udelay (1000);

	return (size9);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base,
			   long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile ulong *addr;
	ulong cnt, val, size;
	ulong save[32];		/* to make test non-destructive */
	unsigned char i = 0;

	memctl->memc_mamr = mamr_value;

	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
		addr = (volatile ulong *)(base + cnt);	/* pointer arith! */

		save[i++] = *addr;
		*addr = ~cnt;
	}

	/* write 0 to base address */
	addr = (volatile ulong *)base;
	save[i] = *addr;
	*addr = 0;

	/* check at base address */
	if ((val = *addr) != 0) {
		/* Restore the original data before leaving the function.
		 */
		*addr = save[i];
		for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
			addr = (volatile ulong *) base + cnt;
			*addr = save[--i];
		}
		return (0);
	}

	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
		addr = (volatile ulong *)(base + cnt);	/* pointer arith! */

		val = *addr;
		*addr = save[--i];

		if (val != (~cnt)) {
			size = cnt * sizeof (long);
			/* Restore the original data before returning
			 */
			for (cnt <<= 1; cnt <= maxsize / sizeof (long);
			     cnt <<= 1) {
				addr = (volatile ulong *) base + cnt;
				*addr = save[--i];
			}
			return (size);
		}
	}
	return (maxsize);
}

/*
 * Miscellaneous intialization
 */
int misc_init_r (void)
{
	char *fpga_data_str = getenv ("fpgadata");
	char *fpga_size_str = getenv ("fpgasize");
	void *fpga_data;
	int fpga_size;
	int status;
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	int flash_size;

	/* Remap FLASH according to real size */
	flash_size = flash_init ();
	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;

	if (fpga_data_str && fpga_size_str) {
		fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
		fpga_size = simple_strtoul (fpga_size_str, NULL, 10);

		status = fpga_boot (fpga_data, fpga_size);
		if (status != 0) {
			printf ("\nFPGA: Booting failed ");
			switch (status) {
			case ERROR_FPGA_PRG_INIT_LOW:
				printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_INIT_HIGH:
				printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
				break;
			case ERROR_FPGA_PRG_DONE:
				printf ("(Timeout: DONE not high after programming FPGA)\n ");
				break;
			}
		}
	}
	return 0;
}
Commit	Line	Data
da93ed81 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
da93ed81 WD	6	*/
	7
	8
	9	#include <common.h>
	10	#include <mpc8xx.h>
	11	#include "fpga.h"
	12
	13	/* ------------------------------------------------------------------------- */
	14
	15	static long int dram_size (long int, long int *, long int);
	16	unsigned long flash_init (void);
	17
	18	/* ------------------------------------------------------------------------- */
	19
	20	#define _NOT_USED_ 0xFFFFCC25
	21
	22	const uint sdram_table[] = {
	23	/*
	24	* Single Read. (Offset 00h in UPMA RAM)
	25	*/
	26	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
	27	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	28
	29	/*
	30	* Burst Read. (Offset 08h in UPMA RAM)
	31	*/
	32	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
	33	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
	34	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	35	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	36
	37	/*
	38	* Single Write. (Offset 18h in UPMA RAM)
	39	*/
	40	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
	41	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	42
	43	/*
	44	* Burst Write. (Offset 20h in UPMA RAM)
	45	*/
	46	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
	47	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
	48	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	49	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	50
	51	/*
	52	* Refresh. (Offset 30h in UPMA RAM)
	53	* (Initialization code at 0x36)
	54	*/
	55	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
	56	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
	57	0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
	58
	59	/*
	60	* Exception. (Offset 3Ch in UPMA RAM)
	61	*/
	62	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
	63	};
	64
	65	/* ------------------------------------------------------------------------- */
	66
	67
	68	/*
	69	* Check Board Identity:
70	*/
71
72	int checkboard (void)
73	{
f0c0b3a9 WD	74	char buf[64];
	75	int i;
	76	int l = getenv_f("serial#", buf, sizeof(buf));
da93ed81 WD	77
	78	puts ("Board QUANTUM, Serial No: ");
	79
f0c0b3a9 WD	80	for (i = 0; i < l; ++i) {
f0c0b3a9 WD	81	if (buf[i] == ' ')
da93ed81	82	break;
f0c0b3a9	83	putc (buf[i]);
da93ed81 WD	84	}
	85	putc ('\n');
	86	return (0); /* success */
	87	}
	88
	89	/* ------------------------------------------------------------------------- */
	90
9973e3c6	91	phys_size_t initdram (int board_type)
da93ed81	92	{
6d0f6bcf	93	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
da93ed81 WD	94	volatile memctl8xx_t *memctl = &immap->im_memctl;
	95	long int size9;
	96
	97	upmconfig (UPMA, (uint *) sdram_table,
	98	sizeof (sdram_table) / sizeof (uint));
	99
	100	/* Refresh clock prescalar */
6d0f6bcf	101	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
da93ed81 WD	102
	103	memctl->memc_mar = 0x00000088;
	104
	105	/* Map controller banks 1 to the SDRAM bank */
6d0f6bcf JCPV	106	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
6d0f6bcf JCPV	107	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
da93ed81	108
6d0f6bcf	109	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
da93ed81 WD	110
	111	udelay (200);
	112
	113	/* perform SDRAM initializsation sequence */
	114
	115	memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */
	116	udelay (1);
	117
	118	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	119
	120	udelay (1000);
	121
	122	/* Check Bank 0 Memory Size,
	123	* 9 column mode
	124	*/
6d0f6bcf	125	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
da93ed81 WD	126	SDRAM_MAX_SIZE);
	127	/*
	128	* Final mapping:
	129	*/
6d0f6bcf	130	memctl->memc_or1 = ((-size9) & 0xFFFF0000) \| CONFIG_SYS_OR_TIMING_SDRAM;
da93ed81 WD	131	udelay (1000);
	132
	133	return (size9);
	134	}
	135
	136	/* ------------------------------------------------------------------------- */
	137
	138	/*
	139	* Check memory range for valid RAM. A simple memory test determines
	140	* the actually available RAM size between addresses `base' and
	141	* `base + maxsize'. Some (not all) hardware errors are detected:
	142	* - short between address lines
	143	* - short between data lines
	144	*/
	145
	146	static long int dram_size (long int mamr_value, long int *base,
	147	long int maxsize)
	148	{
6d0f6bcf	149	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
da93ed81	150	volatile memctl8xx_t *memctl = &immap->im_memctl;
77ddac94	151	volatile ulong *addr;
da93ed81 WD	152	ulong cnt, val, size;
	153	ulong save[32]; /* to make test non-destructive */
	154	unsigned char i = 0;
	155
	156	memctl->memc_mamr = mamr_value;
	157
	158	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
d87080b7	159	addr = (volatile ulong )(base + cnt); / pointer arith! */
da93ed81 WD	160
	161	save[i++] = *addr;
	162	*addr = ~cnt;
	163	}
	164
	165	/* write 0 to base address */
d87080b7	166	addr = (volatile ulong *)base;
da93ed81 WD	167	save[i] = *addr;
	168	*addr = 0;
	169
	170	/* check at base address */
	171	if ((val = *addr) != 0) {
	172	/* Restore the original data before leaving the function.
	173	*/
	174	*addr = save[i];
	175	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
	176	addr = (volatile ulong *) base + cnt;
	177	*addr = save[--i];
	178	}
	179	return (0);
	180	}
	181
	182	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
d87080b7	183	addr = (volatile ulong )(base + cnt); / pointer arith! */
da93ed81 WD	184
	185	val = *addr;
	186	*addr = save[--i];
	187
	188	if (val != (~cnt)) {
	189	size = cnt * sizeof (long);
	190	/* Restore the original data before returning
	191	*/
	192	for (cnt <<= 1; cnt <= maxsize / sizeof (long);
	193	cnt <<= 1) {
	194	addr = (volatile ulong *) base + cnt;
	195	*addr = save[--i];
	196	}
	197	return (size);
	198	}
	199	}
	200	return (maxsize);
	201	}
	202
	203	/*
	204	* Miscellaneous intialization
	205	*/
	206	int misc_init_r (void)
	207	{
	208	char *fpga_data_str = getenv ("fpgadata");
	209	char *fpga_size_str = getenv ("fpgasize");
	210	void *fpga_data;
	211	int fpga_size;
	212	int status;
6d0f6bcf	213	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
da93ed81 WD	214	volatile memctl8xx_t *memctl = &immap->im_memctl;
	215	int flash_size;
	216
	217	/* Remap FLASH according to real size */
	218	flash_size = flash_init ();
6d0f6bcf JCPV	219	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH \| (-flash_size & 0xFFFF8000);
6d0f6bcf JCPV	220	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) \| BR_MS_GPCM \| BR_V;
da93ed81 WD	221
	222	if (fpga_data_str && fpga_size_str) {
	223	fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
	224	fpga_size = simple_strtoul (fpga_size_str, NULL, 10);
	225
	226	status = fpga_boot (fpga_data, fpga_size);
	227	if (status != 0) {
	228	printf ("\nFPGA: Booting failed ");
	229	switch (status) {
	230	case ERROR_FPGA_PRG_INIT_LOW:
	231	printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	232	break;
	233	case ERROR_FPGA_PRG_INIT_HIGH:
	234	printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	235	break;
	236	case ERROR_FPGA_PRG_DONE:
	237	printf ("(Timeout: DONE not high after programming FPGA)\n ");
	238	break;
	239	}
	240	}
	241	}
	242	return 0;
	243	}