[people/ms/u-boot.git] / board / r360mpi / r360mpi.c

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <config.h>
#include <mpc8xx.h>
#include <i2c.h>

#include <commproc.h>
#include <command.h>
#include <malloc.h>

#include <linux/types.h>
#include <linux/string.h>       /* for strdup */


/*
 *  Memory Controller Using
 *
 *  CS0 - Flash memory            (0x40000000)
 *  CS1 - SDRAM                   (0x00000000}
 *  CS2 -
 *  CS3 -
 *  CS4 -
 *  CS5 -
 *  CS6 - PCMCIA device
 *  CS7 - PCMCIA device
 */

/* ------------------------------------------------------------------------- */

#define _not_used_	0xffffffff

const uint sdram_table[]=
{
	/* single read. (offset 0 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	0x1ff77c47,

	/* MRS initialization (offset 5) */

	0x1ff77c34, 0xefeabc34, 0x1fb57c35,

	/* burst read. (offset 8 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* single write. (offset 18 in upm RAM) */
	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* burst write. (offset 20 in upm RAM) */
	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* refresh. (offset 30 in upm RAM) */
	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* exception. (offset 3c in upm RAM) */
	0x7ffffc07, _not_used_, _not_used_, _not_used_ };

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 */

int checkboard (void)
{
	puts ("Board: R360 MPI Board\n");
	return 0;
}

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size8, size9;
	long int size_b0 = 0;
	unsigned long reg;

	upmconfig (UPMA, (uint *) sdram_table,
			   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;

	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller bank 2 to the SDRAM bank at
	 * preliminary address - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or2 = CFG_OR2_PRELIM;
	memctl->memc_br2 = CFG_BR2_PRELIM;

	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
	udelay (200);
	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
	udelay (200);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
					   SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
					   SDRAM_MAX_SIZE);

	if (size8 < size9) {		/* leave configuration at 9 columns */
		size_b0 = size9;
/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
	} else {			/* back to 8 columns            */
		size_b0 = size8;
		memctl->memc_mamr = CFG_MAMR_8COL;
		udelay (500);
/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
	}

	udelay (1000);

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if ((size_b0 < 0x02000000)) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
		udelay (1000);
	}

	/*
	 * Final mapping
	 */

	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

	/* adjust refresh rate depending on SDRAM type, one bank */
	reg = memctl->memc_mptpr;
	reg >>= 1;		/* reduce to CFG_MPTPR_1BK_8K / _4K */
	memctl->memc_mptpr = reg;

	udelay (10000);

#ifdef CONFIG_CAN_DRIVER
	/* Initialize OR3 / BR3 */
	memctl->memc_or3 = CFG_OR3_CAN;		/* switch GPLB_5 to GPLA_5 */
	memctl->memc_br3 = CFG_BR3_CAN;

	/* Initialize MBMR */
	memctl->memc_mbmr = MAMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */

	/* Initialize UPMB for CAN: single read */
	memctl->memc_mdr = 0xFFFFC004;
	memctl->memc_mcr = 0x0100 | UPMB;

	memctl->memc_mdr = 0x0FFFD004;
	memctl->memc_mcr = 0x0101 | UPMB;

	memctl->memc_mdr = 0x0FFFC000;
	memctl->memc_mcr = 0x0102 | UPMB;

	memctl->memc_mdr = 0x3FFFC004;
	memctl->memc_mcr = 0x0103 | UPMB;

	memctl->memc_mdr = 0xFFFFDC05;
	memctl->memc_mcr = 0x0104 | UPMB;

	/* Initialize UPMB for CAN: single write */
	memctl->memc_mdr = 0xFFFCC004;
	memctl->memc_mcr = 0x0118 | UPMB;

	memctl->memc_mdr = 0xCFFCD004;
	memctl->memc_mcr = 0x0119 | UPMB;

	memctl->memc_mdr = 0x0FFCC000;
	memctl->memc_mcr = 0x011A | UPMB;

	memctl->memc_mdr = 0x7FFCC004;
	memctl->memc_mcr = 0x011B | UPMB;

	memctl->memc_mdr = 0xFFFDCC05;
	memctl->memc_mcr = 0x011C | UPMB;
#endif

	return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value,
			   long int *base, long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile long int *addr;
	ulong cnt, val;
	ulong save[32];			/* to make test non-destructive */
	unsigned char i = 0;

	memctl->memc_mamr = mamr_value;

	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
		addr = base + cnt;	/* pointer arith! */

		save[i++] = *addr;
		*addr = ~cnt;
	}

	/* write 0 to base address */
	addr = base;
	save[i] = *addr;
	*addr = 0;

	/* check at base address */
	if ((val = *addr) != 0) {
		*addr = save[i];
		return (0);
	}

	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
		addr = base + cnt;	/* pointer arith! */
		val = *addr;
		*addr = save[--i];

		if (val != (~cnt)) {
			return (cnt * sizeof (long));
		}
	}
	return (maxsize);
}

/* ------------------------------------------------------------------------- */

void r360_i2c_lcd_write (uchar data0, uchar data1)
{
	if (i2c_write (CFG_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
		printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
	}
}

/* ------------------------------------------------------------------------- */

/*-----------------------------------------------------------------------
 * Keyboard Controller
 */

/* Number of bytes returned from Keyboard Controller */
#define KEYBD_KEY_MAX	16				/* maximum key number */
#define KEYBD_DATALEN	((KEYBD_KEY_MAX + 7) / 8)	/* normal key scan data */

static uchar *key_match (uchar *);

int misc_init_r (void)
{
	uchar kbd_data[KEYBD_DATALEN];
	uchar keybd_env[2 * KEYBD_DATALEN + 1];
	uchar *str;
	int i;

	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);

	i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);

	for (i = 0; i < KEYBD_DATALEN; ++i) {
		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
	}
	setenv ("keybd", keybd_env);

	str = strdup (key_match (keybd_env));	/* decode keys */

#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
	setenv ("preboot", str);	/* set or delete definition */
#endif /* CONFIG_PREBOOT */
	if (str != NULL) {
		free (str);
	}

	return (0);
}

/*-----------------------------------------------------------------------
 * Check if pressed key(s) match magic sequence,
 * and return the command string associated with that key(s).
 *
 * If no key press was decoded, NULL is returned.
 *
 * Note: the first character of the argument will be overwritten with
 * the "magic charcter code" of the decoded key(s), or '\0'.
 *
 *
 * Note: the string points to static environment data and must be
 * saved before you call any function that modifies the environment.
 */
#ifdef CONFIG_PREBOOT

static uchar kbd_magic_prefix[] = "key_magic";
static uchar kbd_command_prefix[] = "key_cmd";

static uchar *key_match (uchar * kbd_str)
{
	uchar magic[sizeof (kbd_magic_prefix) + 1];
	uchar cmd_name[sizeof (kbd_command_prefix) + 1];
	uchar *str, *suffix;
	uchar *kbd_magic_keys;
	char *cmd;

	/*
	 * The following string defines the characters that can pe appended
	 * to "key_magic" to form the names of environment variables that
	 * hold "magic" key codes, i. e. such key codes that can cause
	 * pre-boot actions. If the string is empty (""), then only
	 * "key_magic" is checked (old behaviour); the string "125" causes
	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
	 */
	if ((kbd_magic_keys = getenv ("magic_keys")) != NULL) {
		/* loop over all magic keys;
		 * use '\0' suffix in case of empty string
		 */
		for (suffix = kbd_magic_keys;
		     *suffix || suffix == kbd_magic_keys;
		     ++suffix) {
			sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);

#if 0
			printf ("### Check magic \"%s\"\n", magic);
#endif

			if ((str = getenv (magic)) != 0) {

#if 0
				printf ("### Compare \"%s\" \"%s\"\n",
					kbd_str, str);
#endif
				if (strcmp (kbd_str, str) == 0) {
					sprintf (cmd_name, "%s%c",
						 kbd_command_prefix,
						 *suffix);

					if ((cmd = getenv (cmd_name)) != 0) {
#if 0
						printf ("### Set PREBOOT to $(%s): \"%s\"\n",
							cmd_name, cmd);
#endif
						return (cmd);
					}
				}
			}
		}
	}
#if 0
	printf ("### Delete PREBOOT\n");
#endif
	*kbd_str = '\0';
	return (NULL);
}
#endif	/* CONFIG_PREBOOT */

/* Read Keyboard status */
int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	uchar kbd_data[KEYBD_DATALEN];
	uchar keybd_env[2 * KEYBD_DATALEN + 1];
	int i;

	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);

	/* Read keys */
	i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);

	puts ("Keys:");
	for (i = 0; i < KEYBD_DATALEN; ++i) {
		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
		printf (" %02x", kbd_data[i]);
	}
	putc ('\n');
	setenv ("keybd", keybd_env);
	return 0;
}

U_BOOT_CMD(
	kbd,	1,	1,	do_kbd,
	"kbd     - read keyboard status\n",
	NULL
);
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <config.h>
	26	#include <mpc8xx.h>
	27	#include <i2c.h>
	28
	29	#include <commproc.h>
	30	#include <command.h>
c609719b WD	31	#include <malloc.h>
	32
	33	#include <linux/types.h>
	34	#include <linux/string.h> /* for strdup */
	35
	36
	37	/*
	38	* Memory Controller Using
	39	*
	40	* CS0 - Flash memory (0x40000000)
	41	* CS1 - SDRAM (0x00000000}
	42	* CS2 -
	43	* CS3 -
	44	* CS4 -
	45	* CS5 -
	46	* CS6 - PCMCIA device
	47	* CS7 - PCMCIA device
	48	*/
	49
	50	/* ------------------------------------------------------------------------- */
	51
	52	#define _not_used_ 0xffffffff
	53
	54	const uint sdram_table[]=
	55	{
8bde7f77 WD	56	/* single read. (offset 0 in upm RAM) */
	57	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	58	0x1ff77c47,
c609719b	59
8bde7f77	60	/* MRS initialization (offset 5) */
c609719b	61
8bde7f77	62	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
c609719b	63
8bde7f77 WD	64	/* burst read. (offset 8 in upm RAM) */
	65	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	66	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	67	_not_used_, _not_used_, _not_used_, _not_used_,
	68	_not_used_, _not_used_, _not_used_, _not_used_,
c609719b	69
8bde7f77 WD	70	/* single write. (offset 18 in upm RAM) */
	71	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	72	_not_used_, _not_used_, _not_used_, _not_used_,
c609719b	73
8bde7f77 WD	74	/* burst write. (offset 20 in upm RAM) */
	75	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	76	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	77	_not_used_, _not_used_, _not_used_, _not_used_,
	78	_not_used_, _not_used_, _not_used_, _not_used_,
c609719b	79
8bde7f77 WD	80	/* refresh. (offset 30 in upm RAM) */
	81	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	82	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
	83	_not_used_, _not_used_, _not_used_, _not_used_,
c609719b	84
8bde7f77 WD	85	/* exception. (offset 3c in upm RAM) */
8bde7f77 WD	86	0x7ffffc07, _not_used_, _not_used_, _not_used_ };
c609719b WD	87
	88	/* ------------------------------------------------------------------------- */
	89
	90	/*
	91	* Check Board Identity:
	92	*/
	93
	94	int checkboard (void)
	95	{
	96	puts ("Board: R360 MPI Board\n");
	97	return 0;
	98	}
	99
	100	/* ------------------------------------------------------------------------- */
	101
	102	static long int dram_size (long int, long int *, long int);
	103
	104	/* ------------------------------------------------------------------------- */
	105
	106	long int initdram (int board_type)
	107	{
	108	volatile immap_t immap = (immap_t ) CFG_IMMR;
	109	volatile memctl8xx_t *memctl = &immap->im_memctl;
	110	long int size8, size9;
	111	long int size_b0 = 0;
	112	unsigned long reg;
	113
	114	upmconfig (UPMA, (uint *) sdram_table,
	115	sizeof (sdram_table) / sizeof (uint));
	116
	117	/*
	118	* Preliminary prescaler for refresh (depends on number of
	119	* banks): This value is selected for four cycles every 62.4 us
	120	* with two SDRAM banks or four cycles every 31.2 us with one
	121	* bank. It will be adjusted after memory sizing.
	122	*/
	123	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
	124
	125	memctl->memc_mar = 0x00000088;
	126
	127	/*
824a1ebf	128	* Map controller bank 2 to the SDRAM bank at
c609719b WD	129	* preliminary address - these have to be modified after the
	130	* SDRAM size has been determined.
	131	*/
824a1ebf WD	132	memctl->memc_or2 = CFG_OR2_PRELIM;
824a1ebf WD	133	memctl->memc_br2 = CFG_BR2_PRELIM;
c609719b WD	134
	135	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
	136
	137	udelay (200);
	138
	139	/* perform SDRAM initializsation sequence */
	140
824a1ebf	141	memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
c609719b	142	udelay (200);
824a1ebf	143	memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
c609719b WD	144	udelay (200);
	145
	146	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	147
	148	udelay (1000);
	149
	150	/*
	151	* Check Bank 0 Memory Size for re-configuration
	152	*
	153	* try 8 column mode
	154	*/
824a1ebf	155	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
c609719b WD	156	SDRAM_MAX_SIZE);
	157
	158	udelay (1000);
	159
	160	/*
	161	* try 9 column mode
	162	*/
824a1ebf	163	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
c609719b WD	164	SDRAM_MAX_SIZE);
	165
	166	if (size8 < size9) { /* leave configuration at 9 columns */
	167	size_b0 = size9;
	168	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
824a1ebf	169	} else { /* back to 8 columns */
c609719b WD	170	size_b0 = size8;
	171	memctl->memc_mamr = CFG_MAMR_8COL;
	172	udelay (500);
	173	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
	174	}
	175
	176	udelay (1000);
	177
	178	/*
	179	* Adjust refresh rate depending on SDRAM type, both banks
	180	* For types > 128 MBit leave it at the current (fast) rate
	181	*/
	182	if ((size_b0 < 0x02000000)) {
	183	/* reduce to 15.6 us (62.4 us / quad) */
	184	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
	185	udelay (1000);
	186	}
	187
	188	/*
	189	* Final mapping
	190	*/
	191
	192	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
	193	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
	194
	195	/* adjust refresh rate depending on SDRAM type, one bank */
	196	reg = memctl->memc_mptpr;
	197	reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
	198	memctl->memc_mptpr = reg;
	199
	200	udelay (10000);
	201
824a1ebf WD	202	#ifdef CONFIG_CAN_DRIVER
	203	/* Initialize OR3 / BR3 */
	204	memctl->memc_or3 = CFG_OR3_CAN; /* switch GPLB_5 to GPLA_5 */
	205	memctl->memc_br3 = CFG_BR3_CAN;
	206
	207	/* Initialize MBMR */
	208	memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
	209
	210	/* Initialize UPMB for CAN: single read */
	211	memctl->memc_mdr = 0xFFFFC004;
	212	memctl->memc_mcr = 0x0100 \| UPMB;
	213
	214	memctl->memc_mdr = 0x0FFFD004;
	215	memctl->memc_mcr = 0x0101 \| UPMB;
	216
	217	memctl->memc_mdr = 0x0FFFC000;
	218	memctl->memc_mcr = 0x0102 \| UPMB;
	219
	220	memctl->memc_mdr = 0x3FFFC004;
	221	memctl->memc_mcr = 0x0103 \| UPMB;
	222
	223	memctl->memc_mdr = 0xFFFFDC05;
	224	memctl->memc_mcr = 0x0104 \| UPMB;
	225
	226	/* Initialize UPMB for CAN: single write */
	227	memctl->memc_mdr = 0xFFFCC004;
	228	memctl->memc_mcr = 0x0118 \| UPMB;
	229
	230	memctl->memc_mdr = 0xCFFCD004;
	231	memctl->memc_mcr = 0x0119 \| UPMB;
	232
	233	memctl->memc_mdr = 0x0FFCC000;
	234	memctl->memc_mcr = 0x011A \| UPMB;
	235
	236	memctl->memc_mdr = 0x7FFCC004;
	237	memctl->memc_mcr = 0x011B \| UPMB;
	238
	239	memctl->memc_mdr = 0xFFFDCC05;
	240	memctl->memc_mcr = 0x011C \| UPMB;
	241	#endif
	242
c609719b WD	243	return (size_b0);
	244	}
	245
	246	/* ------------------------------------------------------------------------- */
	247
	248	/*
	249	* Check memory range for valid RAM. A simple memory test determines
	250	* the actually available RAM size between addresses `base' and
	251	* `base + maxsize'. Some (not all) hardware errors are detected:
	252	* - short between address lines
	253	* - short between data lines
	254	*/
	255
824a1ebf WD	256	static long int dram_size (long int mamr_value,
824a1ebf WD	257	long int *base, long int maxsize)
c609719b WD	258	{
	259	volatile immap_t immap = (immap_t ) CFG_IMMR;
	260	volatile memctl8xx_t *memctl = &immap->im_memctl;
	261	volatile long int *addr;
	262	ulong cnt, val;
	263	ulong save[32]; /* to make test non-destructive */
	264	unsigned char i = 0;
	265
	266	memctl->memc_mamr = mamr_value;
	267
	268	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
	269	addr = base + cnt; /* pointer arith! */
	270
	271	save[i++] = *addr;
	272	*addr = ~cnt;
	273	}
	274
	275	/* write 0 to base address */
	276	addr = base;
	277	save[i] = *addr;
	278	*addr = 0;
	279
	280	/* check at base address */
	281	if ((val = *addr) != 0) {
	282	*addr = save[i];
	283	return (0);
	284	}
	285
	286	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
	287	addr = base + cnt; /* pointer arith! */
	288	val = *addr;
	289	*addr = save[--i];
	290
	291	if (val != (~cnt)) {
	292	return (cnt * sizeof (long));
	293	}
	294	}
	295	return (maxsize);
	296	}
	297
	298	/* ------------------------------------------------------------------------- */
	299
824a1ebf	300	void r360_i2c_lcd_write (uchar data0, uchar data1)
c609719b	301	{
824a1ebf WD	302	if (i2c_write (CFG_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
824a1ebf WD	303	printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
c609719b WD	304	}
	305	}
	306
	307	/* ------------------------------------------------------------------------- */
	308
	309	/*-----------------------------------------------------------------------
	310	* Keyboard Controller
	311	*/
	312
	313	/* Number of bytes returned from Keyboard Controller */
824a1ebf WD	314	#define KEYBD_KEY_MAX 16 /* maximum key number */
824a1ebf WD	315	#define KEYBD_DATALEN ((KEYBD_KEY_MAX + 7) / 8) /* normal key scan data */
c609719b WD	316
	317	static uchar key_match (uchar );
	318
	319	int misc_init_r (void)
	320	{
	321	uchar kbd_data[KEYBD_DATALEN];
	322	uchar keybd_env[2 * KEYBD_DATALEN + 1];
	323	uchar *str;
	324	int i;
	325
	326	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
	327
824a1ebf	328	i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
c609719b WD	329
	330	for (i = 0; i < KEYBD_DATALEN; ++i) {
	331	sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
	332	}
	333	setenv ("keybd", keybd_env);
	334
824a1ebf	335	str = strdup (key_match (keybd_env)); /* decode keys */
c609719b WD	336
	337	#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
	338	setenv ("preboot", str); /* set or delete definition */
	339	#endif /* CONFIG_PREBOOT */
	340	if (str != NULL) {
	341	free (str);
	342	}
	343
	344	return (0);
	345	}
	346
	347	/*-----------------------------------------------------------------------
	348	* Check if pressed key(s) match magic sequence,
	349	* and return the command string associated with that key(s).
	350	*
	351	* If no key press was decoded, NULL is returned.
	352	*
	353	* Note: the first character of the argument will be overwritten with
	354	* the "magic charcter code" of the decoded key(s), or '\0'.
	355	*
	356	*
	357	* Note: the string points to static environment data and must be
	358	* saved before you call any function that modifies the environment.
	359	*/
	360	#ifdef CONFIG_PREBOOT
	361
	362	static uchar kbd_magic_prefix[] = "key_magic";
	363	static uchar kbd_command_prefix[] = "key_cmd";
	364
824a1ebf	365	static uchar key_match (uchar kbd_str)
c609719b	366	{
c609719b WD	367	uchar magic[sizeof (kbd_magic_prefix) + 1];
c609719b WD	368	uchar cmd_name[sizeof (kbd_command_prefix) + 1];
824a1ebf	369	uchar str, suffix;
c609719b WD	370	uchar *kbd_magic_keys;
c609719b WD	371	char *cmd;
c609719b WD	372
	373	/*
	374	* The following string defines the characters that can pe appended
	375	* to "key_magic" to form the names of environment variables that
	376	* hold "magic" key codes, i. e. such key codes that can cause
	377	* pre-boot actions. If the string is empty (""), then only
	378	* "key_magic" is checked (old behaviour); the string "125" causes
	379	* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
	380	*/
824a1ebf WD	381	if ((kbd_magic_keys = getenv ("magic_keys")) != NULL) {
	382	/* loop over all magic keys;
	383	* use '\0' suffix in case of empty string
	384	*/
	385	for (suffix = kbd_magic_keys;
	386	*suffix \|\| suffix == kbd_magic_keys;
	387	++suffix) {
	388	sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
c609719b	389
c609719b	390	#if 0
824a1ebf	391	printf ("### Check magic \"%s\"\n", magic);
c609719b WD	392	#endif
c609719b WD	393
824a1ebf	394	if ((str = getenv (magic)) != 0) {
d791b1dc	395
4a6fd34b	396	#if 0
824a1ebf WD	397	printf ("### Compare \"%s\" \"%s\"\n",
824a1ebf WD	398	kbd_str, str);
4a6fd34b	399	#endif
824a1ebf WD	400	if (strcmp (kbd_str, str) == 0) {
	401	sprintf (cmd_name, "%s%c",
	402	kbd_command_prefix,
	403	*suffix);
d791b1dc	404
824a1ebf WD	405	if ((cmd = getenv (cmd_name)) != 0) {
	406	#if 0
	407	printf ("### Set PREBOOT to $(%s): \"%s\"\n",
	408	cmd_name, cmd);
	409	#endif
	410	return (cmd);
	411	}
	412	}
	413	}
	414	}
c609719b WD	415	}
	416	#if 0
	417	printf ("### Delete PREBOOT\n");
	418	#endif
824a1ebf	419	*kbd_str = '\0';
c609719b WD	420	return (NULL);
c609719b WD	421	}
824a1ebf	422	#endif /* CONFIG_PREBOOT */
c609719b WD	423
	424	/* Read Keyboard status */
	425	int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
	426	{
	427	uchar kbd_data[KEYBD_DATALEN];
	428	uchar keybd_env[2 * KEYBD_DATALEN + 1];
	429	int i;
	430
	431	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
	432
	433	/* Read keys */
824a1ebf	434	i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
c609719b WD	435
	436	puts ("Keys:");
	437	for (i = 0; i < KEYBD_DATALEN; ++i) {
	438	sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
	439	printf (" %02x", kbd_data[i]);
	440	}
	441	putc ('\n');
	442	setenv ("keybd", keybd_env);
	443	return 0;
	444	}
8bde7f77	445
0d498393 WD	446	U_BOOT_CMD(
0d498393 WD	447	kbd, 1, 1, do_kbd,
8bde7f77 WD	448	"kbd - read keyboard status\n",
	449	NULL
	450	);