[people/ms/u-boot.git] / board / r360mpi / r360mpi.c

/*
 * (C) Copyright 2001-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <config.h>
#include <mpc8xx.h>
#include <i2c.h>

#include <commproc.h>
#include <command.h>
#include <malloc.h>

#include <linux/types.h>
#include <linux/string.h>       /* for strdup */


/*
 *  Memory Controller Using
 *
 *  CS0 - Flash memory		(0x40000000)
 *  CS1 - FLASH memory		(0x????????)
 *  CS2 - SDRAM			(0x00000000)
 *  CS3 -
 *  CS4 -
 *  CS5 -
 *  CS6 - PCMCIA device
 *  CS7 - PCMCIA device
 */

/* ------------------------------------------------------------------------- */

#define _not_used_	0xffffffff

const uint sdram_table[]=
{
	/* single read. (offset 0 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	0x1ff77c47,

	/* MRS initialization (offset 5) */

	0x1ff77c34, 0xefeabc34, 0x1fb57c35,

	/* burst read. (offset 8 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* single write. (offset 18 in upm RAM) */
	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* burst write. (offset 20 in upm RAM) */
	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* refresh. (offset 30 in upm RAM) */
	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* exception. (offset 3c in upm RAM) */
	0x7ffffc07, _not_used_, _not_used_, _not_used_ };

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 */

int checkboard (void)
{
	puts ("Board: R360 MPI Board\n");
	return 0;
}

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size8, size9;
	long int size_b0 = 0;
	unsigned long reg;

	upmconfig (UPMA, (uint *) sdram_table,
			   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;

	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller bank 2 to the SDRAM bank at
	 * preliminary address - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;

	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
	udelay (200);
	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
	udelay (200);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 2 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
					   SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
					   SDRAM_MAX_SIZE);

	if (size8 < size9) {		/* leave configuration at 9 columns */
		size_b0 = size9;
/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
	} else {			/* back to 8 columns            */
		size_b0 = size8;
		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
		udelay (500);
/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
	}

	udelay (1000);

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if ((size_b0 < 0x02000000)) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
		udelay (1000);
	}

	/*
	 * Final mapping
	 */

	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

	/* adjust refresh rate depending on SDRAM type, one bank */
	reg = memctl->memc_mptpr;
	reg >>= 1;		/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
	memctl->memc_mptpr = reg;

	udelay (10000);

#ifdef CONFIG_CAN_DRIVER
	/* Initialize OR3 / BR3 */
	memctl->memc_or3 = CONFIG_SYS_OR3_CAN;		/* switch GPLB_5 to GPLA_5 */
	memctl->memc_br3 = CONFIG_SYS_BR3_CAN;

	/* Initialize MBMR */
	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */

	/* Initialize UPMB for CAN: single read */
	memctl->memc_mdr = 0xFFFFC004;
	memctl->memc_mcr = 0x0100 | UPMB;

	memctl->memc_mdr = 0x0FFFD004;
	memctl->memc_mcr = 0x0101 | UPMB;

	memctl->memc_mdr = 0x0FFFC000;
	memctl->memc_mcr = 0x0102 | UPMB;

	memctl->memc_mdr = 0x3FFFC004;
	memctl->memc_mcr = 0x0103 | UPMB;

	memctl->memc_mdr = 0xFFFFDC05;
	memctl->memc_mcr = 0x0104 | UPMB;

	/* Initialize UPMB for CAN: single write */
	memctl->memc_mdr = 0xFFFCC004;
	memctl->memc_mcr = 0x0118 | UPMB;

	memctl->memc_mdr = 0xCFFCD004;
	memctl->memc_mcr = 0x0119 | UPMB;

	memctl->memc_mdr = 0x0FFCC000;
	memctl->memc_mcr = 0x011A | UPMB;

	memctl->memc_mdr = 0x7FFCC004;
	memctl->memc_mcr = 0x011B | UPMB;

	memctl->memc_mdr = 0xFFFDCC05;
	memctl->memc_mcr = 0x011C | UPMB;
#endif

	return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value,
			   long int *base, long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size(base, maxsize));
}

/* ------------------------------------------------------------------------- */

void r360_i2c_lcd_write (uchar data0, uchar data1)
{
	if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
		printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
	}
}

/* ------------------------------------------------------------------------- */

/*-----------------------------------------------------------------------
 * Keyboard Controller
 */

/* Number of bytes returned from Keyboard Controller */
#define KEYBD_KEY_MAX	16				/* maximum key number */
#define KEYBD_DATALEN	((KEYBD_KEY_MAX + 7) / 8)	/* normal key scan data */

static uchar *key_match (uchar *);

int misc_init_r (void)
{
	char kbd_data[KEYBD_DATALEN];
	char keybd_env[2 * KEYBD_DATALEN + 1];
	char *str;
	int i;

	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);

	for (i = 0; i < KEYBD_DATALEN; ++i) {
		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
	}
	setenv ("keybd", keybd_env);

	str = strdup ((char *)key_match ((uchar *)keybd_env));	/* decode keys */

#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
	setenv ("preboot", str);	/* set or delete definition */
#endif /* CONFIG_PREBOOT */
	if (str != NULL) {
		free (str);
	}

	return (0);
}

/*-----------------------------------------------------------------------
 * Check if pressed key(s) match magic sequence,
 * and return the command string associated with that key(s).
 *
 * If no key press was decoded, NULL is returned.
 *
 * Note: the first character of the argument will be overwritten with
 * the "magic charcter code" of the decoded key(s), or '\0'.
 *
 *
 * Note: the string points to static environment data and must be
 * saved before you call any function that modifies the environment.
 */
#ifdef CONFIG_PREBOOT

static uchar kbd_magic_prefix[] = "key_magic";
static uchar kbd_command_prefix[] = "key_cmd";

static uchar *key_match (uchar * kbd_str)
{
	uchar magic[sizeof (kbd_magic_prefix) + 1];
	uchar cmd_name[sizeof (kbd_command_prefix) + 1];
	uchar *str, *suffix;
	uchar *kbd_magic_keys;
	char *cmd;

	/*
	 * The following string defines the characters that can pe appended
	 * to "key_magic" to form the names of environment variables that
	 * hold "magic" key codes, i. e. such key codes that can cause
	 * pre-boot actions. If the string is empty (""), then only
	 * "key_magic" is checked (old behaviour); the string "125" causes
	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
	 */
	if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
		/* loop over all magic keys;
		 * use '\0' suffix in case of empty string
		 */
		for (suffix = kbd_magic_keys;
		     *suffix || suffix == kbd_magic_keys;
		     ++suffix) {
			sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix);

#if 0
			printf ("### Check magic \"%s\"\n", magic);
#endif

			if ((str = (uchar *)getenv ((char *)magic)) != 0) {

#if 0
				printf ("### Compare \"%s\" \"%s\"\n",
					kbd_str, str);
#endif
				if (strcmp ((char *)kbd_str, (char *)str) == 0) {
					sprintf ((char *)cmd_name, "%s%c",
						 kbd_command_prefix,
						 *suffix);

					if ((cmd = getenv ((char *)cmd_name)) != 0) {
#if 0
						printf ("### Set PREBOOT to $(%s): \"%s\"\n",
							cmd_name, cmd);
#endif
						return ((uchar *)cmd);
					}
				}
			}
		}
	}
#if 0
	printf ("### Delete PREBOOT\n");
#endif
	*kbd_str = '\0';
	return (NULL);
}
#endif	/* CONFIG_PREBOOT */

/* Read Keyboard status */
int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	uchar kbd_data[KEYBD_DATALEN];
	uchar keybd_env[2 * KEYBD_DATALEN + 1];
	int i;

	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	/* Read keys */
	i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);

	puts ("Keys:");
	for (i = 0; i < KEYBD_DATALEN; ++i) {
		sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
		printf (" %02x", kbd_data[i]);
	}
	putc ('\n');
	setenv ("keybd", (char *)keybd_env);
	return 0;
}

U_BOOT_CMD(
	kbd,	1,	1,	do_kbd,
	"read keyboard status",
	""
);
Commit	Line	Data
c609719b	1	/*
cb4dbb7b	2	* (C) Copyright 2001-2003
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
c609719b WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	#include <common.h>
	9	#include <config.h>
	10	#include <mpc8xx.h>
	11	#include <i2c.h>
	12
	13	#include <commproc.h>
	14	#include <command.h>
c609719b WD	15	#include <malloc.h>
	16
	17	#include <linux/types.h>
	18	#include <linux/string.h> /* for strdup */
	19
	20
	21	/*
	22	* Memory Controller Using
	23	*
cb4dbb7b WD	24	* CS0 - Flash memory (0x40000000)
	25	* CS1 - FLASH memory (0x????????)
	26	* CS2 - SDRAM (0x00000000)
c609719b WD	27	* CS3 -
	28	* CS4 -
	29	* CS5 -
	30	* CS6 - PCMCIA device
	31	* CS7 - PCMCIA device
	32	*/
	33
	34	/* ------------------------------------------------------------------------- */
	35
	36	#define _not_used_ 0xffffffff
	37
	38	const uint sdram_table[]=
	39	{
8bde7f77 WD	40	/* single read. (offset 0 in upm RAM) */
	41	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	42	0x1ff77c47,
c609719b	43
8bde7f77	44	/* MRS initialization (offset 5) */
c609719b	45
8bde7f77	46	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
c609719b	47
8bde7f77 WD	48	/* burst read. (offset 8 in upm RAM) */
	49	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	50	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	51	_not_used_, _not_used_, _not_used_, _not_used_,
	52	_not_used_, _not_used_, _not_used_, _not_used_,
c609719b	53
8bde7f77 WD	54	/* single write. (offset 18 in upm RAM) */
	55	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	56	_not_used_, _not_used_, _not_used_, _not_used_,
c609719b	57
8bde7f77 WD	58	/* burst write. (offset 20 in upm RAM) */
	59	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	60	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	61	_not_used_, _not_used_, _not_used_, _not_used_,
	62	_not_used_, _not_used_, _not_used_, _not_used_,
c609719b	63
8bde7f77 WD	64	/* refresh. (offset 30 in upm RAM) */
	65	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	66	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
	67	_not_used_, _not_used_, _not_used_, _not_used_,
c609719b	68
8bde7f77 WD	69	/* exception. (offset 3c in upm RAM) */
8bde7f77 WD	70	0x7ffffc07, _not_used_, _not_used_, _not_used_ };
c609719b WD	71
	72	/* ------------------------------------------------------------------------- */
	73
	74	/*
	75	* Check Board Identity:
	76	*/
	77
	78	int checkboard (void)
	79	{
	80	puts ("Board: R360 MPI Board\n");
	81	return 0;
	82	}
	83
	84	/* ------------------------------------------------------------------------- */
	85
	86	static long int dram_size (long int, long int *, long int);
	87
	88	/* ------------------------------------------------------------------------- */
	89
9973e3c6	90	phys_size_t initdram (int board_type)
c609719b	91	{
6d0f6bcf	92	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c609719b WD	93	volatile memctl8xx_t *memctl = &immap->im_memctl;
	94	long int size8, size9;
	95	long int size_b0 = 0;
	96	unsigned long reg;
	97
	98	upmconfig (UPMA, (uint *) sdram_table,
	99	sizeof (sdram_table) / sizeof (uint));
	100
	101	/*
	102	* Preliminary prescaler for refresh (depends on number of
	103	* banks): This value is selected for four cycles every 62.4 us
	104	* with two SDRAM banks or four cycles every 31.2 us with one
	105	* bank. It will be adjusted after memory sizing.
	106	*/
6d0f6bcf	107	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
c609719b WD	108
	109	memctl->memc_mar = 0x00000088;
	110
	111	/*
824a1ebf	112	* Map controller bank 2 to the SDRAM bank at
c609719b WD	113	* preliminary address - these have to be modified after the
	114	* SDRAM size has been determined.
	115	*/
6d0f6bcf JCPV	116	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
6d0f6bcf JCPV	117	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
c609719b	118
6d0f6bcf	119	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
c609719b WD	120
	121	udelay (200);
	122
	123	/* perform SDRAM initializsation sequence */
	124
824a1ebf	125	memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
c609719b	126	udelay (200);
824a1ebf	127	memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
c609719b WD	128	udelay (200);
	129
	130	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	131
	132	udelay (1000);
	133
	134	/*
cb4dbb7b	135	* Check Bank 2 Memory Size for re-configuration
c609719b WD	136	*
	137	* try 8 column mode
	138	*/
6d0f6bcf	139	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
c609719b WD	140	SDRAM_MAX_SIZE);
	141
	142	udelay (1000);
	143
	144	/*
	145	* try 9 column mode
	146	*/
6d0f6bcf	147	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
c609719b WD	148	SDRAM_MAX_SIZE);
	149
	150	if (size8 < size9) { /* leave configuration at 9 columns */
	151	size_b0 = size9;
	152	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
824a1ebf	153	} else { /* back to 8 columns */
c609719b	154	size_b0 = size8;
6d0f6bcf	155	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
c609719b WD	156	udelay (500);
	157	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
	158	}
	159
	160	udelay (1000);
	161
	162	/*
	163	* Adjust refresh rate depending on SDRAM type, both banks
	164	* For types > 128 MBit leave it at the current (fast) rate
	165	*/
	166	if ((size_b0 < 0x02000000)) {
	167	/* reduce to 15.6 us (62.4 us / quad) */
6d0f6bcf	168	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
c609719b WD	169	udelay (1000);
	170	}
	171
	172	/*
	173	* Final mapping
	174	*/
	175
6d0f6bcf JCPV	176	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) \| CONFIG_SYS_OR_TIMING_SDRAM;
6d0f6bcf JCPV	177	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
c609719b WD	178
	179	/* adjust refresh rate depending on SDRAM type, one bank */
	180	reg = memctl->memc_mptpr;
6d0f6bcf	181	reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
c609719b WD	182	memctl->memc_mptpr = reg;
	183
	184	udelay (10000);
	185
824a1ebf WD	186	#ifdef CONFIG_CAN_DRIVER
824a1ebf WD	187	/* Initialize OR3 / BR3 */
6d0f6bcf JCPV	188	memctl->memc_or3 = CONFIG_SYS_OR3_CAN; /* switch GPLB_5 to GPLA_5 */
6d0f6bcf JCPV	189	memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
824a1ebf WD	190
824a1ebf WD	191	/* Initialize MBMR */
2535d602	192	memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
824a1ebf WD	193
	194	/* Initialize UPMB for CAN: single read */
	195	memctl->memc_mdr = 0xFFFFC004;
	196	memctl->memc_mcr = 0x0100 \| UPMB;
	197
	198	memctl->memc_mdr = 0x0FFFD004;
	199	memctl->memc_mcr = 0x0101 \| UPMB;
	200
	201	memctl->memc_mdr = 0x0FFFC000;
	202	memctl->memc_mcr = 0x0102 \| UPMB;
	203
	204	memctl->memc_mdr = 0x3FFFC004;
	205	memctl->memc_mcr = 0x0103 \| UPMB;
	206
	207	memctl->memc_mdr = 0xFFFFDC05;
	208	memctl->memc_mcr = 0x0104 \| UPMB;
	209
	210	/* Initialize UPMB for CAN: single write */
	211	memctl->memc_mdr = 0xFFFCC004;
	212	memctl->memc_mcr = 0x0118 \| UPMB;
	213
	214	memctl->memc_mdr = 0xCFFCD004;
	215	memctl->memc_mcr = 0x0119 \| UPMB;
	216
	217	memctl->memc_mdr = 0x0FFCC000;
	218	memctl->memc_mcr = 0x011A \| UPMB;
	219
	220	memctl->memc_mdr = 0x7FFCC004;
	221	memctl->memc_mcr = 0x011B \| UPMB;
	222
	223	memctl->memc_mdr = 0xFFFDCC05;
	224	memctl->memc_mcr = 0x011C \| UPMB;
	225	#endif
	226
c609719b WD	227	return (size_b0);
	228	}
	229
	230	/* ------------------------------------------------------------------------- */
	231
	232	/*
	233	* Check memory range for valid RAM. A simple memory test determines
	234	* the actually available RAM size between addresses `base' and
	235	* `base + maxsize'. Some (not all) hardware errors are detected:
	236	* - short between address lines
	237	* - short between data lines
	238	*/
	239
824a1ebf WD	240	static long int dram_size (long int mamr_value,
824a1ebf WD	241	long int *base, long int maxsize)
c609719b	242	{
6d0f6bcf	243	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c609719b	244	volatile memctl8xx_t *memctl = &immap->im_memctl;
c609719b WD	245
	246	memctl->memc_mamr = mamr_value;
	247
c83bf6a2	248	return (get_ram_size(base, maxsize));
c609719b WD	249	}
	250
	251	/* ------------------------------------------------------------------------- */
	252
824a1ebf	253	void r360_i2c_lcd_write (uchar data0, uchar data1)
c609719b	254	{
6d0f6bcf	255	if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
824a1ebf	256	printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
c609719b WD	257	}
	258	}
	259
	260	/* ------------------------------------------------------------------------- */
	261
	262	/*-----------------------------------------------------------------------
	263	* Keyboard Controller
	264	*/
	265
	266	/* Number of bytes returned from Keyboard Controller */
824a1ebf WD	267	#define KEYBD_KEY_MAX 16 /* maximum key number */
824a1ebf WD	268	#define KEYBD_DATALEN ((KEYBD_KEY_MAX + 7) / 8) /* normal key scan data */
c609719b WD	269
	270	static uchar key_match (uchar );
	271
	272	int misc_init_r (void)
	273	{
77ddac94 WD	274	char kbd_data[KEYBD_DATALEN];
	275	char keybd_env[2 * KEYBD_DATALEN + 1];
	276	char *str;
c609719b WD	277	int i;
c609719b WD	278
6d0f6bcf	279	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
c609719b	280
6d0f6bcf	281	i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
c609719b WD	282
	283	for (i = 0; i < KEYBD_DATALEN; ++i) {
	284	sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
	285	}
	286	setenv ("keybd", keybd_env);
	287
77ddac94	288	str = strdup ((char )key_match ((uchar )keybd_env)); /* decode keys */
c609719b WD	289
	290	#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
	291	setenv ("preboot", str); /* set or delete definition */
	292	#endif /* CONFIG_PREBOOT */
	293	if (str != NULL) {
	294	free (str);
	295	}
	296
	297	return (0);
	298	}
	299
	300	/*-----------------------------------------------------------------------
	301	* Check if pressed key(s) match magic sequence,
	302	* and return the command string associated with that key(s).
	303	*
	304	* If no key press was decoded, NULL is returned.
	305	*
	306	* Note: the first character of the argument will be overwritten with
	307	* the "magic charcter code" of the decoded key(s), or '\0'.
	308	*
	309	*
	310	* Note: the string points to static environment data and must be
	311	* saved before you call any function that modifies the environment.
	312	*/
	313	#ifdef CONFIG_PREBOOT
	314
	315	static uchar kbd_magic_prefix[] = "key_magic";
	316	static uchar kbd_command_prefix[] = "key_cmd";
	317
824a1ebf	318	static uchar key_match (uchar kbd_str)
c609719b	319	{
c609719b WD	320	uchar magic[sizeof (kbd_magic_prefix) + 1];
c609719b WD	321	uchar cmd_name[sizeof (kbd_command_prefix) + 1];
824a1ebf	322	uchar str, suffix;
c609719b WD	323	uchar *kbd_magic_keys;
c609719b WD	324	char *cmd;
c609719b WD	325
	326	/*
	327	* The following string defines the characters that can pe appended
	328	* to "key_magic" to form the names of environment variables that
	329	* hold "magic" key codes, i. e. such key codes that can cause
	330	* pre-boot actions. If the string is empty (""), then only
	331	* "key_magic" is checked (old behaviour); the string "125" causes
	332	* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
	333	*/
77ddac94	334	if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
824a1ebf WD	335	/* loop over all magic keys;
	336	* use '\0' suffix in case of empty string
	337	*/
	338	for (suffix = kbd_magic_keys;
	339	*suffix \|\| suffix == kbd_magic_keys;
	340	++suffix) {
77ddac94	341	sprintf ((char )magic, "%s%c", kbd_magic_prefix, suffix);
c609719b	342
c609719b	343	#if 0
824a1ebf	344	printf ("### Check magic \"%s\"\n", magic);
c609719b WD	345	#endif
c609719b WD	346
77ddac94	347	if ((str = (uchar )getenv ((char )magic)) != 0) {
d791b1dc	348
4a6fd34b	349	#if 0
824a1ebf WD	350	printf ("### Compare \"%s\" \"%s\"\n",
824a1ebf WD	351	kbd_str, str);
4a6fd34b	352	#endif
77ddac94 WD	353	if (strcmp ((char )kbd_str, (char )str) == 0) {
77ddac94 WD	354	sprintf ((char *)cmd_name, "%s%c",
824a1ebf WD	355	kbd_command_prefix,
824a1ebf WD	356	*suffix);
d791b1dc	357
77ddac94	358	if ((cmd = getenv ((char *)cmd_name)) != 0) {
824a1ebf WD	359	#if 0
	360	printf ("### Set PREBOOT to $(%s): \"%s\"\n",
	361	cmd_name, cmd);
	362	#endif
77ddac94	363	return ((uchar *)cmd);
824a1ebf WD	364	}
	365	}
	366	}
	367	}
c609719b WD	368	}
	369	#if 0
	370	printf ("### Delete PREBOOT\n");
	371	#endif
824a1ebf	372	*kbd_str = '\0';
c609719b WD	373	return (NULL);
c609719b WD	374	}
824a1ebf	375	#endif /* CONFIG_PREBOOT */
c609719b WD	376
c609719b WD	377	/* Read Keyboard status */
54841ab5	378	int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
c609719b WD	379	{
	380	uchar kbd_data[KEYBD_DATALEN];
	381	uchar keybd_env[2 * KEYBD_DATALEN + 1];
	382	int i;
	383
6d0f6bcf	384	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
c609719b WD	385
c609719b WD	386	/* Read keys */
6d0f6bcf	387	i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
c609719b WD	388
	389	puts ("Keys:");
	390	for (i = 0; i < KEYBD_DATALEN; ++i) {
77ddac94	391	sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
c609719b WD	392	printf (" %02x", kbd_data[i]);
	393	}
	394	putc ('\n');
77ddac94	395	setenv ("keybd", (char *)keybd_env);
c609719b WD	396	return 0;
c609719b WD	397	}
8bde7f77	398
0d498393 WD	399	U_BOOT_CMD(
0d498393 WD	400	kbd, 1, 1, do_kbd,
2fb2604d	401	"read keyboard status",
a89c33db	402	""
8bde7f77	403	);