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[thirdparty/u-boot.git] / board / rattler / rattler.c
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8b0bfc68
WD		 1/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Analogue&Micro Rattler boards family.
6 * Tested on Rattler8248.
7 *
1a459660 8 * SPDX-License-Identifier: GPL-2.0+
8b0bfc68
WD		 9 */
10
11#include <common.h>
12#include <mpc8260.h>
13#include <ioports.h>
14
15/*
16 * I/O Port configuration table
17 *
18 * if conf is 1, then that port pin will be configured at boot time
19 * according to the five values podr/pdir/ppar/psor/pdat for that entry
20 */
21
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JCPV		 22#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
23#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
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WD		 24
25const iop_conf_t iop_conf_tab[4][32] = {
26
27 /* Port A */
28 { /* conf ppar psor pdir podr pdat */
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JCPV		 29 /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
30 /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
31 /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
32 /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
33 /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
34 /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
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WD		 35 /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
36 /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
37 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
38 /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */
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JCPV		 39 /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
40 /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
41 /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
42 /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
43 /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
44 /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
45 /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
46 /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
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WD		 47 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
48 /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
49 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
50 /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
51 /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
52 /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
53 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
54 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
55 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
56 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
57 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
58 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
59 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
60 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
61 },
62
63 /* Port B */
64 { /* conf ppar psor pdir podr pdat */
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JCPV		 65 /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
66 /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
67 /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
68 /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
69 /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
70 /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
71 /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
72 /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
73 /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
74 /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
75 /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
76 /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
77 /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
78 /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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WD		 79 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
80 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
81 /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
82 /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
83 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
84 /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
85 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
86 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
87 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
88 /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
89 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
90 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
91 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
92 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
93 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
94 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
95 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
96 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
97 },
98
99 /* Port C */
100 { /* conf ppar psor pdir podr pdat */
101 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
102 /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
103 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
104 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
105 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
106 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
107 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
108 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
109 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
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JCPV		 110 /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */
111 /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */
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WD		 112 /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
113 /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
6d0f6bcf
JCPV		 114 /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
115 /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */
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WD		 116 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
117 /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
118 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
119 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
120 /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
121 /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
122 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
123 /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
124 /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
125 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
126 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
127 /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
128 /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
129 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
130 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
131 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
132 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
133 },
134
135 /* Port D */
136 { /* conf ppar psor pdir podr pdat */
137 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
138 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
139 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
140 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
141 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
142 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
143 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
144 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
145 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
146 /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
147 /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
148 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
149 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
150 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
151 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
152 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
153 /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */
154 /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */
155 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
156 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
157 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
158 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
159 /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
160 /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
161 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
162 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
163 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
164 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
165 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
166 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
167 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
168 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
169 }
170};
171
9973e3c6 172phys_size_t initdram(int board_type)
8b0bfc68 173{
6d0f6bcf 174 long int msize = CONFIG_SYS_SDRAM_SIZE;
8b0bfc68 175
6d0f6bcf
JCPV		 176#ifndef CONFIG_SYS_RAMBOOT
177 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
8b0bfc68 178 volatile memctl8260_t *memctl = &immap->im_memctl;
6d0f6bcf 179 vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
8b0bfc68 180 uchar c = 0xFF;
6d0f6bcf 181 uint psdmr = CONFIG_SYS_PSDMR;
8b0bfc68
WD		 182 int i;
183
184 immap->im_siu_conf.sc_ppc_acr = 0x02;
185 immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
186 immap->im_siu_conf.sc_tescr1 = 0x00004000;
187
6d0f6bcf 188 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
8b0bfc68
WD		 189
190 /* Initialise 60x bus SDRAM */
6d0f6bcf
JCPV		 191 memctl->memc_psrt = CONFIG_SYS_PSRT;
192 memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
193 memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
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WD		 194 memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
195 *ramaddr = c;
196 memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
197 for (i = 0; i < 8; i++)
198 *ramaddr = c;
199 memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
200 *ramaddr = c;
201 memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
202 *ramaddr = c;
6d0f6bcf 203#endif /* !CONFIG_SYS_RAMBOOT */
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WD		 204
205 /* Return total 60x bus SDRAM size */
206 return msize * 1024 * 1024;
207}
208
209int checkboard(void)
210{
6d0f6bcf 211 vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
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WD		 212
213 printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
214 return 0;
215}
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