[people/ms/u-boot.git] / board / rbc823 / rbc823.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include "mpc8xx.h"
#include <linux/mtd/doc2000.h>

extern int kbd_init(void);
extern int drv_kbd_init(void);

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint sdram_table[] =
{
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
	0x1FF77C47, /* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 */
	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x1FF7FC07, /* last */
		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
};

const uint static_table[] =
{
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
	0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
	0xFFFFFC04, 0xFFFFFC05, /* last */
	                        _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
	0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 *
 * Test TQ ID string (TQM8xx...)
 * If present, check for "L" type (no second DRAM bank),
 * otherwise "L" type is assumed as default.
 *
 * Return 1 for "L" type, 0 else.
 */

int checkboard (void)
{
	char *s = getenv ("serial#");

	if (!s || strncmp (s, "TQM8", 4)) {
		printf ("### No HW ID - assuming RBC823\n");
		return (0);
	}

	puts (s);
	putc ('\n');

	return (0);
}

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size_b0, size8, size9;

	upmconfig (UPMA, (uint *) sdram_table,
		   sizeof (sdram_table) / sizeof (uint));

	/*
	 * 1 Bank of 64Mbit x 2 devices
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller SDRAM bank 0
	 */
	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
	udelay (200);

	/*
	 * Perform SDRAM initializsation sequence
	 */
	memctl->memc_mcr = 0x80008105;	/* SDRAM bank 0 */
	udelay (1);
	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
	udelay (200);
	memctl->memc_mcr = 0x80008130;	/* SDRAM bank 0 - execute twice */
	udelay (1);
	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
	udelay (200);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
	udelay (1000);

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;	/* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
			   SDRAM_MAX_SIZE);
	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
			   SDRAM_MAX_SIZE);

	if (size8 < size9) {	/* leave configuration at 9 columns     */
		size_b0 = size9;
/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
	} else {		/* back to 8 columns                    */
		size_b0 = size8;
		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
		udelay (500);
/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
	}

	udelay (1000);

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if ((size_b0 < 0x02000000)) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
		udelay (1000);
	}

	/* SDRAM Bank 0 is bigger - map first       */

	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
	memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

	udelay (10000);

	return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base,
			   long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size (base, maxsize));
}

void doc_init (void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	upmconfig (UPMB, (uint *) static_table,
		   sizeof (static_table) / sizeof (uint));
	memctl->memc_mbmr = MAMR_DSA_1_CYCL;

	doc_probe (FLASH_BASE1_PRELIM);
}
Commit	Line	Data
682011ff WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include "mpc8xx.h"
	26	#include <linux/mtd/doc2000.h>
	27
	28	extern int kbd_init(void);
	29	extern int drv_kbd_init(void);
	30
	31	/* ------------------------------------------------------------------------- */
	32
	33	static long int dram_size (long int, long int *, long int);
	34
	35	/* ------------------------------------------------------------------------- */
	36
	37	#define _NOT_USED_ 0xFFFFFFFF
	38
	39	const uint sdram_table[] =
	40	{
	41	/*
	42	* Single Read. (Offset 0 in UPMA RAM)
	43	*/
	44	0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
	45	0x1FF77C47, /* last */
	46	/*
	47	* SDRAM Initialization (offset 5 in UPMA RAM)
	48	*
	49	* This is no UPM entry point. The following definition uses
	50	* the remaining space to establish an initialization
	51	* sequence, which is executed by a RUN command.
	52	*
	53	*/
	54	0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
	55	/*
	56	* Burst Read. (Offset 8 in UPMA RAM)
	57	*/
	58	0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
	59	0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
	60	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	61	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	62	/*
	63	* Single Write. (Offset 18 in UPMA RAM)
	64	*/
65	0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
66	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67	/*
68	* Burst Write. (Offset 20 in UPMA RAM)
69	*/
70	0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
71	0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
72	_NOT_USED_,
73	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75	/*
76	* Refresh (Offset 30 in UPMA RAM)
77	*/
78	0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
79	0xFFFFFC84, 0xFFFFFC07, /* last */
80	_NOT_USED_, _NOT_USED_,
81	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82	/*
83	* Exception. (Offset 3c in UPMA RAM)
84	*/
85	0x1FF7FC07, /* last */
86	_NOT_USED_, _NOT_USED_, _NOT_USED_,
87	};
88
89	const uint static_table[] =
90	{
91	/*
92	* Single Read. (Offset 0 in UPMA RAM)
93	*/
94	0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
95	0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
96	0xFFFFFC04, 0xFFFFFC05, /* last */
97	_NOT_USED_, _NOT_USED_,
98	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
99	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
100	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
101	/*
102	* Single Write. (Offset 18 in UPMA RAM)
103	*/
104	0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
105	0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
106	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
107	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
108	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
109	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
110	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
111	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
112	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
113	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114	};
115
116	/* ------------------------------------------------------------------------- */
117
118	/*
119	* Check Board Identity:
120	*
121	* Test TQ ID string (TQM8xx...)
122	* If present, check for "L" type (no second DRAM bank),
123	* otherwise "L" type is assumed as default.
124	*
125	* Return 1 for "L" type, 0 else.
126	*/
127
128	int checkboard (void)
129	{
77ddac94	130	char *s = getenv ("serial#");
682011ff	131
c83bf6a2 WD	132	if (!s \|\| strncmp (s, "TQM8", 4)) {
	133	printf ("### No HW ID - assuming RBC823\n");
	134	return (0);
	135	}
682011ff	136
c83bf6a2 WD	137	puts (s);
c83bf6a2 WD	138	putc ('\n');
682011ff	139
c83bf6a2	140	return (0);
682011ff WD	141	}
	142
	143	/* ------------------------------------------------------------------------- */
	144
9973e3c6	145	phys_size_t initdram (int board_type)
682011ff	146	{
6d0f6bcf	147	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2 WD	148	volatile memctl8xx_t *memctl = &immap->im_memctl;
	149	long int size_b0, size8, size9;
	150
	151	upmconfig (UPMA, (uint *) sdram_table,
	152	sizeof (sdram_table) / sizeof (uint));
	153
	154	/*
	155	* 1 Bank of 64Mbit x 2 devices
	156	*/
6d0f6bcf	157	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
c83bf6a2 WD	158	memctl->memc_mar = 0x00000088;
	159
	160	/*
	161	* Map controller SDRAM bank 0
	162	*/
6d0f6bcf JCPV	163	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
	164	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
	165	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
c83bf6a2 WD	166	udelay (200);
	167
	168	/*
	169	* Perform SDRAM initializsation sequence
	170	*/
	171	memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
	172	udelay (1);
6d0f6bcf	173	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) \| MAMR_TLFA_8X;
c83bf6a2 WD	174	udelay (200);
	175	memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
	176	udelay (1);
6d0f6bcf	177	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) \| MAMR_TLFA_4X;
c83bf6a2 WD	178	udelay (200);
	179
	180	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	181	udelay (1000);
	182
	183	/*
	184	* Preliminary prescaler for refresh (depends on number of
	185	* banks): This value is selected for four cycles every 62.4 us
	186	* with two SDRAM banks or four cycles every 31.2 us with one
	187	* bank. It will be adjusted after memory sizing.
	188	*/
6d0f6bcf	189	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */
c83bf6a2 WD	190
	191	/*
	192	* Check Bank 0 Memory Size for re-configuration
	193	*
	194	* try 8 column mode
	195	*/
6d0f6bcf	196	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
c83bf6a2 WD	197	SDRAM_MAX_SIZE);
	198	udelay (1000);
	199
	200	/*
	201	* try 9 column mode
	202	*/
6d0f6bcf	203	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
c83bf6a2 WD	204	SDRAM_MAX_SIZE);
	205
	206	if (size8 < size9) { /* leave configuration at 9 columns */
	207	size_b0 = size9;
682011ff	208	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
c83bf6a2 WD	209	} else { /* back to 8 columns */
c83bf6a2 WD	210	size_b0 = size8;
6d0f6bcf	211	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
c83bf6a2	212	udelay (500);
682011ff	213	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
c83bf6a2	214	}
682011ff	215
c83bf6a2	216	udelay (1000);
682011ff	217
c83bf6a2 WD	218	/*
	219	* Adjust refresh rate depending on SDRAM type, both banks
	220	* For types > 128 MBit leave it at the current (fast) rate
	221	*/
	222	if ((size_b0 < 0x02000000)) {
	223	/* reduce to 15.6 us (62.4 us / quad) */
6d0f6bcf	224	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
c83bf6a2 WD	225	udelay (1000);
c83bf6a2 WD	226	}
682011ff	227
c83bf6a2	228	/* SDRAM Bank 0 is bigger - map first */
682011ff	229
6d0f6bcf JCPV	230	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) \| CONFIG_SYS_OR_TIMING_SDRAM;
6d0f6bcf JCPV	231	memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
682011ff	232
c83bf6a2	233	udelay (10000);
682011ff	234
c83bf6a2	235	return (size_b0);
682011ff WD	236	}
	237
	238	/* ------------------------------------------------------------------------- */
	239
	240	/*
	241	* Check memory range for valid RAM. A simple memory test determines
	242	* the actually available RAM size between addresses `base' and
	243	* `base + maxsize'. Some (not all) hardware errors are detected:
	244	* - short between address lines
	245	* - short between data lines
	246	*/
	247
c83bf6a2 WD	248	static long int dram_size (long int mamr_value, long int *base,
c83bf6a2 WD	249	long int maxsize)
682011ff	250	{
6d0f6bcf	251	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2	252	volatile memctl8xx_t *memctl = &immap->im_memctl;
682011ff	253
c83bf6a2	254	memctl->memc_mamr = mamr_value;
682011ff	255
c83bf6a2	256	return (get_ram_size (base, maxsize));
682011ff WD	257	}
682011ff WD	258
c83bf6a2	259	void doc_init (void)
682011ff	260	{
6d0f6bcf	261	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2	262	volatile memctl8xx_t *memctl = &immap->im_memctl;
682011ff	263
c83bf6a2 WD	264	upmconfig (UPMB, (uint *) static_table,
	265	sizeof (static_table) / sizeof (uint));
	266	memctl->memc_mbmr = MAMR_DSA_1_CYCL;
682011ff	267
c83bf6a2	268	doc_probe (FLASH_BASE1_PRELIM);
682011ff	269	}