[people/ms/u-boot.git] / board / renesas / alt / alt.c

/*
 * board/renesas/alt/alt.c
 *
 * Copyright (C) 2014, 2015 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#include <common.h>
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <div64.h>
#include "qos.h"

DECLARE_GLOBAL_DATA_PTR;

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	/* QoS */
	qos_init();
}

#define TMU0_MSTP125	(1 << 25)
#define SCIF2_MSTP719	(1 << 19)
#define ETHER_MSTP813	(1 << 13)
#define IIC1_MSTP323	(1 << 23)
#define MMC0_MSTP315	(1 << 15)
#define SDHI0_MSTP314	(1 << 14)
#define SDHI1_MSTP312	(1 << 12)

#define SD1CKCR		0xE6150078
#define SD1_97500KHZ	0x7

int board_early_init_f(void)
{
	/* TMU */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);

	/* SCIF2 */
	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);

	/* ETHER */
	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);

	/* IIC1 / sh-i2c ch1 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);

#ifdef CONFIG_SH_MMCIF
	/* MMC */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
#endif

#ifdef CONFIG_SH_SDHI
	/* SDHI0, 1 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312);

	/*
	 * SD0 clock is set to 97.5MHz by default.
	 * Set SD1 to the 97.5MHz as well.
	 */
	writel(SD1_97500KHZ, SD1CKCR);
#endif
	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	/* Init PFC controller */
	r8a7794_pinmux_init();

	/* Ether Enable */
#if defined(CONFIG_R8A7794_ETHERNET_B)
	gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
	gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
	gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
	gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
	gpio_request(GPIO_FN_ETH_LINK_B, NULL);
	gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
	gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
	gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
	gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
	gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
	gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
	gpio_request(GPIO_FN_ETH_MDC_B, NULL);
#else
	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
	gpio_request(GPIO_FN_ETH_RXD0, NULL);
	gpio_request(GPIO_FN_ETH_RXD1, NULL);
	gpio_request(GPIO_FN_ETH_LINK, NULL);
	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
	gpio_request(GPIO_FN_ETH_MDIO, NULL);
	gpio_request(GPIO_FN_ETH_TXD1, NULL);
	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
	gpio_request(GPIO_FN_ETH_TXD0, NULL);
	gpio_request(GPIO_FN_ETH_MDC, NULL);
#endif
	gpio_request(GPIO_FN_IRQ8, NULL);

	/* PHY reset */
	gpio_request(GPIO_GP_1_24, NULL);
	gpio_direction_output(GPIO_GP_1_24, 0);
	mdelay(20);
	gpio_set_value(GPIO_GP_1_24, 1);
	udelay(1);

	return 0;
}

#define CXR24 0xEE7003C0 /* MAC address high register */
#define CXR25 0xEE7003C8 /* MAC address low register */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SH_ETHER
	int ret = -ENODEV;
	u32 val;
	unsigned char enetaddr[6];

	ret = sh_eth_initialize(bis);
	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
		return ret;

	/* Set Mac address */
	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
		enetaddr[2] << 8 | enetaddr[3];
	writel(val, CXR24);

	val = enetaddr[4] << 8 | enetaddr[5];
	writel(val, CXR25);

	return ret;
#else
	return 0;
#endif
}

int board_mmc_init(bd_t *bis)
{
	int ret = -ENODEV;

#ifdef CONFIG_SH_MMCIF
	gpio_request(GPIO_GP_4_31, NULL);
	gpio_set_value(GPIO_GP_4_31, 1);

	ret = mmcif_mmc_init();
#endif

#ifdef CONFIG_SH_SDHI
	gpio_request(GPIO_FN_SD0_DATA0, NULL);
	gpio_request(GPIO_FN_SD0_DATA1, NULL);
	gpio_request(GPIO_FN_SD0_DATA2, NULL);
	gpio_request(GPIO_FN_SD0_DATA3, NULL);
	gpio_request(GPIO_FN_SD0_CLK, NULL);
	gpio_request(GPIO_FN_SD0_CMD, NULL);
	gpio_request(GPIO_FN_SD0_CD, NULL);
	gpio_request(GPIO_FN_SD1_DATA0, NULL);
	gpio_request(GPIO_FN_SD1_DATA1, NULL);
	gpio_request(GPIO_FN_SD1_DATA2, NULL);
	gpio_request(GPIO_FN_SD1_DATA3, NULL);
	gpio_request(GPIO_FN_SD1_CLK, NULL);
	gpio_request(GPIO_FN_SD1_CMD, NULL);
	gpio_request(GPIO_FN_SD1_CD, NULL);

	/* SDHI 0 */
	gpio_request(GPIO_GP_2_26, NULL);
	gpio_request(GPIO_GP_2_29, NULL);
	gpio_direction_output(GPIO_GP_2_26, 1);
	gpio_direction_output(GPIO_GP_2_29, 1);

	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
			   SH_SDHI_QUIRK_16BIT_BUF);
	if (ret)
		return ret;

	/* SDHI 1 */
	gpio_request(GPIO_GP_4_26, NULL);
	gpio_request(GPIO_GP_4_29, NULL);
	gpio_direction_output(GPIO_GP_4_26, 1);
	gpio_direction_output(GPIO_GP_4_29, 1);

	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
#endif
	return ret;
}

int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}

const struct rmobile_sysinfo sysinfo = {
	CONFIG_ARCH_RMOBILE_BOARD_STRING
};

void reset_cpu(ulong addr)
{
	u8 val;

	i2c_set_bus_num(1); /* PowerIC connected to ch1 */
	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
	val |= 0x02;
	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}

static const struct sh_serial_platdata serial_platdata = {
	.base = SCIF2_BASE,
	.type = PORT_SCIF,
	.clk = 14745600,
	.clk_mode = EXT_CLK,
};

U_BOOT_DEVICE(alt_serials) = {
	.name = "serial_sh",
	.platdata = &serial_platdata,
};
Commit	Line	Data
cff2f5f0 NI	1	/*
	2	* board/renesas/alt/alt.c
	3	*
cae72042	4	* Copyright (C) 2014, 2015 Renesas Electronics Corporation
cff2f5f0 NI	5	*
	6	* SPDX-License-Identifier: GPL-2.0
	7	*/
	8
	9	#include <common.h>
	10	#include <malloc.h>
9e116f64 NI	11	#include <dm.h>
9e116f64 NI	12	#include <dm/platform_data/serial_sh.h>
cff2f5f0 NI	13	#include <asm/processor.h>
	14	#include <asm/mach-types.h>
	15	#include <asm/io.h>
	16	#include <asm/errno.h>
	17	#include <asm/arch/sys_proto.h>
	18	#include <asm/gpio.h>
	19	#include <asm/arch/rmobile.h>
44e1eebf	20	#include <asm/arch/rcar-mstp.h>
2b8c0814	21	#include <asm/arch/mmc.h>
25f9613f	22	#include <asm/arch/sh_sdhi.h>
cff2f5f0 NI	23	#include <netdev.h>
	24	#include <miiphy.h>
	25	#include <i2c.h>
	26	#include <div64.h>
	27	#include "qos.h"
	28
	29	DECLARE_GLOBAL_DATA_PTR;
	30
	31	#define CLK2MHZ(clk) (clk / 1000 / 1000)
	32	void s_init(void)
	33	{
	34	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	35	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	36
	37	/* Watchdog init */
	38	writel(0xA5A5A500, &rwdt->rwtcsra);
	39	writel(0xA5A5A500, &swdt->swtcsra);
	40
	41	/* QoS */
	42	qos_init();
	43	}
	44
cff2f5f0	45	#define TMU0_MSTP125 (1 << 25)
0e429bdf	46	#define SCIF2_MSTP719 (1 << 19)
cff2f5f0	47	#define ETHER_MSTP813 (1 << 13)
92ef38ee	48	#define IIC1_MSTP323 (1 << 23)
2b8c0814	49	#define MMC0_MSTP315 (1 << 15)
25f9613f NI	50	#define SDHI0_MSTP314 (1 << 14)
	51	#define SDHI1_MSTP312 (1 << 12)
	52
	53	#define SD1CKCR 0xE6150078
	54	#define SD1_97500KHZ 0x7
92ef38ee	55
cff2f5f0 NI	56	int board_early_init_f(void)
	57	{
	58	/* TMU */
	59	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	60
0e429bdf NI	61	/* SCIF2 */
0e429bdf NI	62	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
cff2f5f0 NI	63
	64	/* ETHER */
	65	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
	66
92ef38ee NI	67	/* IIC1 / sh-i2c ch1 */
	68	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
	69
2b8c0814 NI	70	#ifdef CONFIG_SH_MMCIF
	71	/* MMC */
	72	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
	73	#endif
25f9613f NI	74
	75	#ifdef CONFIG_SH_SDHI
	76	/* SDHI0, 1 */
	77	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 \| SDHI1_MSTP312);
	78
	79	/*
	80	* SD0 clock is set to 97.5MHz by default.
	81	* Set SD1 to the 97.5MHz as well.
	82	*/
	83	writel(SD1_97500KHZ, SD1CKCR);
	84	#endif
cff2f5f0 NI	85	return 0;
	86	}
	87
cff2f5f0 NI	88	int board_init(void)
	89	{
	90	/* adress of boot parameters */
4772684c	91	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
cff2f5f0 NI	92
	93	/* Init PFC controller */
	94	r8a7794_pinmux_init();
	95
	96	/* Ether Enable */
cae72042 MK	97	#if defined(CONFIG_R8A7794_ETHERNET_B)
	98	gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
	99	gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
	100	gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
	101	gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
	102	gpio_request(GPIO_FN_ETH_LINK_B, NULL);
	103	gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
	104	gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
	105	gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
	106	gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
	107	gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
	108	gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
	109	gpio_request(GPIO_FN_ETH_MDC_B, NULL);
	110	#else
cff2f5f0 NI	111	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
	112	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
	113	gpio_request(GPIO_FN_ETH_RXD0, NULL);
	114	gpio_request(GPIO_FN_ETH_RXD1, NULL);
	115	gpio_request(GPIO_FN_ETH_LINK, NULL);
	116	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
	117	gpio_request(GPIO_FN_ETH_MDIO, NULL);
	118	gpio_request(GPIO_FN_ETH_TXD1, NULL);
	119	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
	120	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
	121	gpio_request(GPIO_FN_ETH_TXD0, NULL);
	122	gpio_request(GPIO_FN_ETH_MDC, NULL);
cae72042	123	#endif
cff2f5f0 NI	124	gpio_request(GPIO_FN_IRQ8, NULL);
	125
	126	/* PHY reset */
	127	gpio_request(GPIO_GP_1_24, NULL);
	128	gpio_direction_output(GPIO_GP_1_24, 0);
	129	mdelay(20);
	130	gpio_set_value(GPIO_GP_1_24, 1);
	131	udelay(1);
	132
	133	return 0;
	134	}
	135
	136	#define CXR24 0xEE7003C0 /* MAC address high register */
	137	#define CXR25 0xEE7003C8 /* MAC address low register */
	138	int board_eth_init(bd_t *bis)
	139	{
	140	#ifdef CONFIG_SH_ETHER
	141	int ret = -ENODEV;
	142	u32 val;
	143	unsigned char enetaddr[6];
	144
	145	ret = sh_eth_initialize(bis);
	146	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
	147	return ret;
	148
	149	/* Set Mac address */
	150	val = enetaddr[0] << 24 \| enetaddr[1] << 16 \|
	151	enetaddr[2] << 8 \| enetaddr[3];
	152	writel(val, CXR24);
	153
	154	val = enetaddr[4] << 8 \| enetaddr[5];
	155	writel(val, CXR25);
	156
	157	return ret;
	158	#else
	159	return 0;
	160	#endif
	161	}
	162
2b8c0814 NI	163	int board_mmc_init(bd_t *bis)
2b8c0814 NI	164	{
25f9613f	165	int ret = -ENODEV;
2b8c0814 NI	166
	167	#ifdef CONFIG_SH_MMCIF
	168	gpio_request(GPIO_GP_4_31, NULL);
	169	gpio_set_value(GPIO_GP_4_31, 1);
	170
	171	ret = mmcif_mmc_init();
	172	#endif
25f9613f NI	173
	174	#ifdef CONFIG_SH_SDHI
	175	gpio_request(GPIO_FN_SD0_DATA0, NULL);
	176	gpio_request(GPIO_FN_SD0_DATA1, NULL);
	177	gpio_request(GPIO_FN_SD0_DATA2, NULL);
	178	gpio_request(GPIO_FN_SD0_DATA3, NULL);
	179	gpio_request(GPIO_FN_SD0_CLK, NULL);
	180	gpio_request(GPIO_FN_SD0_CMD, NULL);
	181	gpio_request(GPIO_FN_SD0_CD, NULL);
	182	gpio_request(GPIO_FN_SD1_DATA0, NULL);
	183	gpio_request(GPIO_FN_SD1_DATA1, NULL);
	184	gpio_request(GPIO_FN_SD1_DATA2, NULL);
	185	gpio_request(GPIO_FN_SD1_DATA3, NULL);
	186	gpio_request(GPIO_FN_SD1_CLK, NULL);
	187	gpio_request(GPIO_FN_SD1_CMD, NULL);
	188	gpio_request(GPIO_FN_SD1_CD, NULL);
	189
	190	/* SDHI 0 */
	191	gpio_request(GPIO_GP_2_26, NULL);
	192	gpio_request(GPIO_GP_2_29, NULL);
	193	gpio_direction_output(GPIO_GP_2_26, 1);
	194	gpio_direction_output(GPIO_GP_2_29, 1);
	195
	196	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
	197	SH_SDHI_QUIRK_16BIT_BUF);
	198	if (ret)
	199	return ret;
	200
	201	/* SDHI 1 */
	202	gpio_request(GPIO_GP_4_26, NULL);
	203	gpio_request(GPIO_GP_4_29, NULL);
	204	gpio_direction_output(GPIO_GP_4_26, 1);
	205	gpio_direction_output(GPIO_GP_4_29, 1);
	206
	207	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
	208	#endif
2b8c0814 NI	209	return ret;
	210	}
	211
cff2f5f0 NI	212	int dram_init(void)
cff2f5f0 NI	213	{
cff2f5f0 NI	214	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	215
	216	return 0;
	217	}
	218
	219	const struct rmobile_sysinfo sysinfo = {
1cc95f6e	220	CONFIG_ARCH_RMOBILE_BOARD_STRING
cff2f5f0 NI	221	};
cff2f5f0 NI	222
cff2f5f0 NI	223	void reset_cpu(ulong addr)
	224	{
	225	u8 val;
	226
f063b32c	227	i2c_set_bus_num(1); /* PowerIC connected to ch1 */
cff2f5f0 NI	228	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
	229	val \|= 0x02;
	230	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
	231	}
9e116f64 NI	232
	233	static const struct sh_serial_platdata serial_platdata = {
	234	.base = SCIF2_BASE,
	235	.type = PORT_SCIF,
	236	.clk = 14745600,
	237	.clk_mode = EXT_CLK,
	238	};
	239
	240	U_BOOT_DEVICE(alt_serials) = {
	241	.name = "serial_sh",
	242	.platdata = &serial_platdata,
	243	};