projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| d21f08ba MV |
2 | /* |
| 3 | * board/renesas/eagle/eagle.c | |
| 4 | * This file is Eagle board support. | |
| 5 | * | |
| 6 | * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> | |
| d21f08ba MV |
7 | */ |
| 8 | ||
| 9 | #include <common.h> | |
| 10 | #include <malloc.h> | |
| 11 | #include <netdev.h> | |
| 12 | #include <dm.h> | |
| 13 | #include <dm/platform_data/serial_sh.h> | |
| 14 | #include <asm/processor.h> | |
| 15 | #include <asm/mach-types.h> | |
| 16 | #include <asm/io.h> | |
| 17 | #include <linux/errno.h> | |
| 18 | #include <asm/arch/sys_proto.h> | |
| 19 | #include <asm/gpio.h> | |
| 20 | #include <asm/arch/gpio.h> | |
| 21 | #include <asm/arch/rmobile.h> | |
| 22 | #include <asm/arch/rcar-mstp.h> | |
| 23 | #include <asm/arch/sh_sdhi.h> | |
| 24 | #include <i2c.h> | |
| 25 | #include <mmc.h> | |
| 26 | ||
| 27 | DECLARE_GLOBAL_DATA_PTR; | |
| 28 | ||
| 29 | #define CPGWPCR 0xE6150904 | |
| 30 | #define CPGWPR 0xE615090C | |
| 31 | ||
| 32 | /* PLL */ | |
| 33 | #define PLL0CR 0xE61500D8 | |
| 34 | #define PLL0_STC_MASK 0x7F000000 | |
| 35 | #define PLL0_STC_OFFSET 24 | |
| 36 | ||
| 37 | #define CLK2MHZ(clk) (clk / 1000 / 1000) | |
| 38 | void s_init(void) | |
| 39 | { | |
| 40 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; | |
| 41 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; | |
| 42 | u32 stc; | |
| 43 | ||
| 44 | /* Watchdog init */ | |
| 45 | writel(0xA5A5A500, &rwdt->rwtcsra); | |
| 46 | writel(0xA5A5A500, &swdt->swtcsra); | |
| 47 | ||
| 48 | /* CPU frequency setting. Set to 0.8GHz */ | |
| 49 | stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET; | |
| 50 | clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); | |
| 51 | } | |
| 52 | ||
| 53 | #define TMU0_MSTP125 BIT(25) /* secure */ | |
| 54 | ||
| 55 | int board_early_init_f(void) | |
| 56 | { | |
| 57 | writel(0xA5A5FFFF, CPGWPCR); | |
| 58 | writel(0x5A5A0000, CPGWPR); | |
| 59 | ||
| 60 | /* TMU0 */ | |
| 61 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); | |
| 62 | ||
| 63 | return 0; | |
| 64 | } | |
| 65 | ||
| 66 | int board_init(void) | |
| 67 | { | |
| 68 | /* adress of boot parameters */ | |
| 69 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; | |
| 70 | ||
| 71 | return 0; | |
| 72 | } | |
| 73 | ||
| 74 | int dram_init(void) | |
| 75 | { | |
| 76 | if (fdtdec_setup_memory_size() != 0) | |
| 77 | return -EINVAL; | |
| 78 | ||
| 79 | return 0; | |
| 80 | } | |
| 81 | ||
| 82 | int dram_init_banksize(void) | |
| 83 | { | |
| 84 | fdtdec_setup_memory_banksize(); | |
| 85 | ||
| 86 | return 0; | |
| 87 | } | |
| 88 | ||
| 89 | #define RST_BASE 0xE6160000 | |
| 90 | #define RST_CA57RESCNT (RST_BASE + 0x40) | |
| 91 | #define RST_CA53RESCNT (RST_BASE + 0x44) | |
| 92 | #define RST_RSTOUTCR (RST_BASE + 0x58) | |
| 93 | #define RST_CA57_CODE 0xA5A5000F | |
| 94 | #define RST_CA53_CODE 0x5A5A000F | |
| 95 | ||
| 96 | void reset_cpu(ulong addr) | |
| 97 | { | |
| 98 | unsigned long midr, cputype; | |
| 99 | ||
| 100 | asm volatile("mrs %0, midr_el1" : "=r" (midr)); | |
| 101 | cputype = (midr >> 4) & 0xfff; | |
| 102 | ||
| 103 | if (cputype == 0xd03) | |
| 104 | writel(RST_CA53_CODE, RST_CA53RESCNT); | |
| 105 | else if (cputype == 0xd07) | |
| 106 | writel(RST_CA57_CODE, RST_CA57RESCNT); | |
| 107 | else | |
| 108 | hang(); | |
| 109 | } |