]>
Commit | Line | Data |
---|---|---|
f4ec4522 NI |
1 | /* |
2 | * board/renesas/lager/lager.c | |
3 | * This file is lager board support. | |
4 | * | |
5 | * Copyright (C) 2013 Renesas Electronics Corporation | |
6 | * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0 | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <malloc.h> | |
13 | #include <netdev.h> | |
cf839572 NI |
14 | #include <dm.h> |
15 | #include <dm/platform_data/serial_sh.h> | |
f4ec4522 NI |
16 | #include <asm/processor.h> |
17 | #include <asm/mach-types.h> | |
18 | #include <asm/io.h> | |
19 | #include <asm/errno.h> | |
20 | #include <asm/arch/sys_proto.h> | |
21 | #include <asm/gpio.h> | |
22 | #include <asm/arch/rmobile.h> | |
44e1eebf | 23 | #include <asm/arch/rcar-mstp.h> |
d7916b1d | 24 | #include <asm/arch/mmc.h> |
acdfecbb | 25 | #include <asm/arch/sh_sdhi.h> |
23565c6b | 26 | #include <miiphy.h> |
b9986be0 | 27 | #include <i2c.h> |
d7916b1d | 28 | #include <mmc.h> |
f4ec4522 NI |
29 | #include "qos.h" |
30 | ||
31 | DECLARE_GLOBAL_DATA_PTR; | |
32 | ||
2c2c6ba6 | 33 | #define CLK2MHZ(clk) (clk / 1000 / 1000) |
f4ec4522 NI |
34 | void s_init(void) |
35 | { | |
dc535e10 NI |
36 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
37 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; | |
f4ec4522 NI |
38 | |
39 | /* Watchdog init */ | |
40 | writel(0xA5A5A500, &rwdt->rwtcsra); | |
41 | writel(0xA5A5A500, &swdt->swtcsra); | |
42 | ||
2c2c6ba6 | 43 | /* CPU frequency setting. Set to 1.4GHz */ |
f212a8ab | 44 | if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { |
d8659c6d | 45 | u32 stat = 0; |
f212a8ab NI |
46 | u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) |
47 | << PLL0_STC_BIT; | |
48 | clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); | |
d8659c6d NI |
49 | |
50 | do { | |
51 | stat = readl(PLLECR) & PLL0ST; | |
52 | } while (stat == 0x0); | |
f212a8ab | 53 | } |
2c2c6ba6 | 54 | |
f4ec4522 NI |
55 | /* QoS(Quality-of-Service) Init */ |
56 | qos_init(); | |
f4ec4522 NI |
57 | } |
58 | ||
f4ec4522 | 59 | #define TMU0_MSTP125 (1 << 25) |
f4ec4522 | 60 | #define SCIF0_MSTP721 (1 << 21) |
23565c6b | 61 | #define ETHER_MSTP813 (1 << 13) |
d7916b1d | 62 | #define MMC1_MSTP305 (1 << 5) |
23565c6b | 63 | |
acdfecbb NI |
64 | #define MSTPSR3 0xE6150048 |
65 | #define SMSTPCR3 0xE615013C | |
66 | #define SDHI0_MSTP314 (1 << 14) | |
67 | #define SDHI1_MSTP313 (1 << 13) | |
68 | #define SDHI2_MSTP312 (1 << 12) | |
69 | ||
70 | #define SD2CKCR 0xE6150078 | |
71 | #define SD2_97500KHZ 0x7 | |
72 | ||
f4ec4522 NI |
73 | int board_early_init_f(void) |
74 | { | |
75 | /* TMU0 */ | |
76 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); | |
f4ec4522 | 77 | /* SCIF0 */ |
f4ec4522 | 78 | mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); |
23565c6b NI |
79 | /* ETHER */ |
80 | mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); | |
d7916b1d NI |
81 | /* eMMC */ |
82 | mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305); | |
acdfecbb NI |
83 | /* SDHI0, 2 */ |
84 | mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); | |
85 | ||
86 | /* | |
87 | * SD0 clock is set to 97.5MHz by default. | |
88 | * Set SD2 to the 97.5MHz as well. | |
89 | */ | |
90 | writel(SD2_97500KHZ, SD2CKCR); | |
23565c6b | 91 | |
f4ec4522 NI |
92 | return 0; |
93 | } | |
94 | ||
95 | DECLARE_GLOBAL_DATA_PTR; | |
96 | int board_init(void) | |
97 | { | |
f4ec4522 | 98 | /* adress of boot parameters */ |
eeb266ab | 99 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
f4ec4522 NI |
100 | |
101 | /* Init PFC controller */ | |
102 | r8a7790_pinmux_init(); | |
103 | ||
23565c6b NI |
104 | /* ETHER Enable */ |
105 | gpio_request(GPIO_FN_ETH_CRS_DV, NULL); | |
106 | gpio_request(GPIO_FN_ETH_RX_ER, NULL); | |
107 | gpio_request(GPIO_FN_ETH_RXD0, NULL); | |
108 | gpio_request(GPIO_FN_ETH_RXD1, NULL); | |
109 | gpio_request(GPIO_FN_ETH_LINK, NULL); | |
110 | gpio_request(GPIO_FN_ETH_REF_CLK, NULL); | |
111 | gpio_request(GPIO_FN_ETH_MDIO, NULL); | |
112 | gpio_request(GPIO_FN_ETH_TXD1, NULL); | |
113 | gpio_request(GPIO_FN_ETH_TX_EN, NULL); | |
114 | gpio_request(GPIO_FN_ETH_MAGIC, NULL); | |
115 | gpio_request(GPIO_FN_ETH_TXD0, NULL); | |
116 | gpio_request(GPIO_FN_ETH_MDC, NULL); | |
117 | gpio_request(GPIO_FN_IRQ0, NULL); | |
118 | ||
119 | gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ | |
120 | gpio_direction_output(GPIO_GP_5_31, 0); | |
121 | mdelay(20); | |
122 | gpio_set_value(GPIO_GP_5_31, 1); | |
123 | udelay(1); | |
124 | ||
125 | return 0; | |
126 | } | |
127 | ||
128 | #define CXR24 0xEE7003C0 /* MAC address high register */ | |
129 | #define CXR25 0xEE7003C8 /* MAC address low register */ | |
130 | int board_eth_init(bd_t *bis) | |
131 | { | |
132 | int ret = -ENODEV; | |
133 | ||
134 | #ifdef CONFIG_SH_ETHER | |
135 | u32 val; | |
136 | unsigned char enetaddr[6]; | |
137 | ||
138 | ret = sh_eth_initialize(bis); | |
139 | if (!eth_getenv_enetaddr("ethaddr", enetaddr)) | |
140 | return ret; | |
141 | ||
142 | /* Set Mac address */ | |
143 | val = enetaddr[0] << 24 | enetaddr[1] << 16 | | |
144 | enetaddr[2] << 8 | enetaddr[3]; | |
145 | writel(val, CXR24); | |
146 | ||
147 | val = enetaddr[4] << 8 | enetaddr[5]; | |
148 | writel(val, CXR25); | |
149 | ||
150 | #endif | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
155 | /* lager has KSZ8041NL/RNL */ | |
156 | #define PHY_CONTROL1 0x1E | |
157 | #define PHY_LED_MODE 0xC0000 | |
158 | #define PHY_LED_MODE_ACK 0x4000 | |
159 | int board_phy_config(struct phy_device *phydev) | |
160 | { | |
161 | int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); | |
162 | ret &= ~PHY_LED_MODE; | |
163 | ret |= PHY_LED_MODE_ACK; | |
164 | ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); | |
165 | ||
f4ec4522 NI |
166 | return 0; |
167 | } | |
168 | ||
d7916b1d NI |
169 | int board_mmc_init(bd_t *bis) |
170 | { | |
acdfecbb | 171 | int ret = -ENODEV; |
d7916b1d NI |
172 | |
173 | #ifdef CONFIG_SH_MMCIF | |
174 | gpio_request(GPIO_FN_MMC1_D0, NULL); | |
175 | gpio_request(GPIO_FN_MMC1_D1, NULL); | |
176 | gpio_request(GPIO_FN_MMC1_D2, NULL); | |
177 | gpio_request(GPIO_FN_MMC1_D3, NULL); | |
178 | gpio_request(GPIO_FN_MMC1_D4, NULL); | |
179 | gpio_request(GPIO_FN_MMC1_D5, NULL); | |
180 | gpio_request(GPIO_FN_MMC1_D6, NULL); | |
181 | gpio_request(GPIO_FN_MMC1_D7, NULL); | |
182 | gpio_request(GPIO_FN_MMC1_CLK, NULL); | |
183 | gpio_request(GPIO_FN_MMC1_CMD, NULL); | |
184 | ||
185 | ret = mmcif_mmc_init(); | |
186 | #endif | |
acdfecbb NI |
187 | |
188 | #ifdef CONFIG_SH_SDHI | |
189 | gpio_request(GPIO_FN_SD0_DAT0, NULL); | |
190 | gpio_request(GPIO_FN_SD0_DAT1, NULL); | |
191 | gpio_request(GPIO_FN_SD0_DAT2, NULL); | |
192 | gpio_request(GPIO_FN_SD0_DAT3, NULL); | |
193 | gpio_request(GPIO_FN_SD0_CLK, NULL); | |
194 | gpio_request(GPIO_FN_SD0_CMD, NULL); | |
195 | gpio_request(GPIO_FN_SD0_CD, NULL); | |
196 | gpio_request(GPIO_FN_SD2_DAT0, NULL); | |
197 | gpio_request(GPIO_FN_SD2_DAT1, NULL); | |
198 | gpio_request(GPIO_FN_SD2_DAT2, NULL); | |
199 | gpio_request(GPIO_FN_SD2_DAT3, NULL); | |
200 | gpio_request(GPIO_FN_SD2_CLK, NULL); | |
201 | gpio_request(GPIO_FN_SD2_CMD, NULL); | |
202 | gpio_request(GPIO_FN_SD2_CD, NULL); | |
203 | ||
204 | /* | |
205 | * SDHI 0 | |
206 | * need JP3 set to pin-1 side on board. | |
207 | */ | |
208 | gpio_request(GPIO_GP_5_24, NULL); | |
209 | gpio_request(GPIO_GP_5_29, NULL); | |
210 | gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ | |
211 | gpio_direction_output(GPIO_GP_5_29, 1); /* 1: 3.3V, 0: 1.8V */ | |
212 | ||
213 | ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, | |
214 | SH_SDHI_QUIRK_16BIT_BUF); | |
215 | if (ret) | |
216 | return ret; | |
217 | ||
218 | /* SDHI 2 */ | |
219 | gpio_request(GPIO_GP_5_25, NULL); | |
220 | gpio_request(GPIO_GP_5_30, NULL); | |
221 | gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ | |
222 | gpio_direction_output(GPIO_GP_5_30, 1); /* 1: 3.3V, 0: 1.8V */ | |
223 | ||
224 | ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); | |
225 | #endif | |
d7916b1d NI |
226 | return ret; |
227 | } | |
228 | ||
229 | ||
f4ec4522 NI |
230 | int dram_init(void) |
231 | { | |
f4ec4522 NI |
232 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | const struct rmobile_sysinfo sysinfo = { | |
1cc95f6e | 238 | CONFIG_ARCH_RMOBILE_BOARD_STRING |
f4ec4522 NI |
239 | }; |
240 | ||
f4ec4522 NI |
241 | void reset_cpu(ulong addr) |
242 | { | |
b9986be0 NI |
243 | u8 val; |
244 | ||
245 | i2c_set_bus_num(3); /* PowerIC connected to ch3 */ | |
246 | i2c_init(400000, 0); | |
247 | i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); | |
248 | val |= 0x02; | |
249 | i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); | |
f4ec4522 | 250 | } |
cf839572 NI |
251 | |
252 | static const struct sh_serial_platdata serial_platdata = { | |
253 | .base = SCIF0_BASE, | |
254 | .type = PORT_SCIF, | |
255 | .clk = 14745600, | |
256 | .clk_mode = EXT_CLK, | |
257 | }; | |
258 | ||
259 | U_BOOT_DEVICE(lager_serials) = { | |
260 | .name = "serial_sh", | |
261 | .platdata = &serial_platdata, | |
262 | }; |