projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8ca805e1 NI |
1 | /* |
| 2 | * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
| 3 | * Copyright (C) 2011 Renesas Solutions Corp. | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 8ca805e1 NI |
6 | */ |
| 7 | #include <config.h> | |
| 8 | #include <version.h> | |
| 9 | #include <asm/processor.h> | |
| 10 | #include <asm/macro.h> | |
| 11 | ||
| 12 | #include <asm/processor.h> | |
| 13 | ||
| 14 | .global lowlevel_init | |
| 15 | ||
| 16 | .text | |
| 17 | .align 2 | |
| 18 | ||
| 19 | lowlevel_init: | |
| 20 | ||
| 21 | /* WDT */ | |
| 22 | write32 WDTCSR_A, WDTCSR_D | |
| 23 | ||
| 24 | /* MMU */ | |
| 25 | write32 MMUCR_A, MMUCR_D | |
| 26 | ||
| 27 | write32 FRQCR2_A, FRQCR2_D | |
| 28 | write32 FRQCR0_A, FRQCR0_D | |
| 29 | ||
| 30 | write32 CS0CTRL_A, CS0CTRL_D | |
| 31 | write32 CS1CTRL_A, CS1CTRL_D | |
| 32 | write32 CS0CTRL2_A, CS0CTRL2_D | |
| 33 | ||
| 34 | write32 CSPWCR0_A, CSPWCR0_D | |
| 35 | write32 CSPWCR1_A, CSPWCR1_D | |
| 36 | write32 CS1GDST_A, CS1GDST_D | |
| 37 | ||
| 38 | # clock mode check | |
| 39 | mov.l MODEMR, r1 | |
| 40 | mov.l @r1, r0 | |
| 41 | and #6, r0 /* Check 1 and 2 bit.*/ | |
| 42 | cmp/eq #2, r0 /* 0x02 is 533Mhz mode */ | |
| 43 | bt init_lbsc_533 | |
| 44 | ||
| 45 | init_lbsc_400: | |
| 46 | ||
| 47 | write32 CSWCR0_A, CSWCR0_D_400 | |
| 48 | write32 CSWCR1_A, CSWCR1_D | |
| 49 | ||
| 50 | bra init_dbsc3_400_pad | |
| 51 | nop | |
| 52 | ||
| 53 | .align 2 | |
| 54 | ||
| 55 | MODEMR: .long 0xFFCC0020 | |
| 56 | WDTCSR_A: .long 0xFFCC0004 | |
| 57 | WDTCSR_D: .long 0xA5000000 | |
| 58 | MMUCR_A: .long 0xFF000010 | |
| 59 | MMUCR_D: .long 0x00000004 | |
| 60 | ||
| 61 | FRQCR2_A: .long 0xFFC80008 | |
| 62 | FRQCR2_D: .long 0x00000000 | |
| 63 | FRQCR0_A: .long 0xFFC80000 | |
| 64 | FRQCR0_D: .long 0xCF000001 | |
| 65 | ||
| 66 | CS0CTRL_A: .long 0xFF800200 | |
| 67 | CS0CTRL_D: .long 0x00000020 | |
| 68 | CS1CTRL_A: .long 0xFF800204 | |
| 69 | CS1CTRL_D: .long 0x00000020 | |
| 70 | ||
| 71 | CS0CTRL2_A: .long 0xFF800220 | |
| 72 | CS0CTRL2_D: .long 0x00004000 | |
| 73 | ||
| 74 | CSPWCR0_A: .long 0xFF800280 | |
| 75 | CSPWCR0_D: .long 0x00000000 | |
| 76 | CSPWCR1_A: .long 0xFF800284 | |
| 77 | CSPWCR1_D: .long 0x00000000 | |
| 78 | CS1GDST_A: .long 0xFF8002C0 | |
| 79 | CS1GDST_D: .long 0x00000011 | |
| 80 | ||
| 81 | init_lbsc_533: | |
| 82 | ||
| 83 | write32 CSWCR0_A, CSWCR0_D_533 | |
| 84 | write32 CSWCR1_A, CSWCR1_D | |
| 85 | ||
| 86 | bra init_dbsc3_533_pad | |
| 87 | nop | |
| 88 | ||
| 89 | .align 2 | |
| 90 | ||
| 91 | CSWCR0_A: .long 0xFF800230 | |
| 92 | CSWCR0_D_533: .long 0x01120104 | |
| 93 | CSWCR0_D_400: .long 0x02120114 | |
| 94 | /* CSWCR0_D_400: .long 0x01160116 */ | |
| 95 | CSWCR1_A: .long 0xFF800234 | |
| 96 | CSWCR1_D: .long 0x077F077F | |
| 97 | /* CSWCR1_D_400: .long 0x00120012 */ | |
| 98 | ||
| 99 | init_dbsc3_400_pad: | |
| 100 | ||
| 101 | write32 DBPDCNT3_A, DBPDCNT3_D | |
| 102 | wait_timer WAIT_200US_400 | |
| 103 | ||
| 104 | write32 DBPDCNT0_A, DBPDCNT0_D_400 | |
| 105 | write32 DBPDCNT3_A, DBPDCNT3_D0 | |
| 106 | write32 DBPDCNT1_A, DBPDCNT1_D | |
| 107 | ||
| 108 | write32 DBPDCNT3_A, DBPDCNT3_D1 | |
| 109 | wait_timer WAIT_32MCLK | |
| 110 | ||
| 111 | write32 DBPDCNT3_A, DBPDCNT3_D2 | |
| 112 | wait_timer WAIT_100US_400 | |
| 113 | ||
| 114 | write32 DBPDCNT3_A, DBPDCNT3_D3 | |
| 115 | wait_timer WAIT_16MCLK | |
| 116 | ||
| 117 | write32 DBPDCNT3_A, DBPDCNT3_D4 | |
| 118 | wait_timer WAIT_200US_400 | |
| 119 | ||
| 120 | write32 DBPDCNT3_A, DBPDCNT3_D5 | |
| 121 | wait_timer WAIT_1MCLK | |
| 122 | ||
| 123 | write32 DBPDCNT3_A, DBPDCNT3_D6 | |
| 124 | wait_timer WAIT_10KMCLK | |
| 125 | ||
| 126 | bra init_dbsc3_ctrl_400 | |
| 127 | nop | |
| 128 | ||
| 129 | .align 2 | |
| 130 | ||
| 131 | init_dbsc3_533_pad: | |
| 132 | ||
| 133 | write32 DBPDCNT3_A, DBPDCNT3_D | |
| 134 | wait_timer WAIT_200US_533 | |
| 135 | ||
| 136 | write32 DBPDCNT0_A, DBPDCNT0_D_533 | |
| 137 | write32 DBPDCNT3_A, DBPDCNT3_D0 | |
| 138 | write32 DBPDCNT1_A, DBPDCNT1_D | |
| 139 | ||
| 140 | write32 DBPDCNT3_A, DBPDCNT3_D1 | |
| 141 | wait_timer WAIT_32MCLK | |
| 142 | ||
| 143 | write32 DBPDCNT3_A, DBPDCNT3_D2 | |
| 144 | wait_timer WAIT_100US_533 | |
| 145 | ||
| 146 | write32 DBPDCNT3_A, DBPDCNT3_D3 | |
| 147 | wait_timer WAIT_16MCLK | |
| 148 | ||
| 149 | write32 DBPDCNT3_A, DBPDCNT3_D4 | |
| 150 | wait_timer WAIT_200US_533 | |
| 151 | ||
| 152 | write32 DBPDCNT3_A, DBPDCNT3_D5 | |
| 153 | wait_timer WAIT_1MCLK | |
| 154 | ||
| 155 | write32 DBPDCNT3_A, DBPDCNT3_D6 | |
| 156 | wait_timer WAIT_10KMCLK | |
| 157 | ||
| 158 | bra init_dbsc3_ctrl_533 | |
| 159 | nop | |
| 160 | ||
| 161 | .align 2 | |
| 162 | ||
| 163 | WAIT_200US_400: .long 40000 | |
| 164 | WAIT_200US_533: .long 53300 | |
| 165 | WAIT_100US_400: .long 20000 | |
| 166 | WAIT_100US_533: .long 26650 | |
| 167 | WAIT_32MCLK: .long 32 | |
| 168 | WAIT_16MCLK: .long 16 | |
| 169 | WAIT_1MCLK: .long 1 | |
| 170 | WAIT_10KMCLK: .long 10000 | |
| 171 | ||
| 172 | DBPDCNT0_A: .long 0xFE800200 | |
| 173 | DBPDCNT0_D_533: .long 0x00010245 | |
| 174 | DBPDCNT0_D_400: .long 0x00010235 | |
| 175 | DBPDCNT1_A: .long 0xFE800204 | |
| 176 | DBPDCNT1_D: .long 0x00000014 | |
| 177 | DBPDCNT3_A: .long 0xFE80020C | |
| 178 | DBPDCNT3_D: .long 0x80000000 | |
| 179 | DBPDCNT3_D0: .long 0x800F0000 | |
| 180 | DBPDCNT3_D1: .long 0x800F1000 | |
| 181 | DBPDCNT3_D2: .long 0x820F1000 | |
| 182 | DBPDCNT3_D3: .long 0x860F1000 | |
| 183 | DBPDCNT3_D4: .long 0x870F1000 | |
| 184 | DBPDCNT3_D5: .long 0x870F3000 | |
| 185 | DBPDCNT3_D6: .long 0x870F7000 | |
| 186 | ||
| 187 | init_dbsc3_ctrl_400: | |
| 188 | ||
| 189 | write32 DBKIND_A, DBKIND_D | |
| 190 | write32 DBCONF_A, DBCONF_D | |
| 191 | ||
| 192 | write32 DBTR0_A, DBTR0_D_400 | |
| 193 | write32 DBTR1_A, DBTR1_D_400 | |
| 194 | write32 DBTR2_A, DBTR2_D | |
| 195 | write32 DBTR3_A, DBTR3_D_400 | |
| 196 | write32 DBTR4_A, DBTR4_D_400 | |
| 197 | write32 DBTR5_A, DBTR5_D_400 | |
| 198 | write32 DBTR6_A, DBTR6_D_400 | |
| 199 | write32 DBTR7_A, DBTR7_D | |
| 200 | write32 DBTR8_A, DBTR8_D_400 | |
| 201 | write32 DBTR9_A, DBTR9_D | |
| 202 | write32 DBTR10_A, DBTR10_D_400 | |
| 203 | write32 DBTR11_A, DBTR11_D | |
| 204 | write32 DBTR12_A, DBTR12_D_400 | |
| 205 | write32 DBTR13_A, DBTR13_D_400 | |
| 206 | write32 DBTR14_A, DBTR14_D | |
| 207 | write32 DBTR15_A, DBTR15_D | |
| 208 | write32 DBTR16_A, DBTR16_D_400 | |
| 209 | write32 DBTR17_A, DBTR17_D_400 | |
| 210 | write32 DBTR18_A, DBTR18_D_400 | |
| 211 | ||
| 212 | write32 DBBL_A, DBBL_D | |
| 213 | write32 DBRNK0_A, DBRNK0_D | |
| 214 | ||
| 215 | write32 DBCMD_A, DBCMD_D0_400 | |
| 216 | write32 DBCMD_A, DBCMD_D1 | |
| 217 | write32 DBCMD_A, DBCMD_D2 | |
| 218 | write32 DBCMD_A, DBCMD_D3 | |
| 219 | write32 DBCMD_A, DBCMD_D4 | |
| 220 | write32 DBCMD_A, DBCMD_D5_400 | |
| 221 | write32 DBCMD_A, DBCMD_D6 | |
| 222 | write32 DBCMD_A, DBCMD_D7 | |
| 223 | write32 DBCMD_A, DBCMD_D8 | |
| 224 | write32 DBCMD_A, DBCMD_D9_400 | |
| 225 | write32 DBCMD_A, DBCMD_D10 | |
| 226 | write32 DBCMD_A, DBCMD_D11 | |
| 227 | write32 DBCMD_A, DBCMD_D12 | |
| 228 | ||
| 229 | write32 DBBS0CNT1_A, DBBS0CNT1_D | |
| 230 | write32 DBPDNCNF_A, DBPDNCNF_D | |
| 231 | ||
| 232 | write32 DBRFCNF0_A, DBRFCNF0_D | |
| 233 | write32 DBRFCNF1_A, DBRFCNF1_D_400 | |
| 234 | write32 DBRFCNF2_A, DBRFCNF2_D | |
| 235 | write32 DBRFEN_A, DBRFEN_D | |
| 236 | write32 DBACEN_A, DBACEN_D | |
| 237 | write32 DBACEN_A, DBACEN_D | |
| 238 | ||
| 239 | /* Dummy read */ | |
| 240 | mov.l DBWAIT_A, r1 | |
| 241 | synco | |
| 242 | mov.l @r1, r0 | |
| 243 | synco | |
| 244 | ||
| 245 | /* Dummy read */ | |
| 246 | mov.l SDRAM_A, r1 | |
| 247 | synco | |
| 248 | mov.l @r1, r0 | |
| 249 | synco | |
| 250 | ||
| 251 | /* need sleep 186A0 */ | |
| 252 | ||
| 253 | bra init_pfc_sh7734 | |
| 254 | nop | |
| 255 | ||
| 256 | .align 2 | |
| 257 | ||
| 258 | init_dbsc3_ctrl_533: | |
| 259 | ||
| 260 | write32 DBKIND_A, DBKIND_D | |
| 261 | write32 DBCONF_A, DBCONF_D | |
| 262 | ||
| 263 | write32 DBTR0_A, DBTR0_D_533 | |
| 264 | write32 DBTR1_A, DBTR1_D_533 | |
| 265 | write32 DBTR2_A, DBTR2_D | |
| 266 | write32 DBTR3_A, DBTR3_D_533 | |
| 267 | write32 DBTR4_A, DBTR4_D_533 | |
| 268 | write32 DBTR5_A, DBTR5_D_533 | |
| 269 | write32 DBTR6_A, DBTR6_D_533 | |
| 270 | write32 DBTR7_A, DBTR7_D | |
| 271 | write32 DBTR8_A, DBTR8_D_533 | |
| 272 | write32 DBTR9_A, DBTR9_D | |
| 273 | write32 DBTR10_A, DBTR10_D_533 | |
| 274 | write32 DBTR11_A, DBTR11_D | |
| 275 | write32 DBTR12_A, DBTR12_D_533 | |
| 276 | write32 DBTR13_A, DBTR13_D_533 | |
| 277 | write32 DBTR14_A, DBTR14_D | |
| 278 | write32 DBTR15_A, DBTR15_D | |
| 279 | write32 DBTR16_A, DBTR16_D_533 | |
| 280 | write32 DBTR17_A, DBTR17_D_533 | |
| 281 | write32 DBTR18_A, DBTR18_D_533 | |
| 282 | ||
| 283 | write32 DBBL_A, DBBL_D | |
| 284 | write32 DBRNK0_A, DBRNK0_D | |
| 285 | ||
| 286 | write32 DBCMD_A, DBCMD_D0_533 | |
| 287 | write32 DBCMD_A, DBCMD_D1 | |
| 288 | write32 DBCMD_A, DBCMD_D2 | |
| 289 | write32 DBCMD_A, DBCMD_D3 | |
| 290 | write32 DBCMD_A, DBCMD_D4 | |
| 291 | write32 DBCMD_A, DBCMD_D5_533 | |
| 292 | write32 DBCMD_A, DBCMD_D6 | |
| 293 | write32 DBCMD_A, DBCMD_D7 | |
| 294 | write32 DBCMD_A, DBCMD_D8 | |
| 295 | write32 DBCMD_A, DBCMD_D9_533 | |
| 296 | write32 DBCMD_A, DBCMD_D10 | |
| 297 | write32 DBCMD_A, DBCMD_D11 | |
| 298 | write32 DBCMD_A, DBCMD_D12 | |
| 299 | ||
| 300 | write32 DBBS0CNT1_A, DBBS0CNT1_D | |
| 301 | write32 DBPDNCNF_A, DBPDNCNF_D | |
| 302 | ||
| 303 | write32 DBRFCNF0_A, DBRFCNF0_D | |
| 304 | write32 DBRFCNF1_A, DBRFCNF1_D_533 | |
| 305 | write32 DBRFCNF2_A, DBRFCNF2_D | |
| 306 | write32 DBRFEN_A, DBRFEN_D | |
| 307 | write32 DBACEN_A, DBACEN_D | |
| 308 | write32 DBACEN_A, DBACEN_D | |
| 309 | ||
| 310 | /* Dummy read */ | |
| 311 | mov.l DBWAIT_A, r1 | |
| 312 | synco | |
| 313 | mov.l @r1, r0 | |
| 314 | synco | |
| 315 | ||
| 316 | /* Dummy read */ | |
| 317 | mov.l SDRAM_A, r1 | |
| 318 | synco | |
| 319 | mov.l @r1, r0 | |
| 320 | synco | |
| 321 | ||
| 322 | /* need sleep 186A0 */ | |
| 323 | ||
| 324 | bra init_pfc_sh7734 | |
| 325 | nop | |
| 326 | ||
| 327 | .align 2 | |
| 328 | ||
| 329 | DBKIND_A: .long 0xFE800020 | |
| 330 | DBKIND_D: .long 0x00000005 | |
| 331 | DBCONF_A: .long 0xFE800024 | |
| 332 | DBCONF_D: .long 0x0D030A01 | |
| 333 | ||
| 334 | DBTR0_A: .long 0xFE800040 | |
| 335 | DBTR0_D_533:.long 0x00000004 | |
| 336 | DBTR0_D_400:.long 0x00000003 | |
| 337 | DBTR1_A: .long 0xFE800044 | |
| 338 | DBTR1_D_533:.long 0x00000003 | |
| 339 | DBTR1_D_400:.long 0x00000002 | |
| 340 | DBTR2_A: .long 0xFE800048 | |
| 341 | DBTR2_D: .long 0x00000000 | |
| 342 | DBTR3_A: .long 0xFE800050 | |
| 343 | DBTR3_D_533:.long 0x00000004 | |
| 344 | DBTR3_D_400:.long 0x00000003 | |
| 345 | ||
| 346 | DBTR4_A: .long 0xFE800054 | |
| 347 | DBTR4_D_533:.long 0x00050004 | |
| 348 | DBTR4_D_400:.long 0x00050003 | |
| 349 | ||
| 350 | DBTR5_A: .long 0xFE800058 | |
| 351 | DBTR5_D_533:.long 0x0000000F | |
| 352 | DBTR5_D_400:.long 0x0000000B | |
| 353 | ||
| 354 | DBTR6_A: .long 0xFE80005C | |
| 355 | DBTR6_D_533:.long 0x0000000B | |
| 356 | DBTR6_D_400:.long 0x00000008 | |
| 357 | ||
| 358 | DBTR7_A: .long 0xFE800060 | |
| 359 | DBTR7_D: .long 0x00000002 /* common value */ | |
| 360 | ||
| 361 | DBTR8_A: .long 0xFE800064 | |
| 362 | DBTR8_D_533:.long 0x0000000D | |
| 363 | DBTR8_D_400:.long 0x0000000A | |
| 364 | ||
| 365 | DBTR9_A: .long 0xFE800068 | |
| 366 | DBTR9_D: .long 0x00000002 /* common value */ | |
| 367 | ||
| 368 | DBTR10_A: .long 0xFE80006C | |
| 369 | DBTR10_D_533:.long 0x00000004 | |
| 370 | DBTR10_D_400:.long 0x00000003 | |
| 371 | ||
| 372 | DBTR11_A: .long 0xFE800070 | |
| 373 | DBTR11_D: .long 0x00000008 /* common value */ | |
| 374 | ||
| 375 | DBTR12_A: .long 0xFE800074 | |
| 376 | DBTR12_D_533:.long 0x00000009 | |
| 377 | DBTR12_D_400:.long 0x00000008 | |
| 378 | ||
| 379 | DBTR13_A: .long 0xFE800078 | |
| 380 | DBTR13_D_533:.long 0x00000022 | |
| 381 | DBTR13_D_400:.long 0x0000001A | |
| 382 | ||
| 383 | DBTR14_A: .long 0xFE80007C | |
| 384 | DBTR14_D: .long 0x00070002 /* common value */ | |
| 385 | ||
| 386 | DBTR15_A: .long 0xFE800080 | |
| 387 | DBTR15_D: .long 0x00000003 /* common value */ | |
| 388 | ||
| 389 | DBTR16_A: .long 0xFE800084 | |
| 390 | DBTR16_D_533:.long 0x120A1001 | |
| 391 | DBTR16_D_400:.long 0x12091001 | |
| 392 | ||
| 393 | DBTR17_A: .long 0xFE800088 | |
| 394 | DBTR17_D_533:.long 0x00040000 | |
| 395 | DBTR17_D_400:.long 0x00030000 | |
| 396 | ||
| 397 | DBTR18_A: .long 0xFE80008C | |
| 398 | DBTR18_D_533:.long 0x02010200 | |
| 399 | DBTR18_D_400:.long 0x02000207 | |
| 400 | ||
| 401 | DBBL_A: .long 0xFE8000B0 | |
| 402 | DBBL_D: .long 0x00000000 | |
| 403 | ||
| 404 | DBRNK0_A: .long 0xFE800100 | |
| 405 | DBRNK0_D: .long 0x00000001 | |
| 406 | ||
| 407 | DBCMD_A: .long 0xFE800018 | |
| 408 | DBCMD_D0_533: .long 0x1100006B | |
| 409 | DBCMD_D0_400: .long 0x11000050 | |
| 410 | DBCMD_D1: .long 0x0B000000 /* common value */ | |
| 411 | DBCMD_D2: .long 0x2A004000 /* common value */ | |
| 412 | DBCMD_D3: .long 0x2B006000 /* common value */ | |
| 413 | DBCMD_D4: .long 0x29002004 /* common value */ | |
| 414 | DBCMD_D5_533: .long 0x28000743 | |
| 415 | DBCMD_D5_400: .long 0x28000533 | |
| 416 | DBCMD_D6: .long 0x0B000000 /* common value */ | |
| 417 | DBCMD_D7: .long 0x0C000000 /* common value */ | |
| 418 | DBCMD_D8: .long 0x0C000000 /* common value */ | |
| 419 | DBCMD_D9_533: .long 0x28000643 | |
| 420 | DBCMD_D9_400: .long 0x28000433 | |
| 421 | DBCMD_D10: .long 0x000000C8 /* common value */ | |
| 422 | DBCMD_D11: .long 0x29002384 /* common value */ | |
| 423 | DBCMD_D12: .long 0x29002004 /* common value */ | |
| 424 | ||
| 425 | DBBS0CNT1_A: .long 0xFE800304 | |
| 426 | DBBS0CNT1_D: .long 0x00000000 | |
| 427 | DBPDNCNF_A: .long 0xFE800180 | |
| 428 | DBPDNCNF_D: .long 0x00000200 | |
| 429 | ||
| 430 | DBRFCNF0_A: .long 0xFE8000E0 | |
| 431 | DBRFCNF0_D: .long 0x000001FF | |
| 432 | DBRFCNF1_A: .long 0xFE8000E4 | |
| 433 | DBRFCNF1_D_533: .long 0x00000805 | |
| 434 | DBRFCNF1_D_400: .long 0x00000618 | |
| 435 | ||
| 436 | DBRFCNF2_A: .long 0xFE8000E8 | |
| 437 | DBRFCNF2_D: .long 0x00000000 | |
| 438 | ||
| 439 | DBRFEN_A: .long 0xFE800014 | |
| 440 | DBRFEN_D: .long 0x00000001 | |
| 441 | ||
| 442 | DBACEN_A: .long 0xFE800010 | |
| 443 | DBACEN_D: .long 0x00000001 | |
| 444 | ||
| 445 | DBWAIT_A: .long 0xFE80001C | |
| 446 | SDRAM_A: .long 0x0C000000 | |
| 447 | ||
| 448 | init_pfc_sh7734: | |
| 449 | write32 PFC_PMMR_A, PFC_PMMR_MODESEL1 | |
| 450 | write32 PFC_MODESEL1_A, PFC_MODESEL1_D | |
| 451 | ||
| 452 | write32 PFC_PMMR_A, PFC_PMMR_MODESEL2 | |
| 453 | write32 PFC_MODESEL2_A, PFC_MODESEL2_D | |
| 454 | ||
| 455 | write32 PFC_PMMR_A, PFC_PMMR_IPSR3 | |
| 456 | write32 PFC_IPSR3_A, PFC_IPSR3_D | |
| 457 | ||
| 458 | write32 PFC_PMMR_A, PFC_PMMR_IPSR4 | |
| 459 | write32 PFC_IPSR4_A, PFC_IPSR4_D | |
| 460 | ||
| 461 | write32 PFC_PMMR_A, PFC_PMMR_IPSR11 | |
| 462 | write32 PFC_IPSR11_A, PFC_IPSR11_D | |
| 463 | ||
| 464 | write32 PFC_PMMR_A, PFC_PMMR_GPSR0 | |
| 465 | write32 PFC_GPSR0_A, PFC_GPSR0_D | |
| 466 | ||
| 467 | write32 PFC_PMMR_A, PFC_PMMR_GPSR1 | |
| 468 | write32 PFC_GPSR1_A, PFC_GPSR1_D | |
| 469 | ||
| 470 | write32 PFC_PMMR_A, PFC_PMMR_GPSR2 | |
| 471 | write32 PFC_GPSR2_A, PFC_GPSR2_D | |
| 472 | ||
| 473 | write32 PFC_PMMR_A, PFC_PMMR_GPSR3 | |
| 474 | write32 PFC_GPSR3_A, PFC_GPSR3_D | |
| 475 | ||
| 476 | write32 PFC_PMMR_A, PFC_PMMR_GPSR4 | |
| 477 | write32 PFC_GPSR4_A, PFC_GPSR4_D | |
| 478 | ||
| 479 | write32 PFC_PMMR_A, PFC_PMMR_GPSR5 | |
| 480 | write32 PFC_GPSR5_A, PFC_GPSR5_D | |
| 481 | ||
| 482 | /* sleep 186A0 */ | |
| 483 | ||
| 484 | write32 GPIO2_INOUTSEL1_A, GPIO2_INOUTSEL1_D | |
| 485 | write32 GPIO1_OUTDT1_A, GPIO1_OUTDT1_D | |
| 486 | write32 GPIO2_INOUTSEL2_A, GPIO2_INOUTSEL2_D | |
| 487 | write32 GPIO2_OUTDT2_A, GPIO2_OUTDT2_D | |
| 488 | write32 GPIO4_INOUTSEL4_A, GPIO4_INOUTSEL4_D | |
| 489 | write32 GPIO4_OUTDT4_A, GPIO4_OUTDT4_D | |
| 490 | ||
| 491 | write32 CCR_A, CCR_D | |
| 492 | ||
| 493 | stc sr, r0 | |
| 494 | mov.l SR_MASK_D, r1 | |
| 495 | and r1, r0 | |
| 496 | ldc r0, sr | |
| 497 | ||
| 498 | rts | |
| 499 | nop | |
| 500 | ||
| 501 | .align 2 | |
| 502 | ||
| 503 | PFC_PMMR_A: .long 0xFFFC0000 | |
| 504 | ||
| 505 | /* MODESEL | |
| 506 | * 28: Select IEBUS Group B | |
| 507 | */ | |
| 508 | PFC_MODESEL1_A: .long 0xFFFC004C | |
| 509 | PFC_MODESEL1_D: .long 0x10000000 | |
| 510 | PFC_PMMR_MODESEL1: .long 0xEFFFFFFF | |
| 511 | ||
| 512 | /* MODESEL | |
| 513 | * 9: Select SCIF3 Group B | |
| 514 | * 7: Select SCIF2 Group B | |
| 515 | * 4: Select SCIF1 Group B | |
| 516 | */ | |
| 517 | PFC_MODESEL2_A: .long 0xFFFC0050 | |
| 518 | PFC_MODESEL2_D: .long 0x00000290 | |
| 519 | PFC_PMMR_MODESEL2: .long 0xFFFFFD6F | |
| 520 | ||
| 521 | # Enable functios | |
| 522 | # SD1_DAT2_A SD1_DAT1_A, SD1_DAT0_A, | |
| 523 | # EXWAIT0, RDW/RW, SD1_CMD_A, SD1_WP_A, | |
| 524 | # SD1_CD_A, TX3_B, RX3_B, CS1, D15 | |
| 525 | PFC_IPSR3_A: .long 0xFFFC0028 | |
| 526 | PFC_IPSR3_D: .long 0x09209248 | |
| 527 | PFC_PMMR_IPSR3: .long 0xF6DF6DB7 | |
| 528 | ||
| 529 | # Enable functios | |
| 530 | # RMII0_MDIO_A , RMII0_MDC_A, | |
| 531 | # RMII0_CRS_DV_A, RMII0_RX_ER_A, | |
| 532 | # RMII0_TXD_EN_A, MII0_RXD1_A | |
| 533 | PFC_IPSR4_A: .long 0xFFFC002C | |
| 534 | PFC_IPSR4_D: .long 0x0001B6DB | |
| 535 | PFC_PMMR_IPSR4: .long 0xFFFE4924 | |
| 536 | ||
| 537 | # Enable functios | |
| 538 | # DACK1, DREQ1, SD1_DAT3_A, SD1_CLK_A, IERX_B, | |
| 539 | # IETX_B, TX0_A, RMII0_TXD0_A, | |
| 540 | # RMII0_TXD1_A, RMII0_TXD0_A, SDSEL, SDA0, SDA1, SCL1 | |
| 541 | PFC_IPSR11_A: .long 0xFFFC0048 | |
| 542 | PFC_IPSR11_D: .long 0x002C89B0 | |
| 543 | PFC_PMMR_IPSR11:.long 0xFFD3764F | |
| 544 | ||
| 545 | PFC_GPSR0_A: .long 0xFFFC0004 | |
| 546 | PFC_GPSR0_D: .long 0xFFFFFFFF | |
| 547 | PFC_PMMR_GPSR0: .long 0x00000000 | |
| 548 | ||
| 549 | PFC_GPSR1_A: .long 0xFFFC0008 | |
| 550 | PFC_GPSR1_D: .long 0x7FBF7FFF | |
| 551 | PFC_PMMR_GPSR1: .long 0x80408000 | |
| 552 | ||
| 553 | PFC_GPSR2_A: .long 0xFFFC000C | |
| 554 | PFC_GPSR2_D: .long 0xBFC07EDF | |
| 555 | PFC_PMMR_GPSR2: .long 0x403F8120 | |
| 556 | ||
| 557 | PFC_GPSR3_A: .long 0xFFFC0010 | |
| 558 | PFC_GPSR3_D: .long 0xFFFFFFFF | |
| 559 | PFC_PMMR_GPSR3: .long 0x00000000 | |
| 560 | ||
| 561 | PFC_GPSR4_A: .long 0xFFFC0014 | |
| 562 | #if 0 /* orig */ | |
| 563 | PFC_GPSR4_D: .long 0xFFFFFFFF | |
| 564 | PFC_PMMR_GPSR4: .long 0x00000000 | |
| 565 | #else | |
| 566 | PFC_GPSR4_D: .long 0xFBFFFFFF | |
| 567 | PFC_PMMR_GPSR4: .long 0x04000000 | |
| 568 | #endif | |
| 569 | ||
| 570 | PFC_GPSR5_A: .long 0xFFFC0018 | |
| 571 | PFC_GPSR5_D: .long 0x00000C01 | |
| 572 | PFC_PMMR_GPSR5: .long 0xFFFFF3FE | |
| 573 | ||
| 574 | I2C_ICCR2_A: .long 0xFFC70001 | |
| 575 | I2C_ICCR2_D: .long 0x00 | |
| 576 | I2C_ICCR2_D1: .long 0x20 | |
| 577 | ||
| 578 | GPIO2_INOUTSEL1_A: .long 0xFFC41004 | |
| 579 | GPIO2_INOUTSEL1_D: .long 0x80408000 | |
| 580 | GPIO1_OUTDT1_A: .long 0xFFC41008 /* bit15: LED4, bit22: LED5 */ | |
| 581 | GPIO1_OUTDT1_D: .long 0x80408000 | |
| 582 | GPIO2_INOUTSEL2_A: .long 0xFFC42004 | |
| 583 | GPIO2_INOUTSEL2_D: .long 0x40000120 | |
| 584 | GPIO2_OUTDT2_A: .long 0xFFC42008 | |
| 585 | GPIO2_OUTDT2_D: .long 0x40000120 | |
| 586 | GPIO4_INOUTSEL4_A: .long 0xFFC44004 | |
| 587 | GPIO4_INOUTSEL4_D: .long 0x04000000 | |
| 588 | GPIO4_OUTDT4_A: .long 0xFFC44008 | |
| 589 | GPIO4_OUTDT4_D: .long 0x04000000 | |
| 590 | ||
| 591 | CCR_A: .long 0xFF00001C | |
| 592 | CCR_D: .long 0x0000090B | |
| 593 | SR_MASK_D: .long 0xEFFFFF0F |