projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 72fd3838 | 2 | /* |
| a7da6f8c | 3 | * board/renesas/rcar-common/common.c |
| 72fd3838 NI |
4 | * |
| 5 | * Copyright (C) 2013 Renesas Electronics Corporation | |
| 6 | * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
| 581183de | 7 | * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| 72fd3838 NI |
8 | */ |
| 9 | ||
| 10 | #include <common.h> | |
| 11 | #include <asm/io.h> | |
| 12 | #include <asm/arch/sys_proto.h> | |
| 13 | #include <asm/arch/rmobile.h> | |
| 14 | #include <asm/arch/rcar-mstp.h> | |
| 15 | ||
| 16 | #define TSTR0 0x04 | |
| 17 | #define TSTR0_STR0 0x01 | |
| 18 | ||
| 8e2e5886 NI |
19 | static struct mstp_ctl mstptbl[] = { |
| 20 | { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA, | |
| 21 | RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA }, | |
| 22 | { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA, | |
| 23 | RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA }, | |
| 24 | { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA, | |
| 25 | RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA }, | |
| 26 | { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA, | |
| 27 | RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA }, | |
| 28 | { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA, | |
| 29 | RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA }, | |
| 30 | { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA, | |
| 31 | RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA }, | |
| 581183de NI |
32 | #ifdef CONFIG_RCAR_GEN3 |
| 33 | { SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA, | |
| 34 | RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA }, | |
| 35 | #endif | |
| 8e2e5886 NI |
36 | { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA, |
| 37 | RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA }, | |
| 38 | { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA, | |
| 39 | RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA }, | |
| 40 | { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA, | |
| 41 | RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA }, | |
| 42 | { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA, | |
| 43 | RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA }, | |
| 44 | { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA, | |
| 45 | RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA }, | |
| 46 | }; | |
| 47 | ||
| 72fd3838 NI |
48 | void arch_preboot_os(void) |
| 49 | { | |
| 8e2e5886 NI |
50 | int i; |
| 51 | ||
| 72fd3838 NI |
52 | /* stop TMU0 */ |
| 53 | mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0); | |
| 54 | ||
| 8e2e5886 NI |
55 | /* Stop module clock */ |
| 56 | for (i = 0; i < ARRAY_SIZE(mstptbl); i++) { | |
| 4ebaba55 NI |
57 | mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr, |
| 58 | mstptbl[i].s_dis, | |
| 8e2e5886 | 59 | mstptbl[i].s_ena); |
| 4ebaba55 NI |
60 | mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr, |
| 61 | mstptbl[i].r_dis, | |
| 8e2e5886 NI |
62 | mstptbl[i].r_ena); |
| 63 | } | |
| 72fd3838 | 64 | } |