[thirdparty/u-boot.git] / board / renesas / sh7752evb / sh7752evb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2012  Renesas Solutions Corp.
 */

#include <common.h>
#include <command.h>
#include <env.h>
#include <flash.h>
#include <init.h>
#include <malloc.h>
#include <net.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmc.h>
#include <spi.h>
#include <spi_flash.h>

int checkboard(void)
{
	puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");

	return 0;
}

static void init_gpio(void)
{
	struct gpio_regs *gpio = GPIO_BASE;
	struct sermux_regs *sermux = SERMUX_BASE;

	/* GPIO */
	writew(0x0000, &gpio->pacr);	/* GETHER */
	writew(0x0001, &gpio->pbcr);	/* INTC */
	writew(0x0000, &gpio->pccr);	/* PWMU, INTC */
	writew(0xeaff, &gpio->pecr);	/* GPIO */
	writew(0x0000, &gpio->pfcr);	/* WDT */
	writew(0x0000, &gpio->phcr);	/* SPI1 */
	writew(0x0000, &gpio->picr);	/* SDHI */
	writew(0x0003, &gpio->pkcr);	/* SerMux */
	writew(0x0000, &gpio->plcr);	/* SerMux */
	writew(0x0000, &gpio->pmcr);	/* RIIC */
	writew(0x0000, &gpio->pncr);	/* USB, SGPIO */
	writew(0x0000, &gpio->pocr);	/* SGPIO */
	writew(0xd555, &gpio->pqcr);	/* GPIO */
	writew(0x0000, &gpio->prcr);	/* RIIC */
	writew(0x0000, &gpio->pscr);	/* RIIC */
	writeb(0x00, &gpio->pudr);
	writew(0x5555, &gpio->pucr);	/* Debug LED */
	writew(0x0000, &gpio->pvcr);	/* RSPI */
	writew(0x0000, &gpio->pwcr);	/* EVC */
	writew(0x0000, &gpio->pxcr);	/* LBSC */
	writew(0x0000, &gpio->pycr);	/* LBSC */
	writew(0x0000, &gpio->pzcr);	/* eMMC */
	writew(0xfe00, &gpio->psel0);
	writew(0xff00, &gpio->psel3);
	writew(0x771f, &gpio->psel4);
	writew(0x00ff, &gpio->psel6);
	writew(0xfc00, &gpio->psel7);

	writeb(0x10, &sermux->smr0);	/* SMR0: SerMux mode 0 */
}

static void init_usb_phy(void)
{
	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	struct usb1_port_regs *port = USB1_PORT_BASE;
	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;

	writew(0x0100, &phy->reset);		/* set reset */
	/* port0 = USB0, port1 = USB1 */
	writew(0x0002, &phy->portsel);
	writel(0x0001, &port->port1sel);	/* port1 = Host */
	writew(0x0111, &phy->reset);		/* clear reset */

	writew(0x4000, &common0->suspmode);
	writew(0x4000, &common1->suspmode);

#if defined(__LITTLE_ENDIAN)
	writel(0x00000000, &align->ehcidatac);
	writel(0x00000000, &align->ohcidatac);
#endif
}

static void init_gether_mdio(void)
{
	struct gpio_regs *gpio = GPIO_BASE;

	writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
	writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr);	/* Use ET0-MDIO */
}

static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
{
	struct ether_mac_regs *ether;
	unsigned char mac[6];
	unsigned long val;

	string_to_enetaddr(mac_string, mac);

	if (!channel)
		ether = GETHER0_MAC_BASE;
	else
		ether = GETHER1_MAC_BASE;

	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
	writel(val, &ether->mahr);
	val = (mac[4] << 8) | mac[5];
	writel(val, &ether->malr);
}

/*****************************************************************
 * This PMB must be set on this timing. The lowlevel_init is run on
 * Area 0(phys 0x00000000), so we have to map it.
 *
 * The new PMB table is following:
 * ent	virt		phys		v	sz	c	wt
 * 0	0xa0000000	0x40000000	1	128M	0	1
 * 1	0xa8000000	0x48000000	1	128M	0	1
 * 2	0xb0000000	0x50000000	1	128M	0	1
 * 3	0xb8000000	0x58000000	1	128M	0	1
 * 4	0x80000000	0x40000000	1	128M	1	1
 * 5	0x88000000	0x48000000	1	128M	1	1
 * 6	0x90000000	0x50000000	1	128M	1	1
 * 7	0x98000000	0x58000000	1	128M	1	1
 */
static void set_pmb_on_board_init(void)
{
	struct mmu_regs *mmu = MMU_BASE;

	/* clear ITLB */
	writel(0x00000004, &mmu->mmucr);

	/* delete PMB for SPIBOOT */
	writel(0, PMB_ADDR_BASE(0));
	writel(0, PMB_DATA_BASE(0));

	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	/*			ppn  ub v s1 s0  c  wt */
	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
}

int board_init(void)
{
	init_gpio();
	set_pmb_on_board_init();

	init_usb_phy();
	init_gether_mdio();

	return 0;
}

int board_mmc_init(bd_t *bis)
{
	struct gpio_regs *gpio = GPIO_BASE;

	writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
	writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
	udelay(1);
	writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr);	/* Release reset */
	udelay(200);

	return mmcif_mmc_init();
}

static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
#ifdef CONFIG_DEPRECATED
	struct spi_flash *spi;
	int ret;

	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (spi == NULL) {
		printf("%s: spi_flash probe failed.\n", __func__);
		return 1;
	}

	ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
	if (ret) {
		printf("%s: spi_flash read failed.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);
#endif

	return 0;
}

static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
{
	memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
		SH7752EVB_ETHERNET_MAC_SIZE);
	mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */

	return 0;
}

static void init_ethernet_mac(void)
{
	char mac_string[64];
	char env_string[64];
	int i;
	unsigned char *buf;

	buf = malloc(256);
	if (!buf) {
		printf("%s: malloc failed.\n", __func__);
		return;
	}
	get_sh_eth_mac_raw(buf, 256);

	/* Gigabit Ethernet */
	for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
		get_sh_eth_mac(i, mac_string, buf);
		if (i == 0)
			env_set("ethaddr", mac_string);
		else {
			sprintf(env_string, "eth%daddr", i);
			env_set(env_string, mac_string);
		}
		set_mac_to_sh_giga_eth_register(i, mac_string);
	}

	free(buf);
}

int board_late_init(void)
{
	init_ethernet_mac();

	return 0;
}

#ifdef CONFIG_DEPRECATED
int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	int i, ret;
	char mac_string[256];
	struct spi_flash *spi;
	unsigned char *buf;

	if (argc != 3) {
		buf = malloc(256);
		if (!buf) {
			printf("%s: malloc failed.\n", __func__);
			return 1;
		}

		get_sh_eth_mac_raw(buf, 256);

		/* print current MAC address */
		for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
			get_sh_eth_mac(i, mac_string, buf);
			printf("GETHERC ch%d = %s\n", i, mac_string);
		}
		free(buf);
		return 0;
	}

	/* new setting */
	memset(mac_string, 0xff, sizeof(mac_string));
	sprintf(mac_string, "%s\t%s",
		argv[1], argv[2]);

	/* write MAC data to SPI rom */
	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (!spi) {
		printf("%s: spi_flash probe failed.\n", __func__);
		return 1;
	}

	ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
				SH7752EVB_SPI_SECTOR_SIZE);
	if (ret) {
		printf("%s: spi_flash erase failed.\n", __func__);
		return 1;
	}

	ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
				sizeof(mac_string), mac_string);
	if (ret) {
		printf("%s: spi_flash write failed.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	puts("The writing of the MAC address to SPI ROM was completed.\n");

	return 0;
}

U_BOOT_CMD(
	write_mac,	3,	1,	do_write_mac,
	"write MAC address for GETHERC",
	"[GETHERC ch0] [GETHERC ch1]\n"
);
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1a2621ba YS	2	/*
1a2621ba YS	3	* Copyright (C) 2012 Renesas Solutions Corp.
1a2621ba YS	4	*/
	5
	6	#include <common.h>
09140113	7	#include <command.h>
9fb625ce	8	#include <env.h>
b79fdc76	9	#include <flash.h>
5255932f	10	#include <init.h>
1a2621ba	11	#include <malloc.h>
90526e9f	12	#include <net.h>
1a2621ba YS	13	#include <asm/processor.h>
	14	#include <asm/io.h>
	15	#include <asm/mmc.h>
ff0960f9	16	#include <spi.h>
1a2621ba YS	17	#include <spi_flash.h>
	18
	19	int checkboard(void)
	20	{
	21	puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
	22
	23	return 0;
	24	}
	25
	26	static void init_gpio(void)
	27	{
	28	struct gpio_regs *gpio = GPIO_BASE;
	29	struct sermux_regs *sermux = SERMUX_BASE;
	30
	31	/* GPIO */
	32	writew(0x0000, &gpio->pacr); /* GETHER */
	33	writew(0x0001, &gpio->pbcr); /* INTC */
	34	writew(0x0000, &gpio->pccr); /* PWMU, INTC */
	35	writew(0xeaff, &gpio->pecr); /* GPIO */
	36	writew(0x0000, &gpio->pfcr); /* WDT */
	37	writew(0x0000, &gpio->phcr); /* SPI1 */
	38	writew(0x0000, &gpio->picr); /* SDHI */
	39	writew(0x0003, &gpio->pkcr); /* SerMux */
	40	writew(0x0000, &gpio->plcr); /* SerMux */
	41	writew(0x0000, &gpio->pmcr); /* RIIC */
	42	writew(0x0000, &gpio->pncr); /* USB, SGPIO */
	43	writew(0x0000, &gpio->pocr); /* SGPIO */
	44	writew(0xd555, &gpio->pqcr); /* GPIO */
	45	writew(0x0000, &gpio->prcr); /* RIIC */
	46	writew(0x0000, &gpio->pscr); /* RIIC */
	47	writeb(0x00, &gpio->pudr);
	48	writew(0x5555, &gpio->pucr); /* Debug LED */
	49	writew(0x0000, &gpio->pvcr); /* RSPI */
	50	writew(0x0000, &gpio->pwcr); /* EVC */
	51	writew(0x0000, &gpio->pxcr); /* LBSC */
	52	writew(0x0000, &gpio->pycr); /* LBSC */
	53	writew(0x0000, &gpio->pzcr); /* eMMC */
	54	writew(0xfe00, &gpio->psel0);
	55	writew(0xff00, &gpio->psel3);
	56	writew(0x771f, &gpio->psel4);
	57	writew(0x00ff, &gpio->psel6);
	58	writew(0xfc00, &gpio->psel7);
	59
	60	writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
	61	}
	62
	63	static void init_usb_phy(void)
	64	{
	65	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	66	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	67	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	68	struct usb1_port_regs *port = USB1_PORT_BASE;
	69	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
	70
	71	writew(0x0100, &phy->reset); /* set reset */
	72	/* port0 = USB0, port1 = USB1 */
	73	writew(0x0002, &phy->portsel);
	74	writel(0x0001, &port->port1sel); /* port1 = Host */
	75	writew(0x0111, &phy->reset); /* clear reset */
	76
	77	writew(0x4000, &common0->suspmode);
	78	writew(0x4000, &common1->suspmode);
	79
	80	#if defined(__LITTLE_ENDIAN)
81	writel(0x00000000, &align->ehcidatac);
82	writel(0x00000000, &align->ohcidatac);
83	#endif
84	}
85
86	static void init_gether_mdio(void)
87	{
88	struct gpio_regs *gpio = GPIO_BASE;
89
90	writew(readw(&gpio->pgcr) \| 0x0004, &gpio->pgcr);
91	writeb(readb(&gpio->pgdr) \| 0x02, &gpio->pgdr); /* Use ET0-MDIO */
92	}
93
94	static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
95	{
96	struct ether_mac_regs *ether;
97	unsigned char mac[6];
98	unsigned long val;
99
fb8977c5	100	string_to_enetaddr(mac_string, mac);
1a2621ba YS	101
	102	if (!channel)
	103	ether = GETHER0_MAC_BASE;
	104	else
	105	ether = GETHER1_MAC_BASE;
	106
	107	val = (mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3];
	108	writel(val, &ether->mahr);
	109	val = (mac[4] << 8) \| mac[5];
	110	writel(val, &ether->malr);
	111	}
	112
	113	/*****************************************************************
	114	* This PMB must be set on this timing. The lowlevel_init is run on
	115	* Area 0(phys 0x00000000), so we have to map it.
	116	*
	117	* The new PMB table is following:
	118	* ent virt phys v sz c wt
	119	* 0 0xa0000000 0x40000000 1 128M 0 1
	120	* 1 0xa8000000 0x48000000 1 128M 0 1
	121	* 2 0xb0000000 0x50000000 1 128M 0 1
	122	* 3 0xb8000000 0x58000000 1 128M 0 1
	123	* 4 0x80000000 0x40000000 1 128M 1 1
	124	* 5 0x88000000 0x48000000 1 128M 1 1
	125	* 6 0x90000000 0x50000000 1 128M 1 1
	126	* 7 0x98000000 0x58000000 1 128M 1 1
	127	*/
	128	static void set_pmb_on_board_init(void)
	129	{
	130	struct mmu_regs *mmu = MMU_BASE;
	131
	132	/* clear ITLB */
	133	writel(0x00000004, &mmu->mmucr);
	134
	135	/* delete PMB for SPIBOOT */
	136	writel(0, PMB_ADDR_BASE(0));
	137	writel(0, PMB_DATA_BASE(0));
	138
	139	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	140	/* ppn ub v s1 s0 c wt */
	141	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	142	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	143	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	144	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	145	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	146	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	147	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	148	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	149	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	150	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	151	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	152	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
	153	}
	154
	155	int board_init(void)
	156	{
	157	init_gpio();
	158	set_pmb_on_board_init();
	159
	160	init_usb_phy();
	161	init_gether_mdio();
	162
	163	return 0;
	164	}
165
1a2621ba YS	166	int board_mmc_init(bd_t *bis)
	167	{
	168	struct gpio_regs *gpio = GPIO_BASE;
	169
	170	writew(readw(&gpio->pgcr) \| 0x0040, &gpio->pgcr);
	171	writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
	172	udelay(1);
	173	writeb(readb(&gpio->pgdr) \| 0x08, &gpio->pgdr); /* Release reset */
	174	udelay(200);
	175
	176	return mmcif_mmc_init();
	177	}
	178
	179	static int get_sh_eth_mac_raw(unsigned char *buf, int size)
	180	{
88369d33	181	#ifdef CONFIG_DEPRECATED
1a2621ba YS	182	struct spi_flash *spi;
	183	int ret;
	184
	185	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	186	if (spi == NULL) {
	187	printf("%s: spi_flash probe failed.\n", __func__);
	188	return 1;
	189	}
	190
	191	ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
	192	if (ret) {
	193	printf("%s: spi_flash read failed.\n", __func__);
	194	spi_flash_free(spi);
	195	return 1;
	196	}
	197	spi_flash_free(spi);
88369d33	198	#endif
1a2621ba YS	199
	200	return 0;
	201	}
	202
	203	static int get_sh_eth_mac(int channel, char mac_string, unsigned char buf)
	204	{
	205	memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
	206	SH7752EVB_ETHERNET_MAC_SIZE);
	207	mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
	208
	209	return 0;
	210	}
	211
	212	static void init_ethernet_mac(void)
	213	{
	214	char mac_string[64];
	215	char env_string[64];
	216	int i;
	217	unsigned char *buf;
	218
	219	buf = malloc(256);
	220	if (!buf) {
	221	printf("%s: malloc failed.\n", __func__);
	222	return;
	223	}
	224	get_sh_eth_mac_raw(buf, 256);
	225
	226	/* Gigabit Ethernet */
	227	for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
	228	get_sh_eth_mac(i, mac_string, buf);
	229	if (i == 0)
382bee57	230	env_set("ethaddr", mac_string);
1a2621ba YS	231	else {
1a2621ba YS	232	sprintf(env_string, "eth%daddr", i);
382bee57	233	env_set(env_string, mac_string);
1a2621ba YS	234	}
	235	set_mac_to_sh_giga_eth_register(i, mac_string);
	236	}
	237
	238	free(buf);
	239	}
	240
	241	int board_late_init(void)
	242	{
	243	init_ethernet_mac();
	244
	245	return 0;
	246	}
	247
88369d33	248	#ifdef CONFIG_DEPRECATED
09140113	249	int do_write_mac(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
1a2621ba YS	250	{
	251	int i, ret;
	252	char mac_string[256];
	253	struct spi_flash *spi;
	254	unsigned char *buf;
	255
	256	if (argc != 3) {
	257	buf = malloc(256);
	258	if (!buf) {
	259	printf("%s: malloc failed.\n", __func__);
	260	return 1;
	261	}
	262
	263	get_sh_eth_mac_raw(buf, 256);
	264
	265	/* print current MAC address */
	266	for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
	267	get_sh_eth_mac(i, mac_string, buf);
	268	printf("GETHERC ch%d = %s\n", i, mac_string);
	269	}
	270	free(buf);
	271	return 0;
	272	}
	273
	274	/* new setting */
	275	memset(mac_string, 0xff, sizeof(mac_string));
	276	sprintf(mac_string, "%s\t%s",
	277	argv[1], argv[2]);
	278
	279	/* write MAC data to SPI rom */
	280	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	281	if (!spi) {
	282	printf("%s: spi_flash probe failed.\n", __func__);
	283	return 1;
	284	}
	285
	286	ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
	287	SH7752EVB_SPI_SECTOR_SIZE);
	288	if (ret) {
	289	printf("%s: spi_flash erase failed.\n", __func__);
	290	return 1;
	291	}
	292
	293	ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
	294	sizeof(mac_string), mac_string);
	295	if (ret) {
	296	printf("%s: spi_flash write failed.\n", __func__);
	297	spi_flash_free(spi);
	298	return 1;
	299	}
	300	spi_flash_free(spi);
	301
	302	puts("The writing of the MAC address to SPI ROM was completed.\n");
	303
	304	return 0;
	305	}
	306
	307	U_BOOT_CMD(
	308	write_mac, 3, 1, do_write_mac,
	309	"write MAC address for GETHERC",
	310	"[GETHERC ch0] [GETHERC ch1]\n"
	311	);
88369d33	312	#endif