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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1a2621ba YS |
2 | /* |
3 | * Copyright (C) 2012 Renesas Solutions Corp. | |
1a2621ba YS |
4 | */ |
5 | ||
6 | #include <common.h> | |
9fb625ce | 7 | #include <env.h> |
b79fdc76 | 8 | #include <flash.h> |
5255932f | 9 | #include <init.h> |
1a2621ba YS |
10 | #include <malloc.h> |
11 | #include <asm/processor.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/mmc.h> | |
ff0960f9 | 14 | #include <spi.h> |
1a2621ba YS |
15 | #include <spi_flash.h> |
16 | ||
17 | int checkboard(void) | |
18 | { | |
19 | puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n"); | |
20 | ||
21 | return 0; | |
22 | } | |
23 | ||
24 | static void init_gpio(void) | |
25 | { | |
26 | struct gpio_regs *gpio = GPIO_BASE; | |
27 | struct sermux_regs *sermux = SERMUX_BASE; | |
28 | ||
29 | /* GPIO */ | |
30 | writew(0x0000, &gpio->pacr); /* GETHER */ | |
31 | writew(0x0001, &gpio->pbcr); /* INTC */ | |
32 | writew(0x0000, &gpio->pccr); /* PWMU, INTC */ | |
33 | writew(0xeaff, &gpio->pecr); /* GPIO */ | |
34 | writew(0x0000, &gpio->pfcr); /* WDT */ | |
35 | writew(0x0000, &gpio->phcr); /* SPI1 */ | |
36 | writew(0x0000, &gpio->picr); /* SDHI */ | |
37 | writew(0x0003, &gpio->pkcr); /* SerMux */ | |
38 | writew(0x0000, &gpio->plcr); /* SerMux */ | |
39 | writew(0x0000, &gpio->pmcr); /* RIIC */ | |
40 | writew(0x0000, &gpio->pncr); /* USB, SGPIO */ | |
41 | writew(0x0000, &gpio->pocr); /* SGPIO */ | |
42 | writew(0xd555, &gpio->pqcr); /* GPIO */ | |
43 | writew(0x0000, &gpio->prcr); /* RIIC */ | |
44 | writew(0x0000, &gpio->pscr); /* RIIC */ | |
45 | writeb(0x00, &gpio->pudr); | |
46 | writew(0x5555, &gpio->pucr); /* Debug LED */ | |
47 | writew(0x0000, &gpio->pvcr); /* RSPI */ | |
48 | writew(0x0000, &gpio->pwcr); /* EVC */ | |
49 | writew(0x0000, &gpio->pxcr); /* LBSC */ | |
50 | writew(0x0000, &gpio->pycr); /* LBSC */ | |
51 | writew(0x0000, &gpio->pzcr); /* eMMC */ | |
52 | writew(0xfe00, &gpio->psel0); | |
53 | writew(0xff00, &gpio->psel3); | |
54 | writew(0x771f, &gpio->psel4); | |
55 | writew(0x00ff, &gpio->psel6); | |
56 | writew(0xfc00, &gpio->psel7); | |
57 | ||
58 | writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ | |
59 | } | |
60 | ||
61 | static void init_usb_phy(void) | |
62 | { | |
63 | struct usb_common_regs *common0 = USB0_COMMON_BASE; | |
64 | struct usb_common_regs *common1 = USB1_COMMON_BASE; | |
65 | struct usb0_phy_regs *phy = USB0_PHY_BASE; | |
66 | struct usb1_port_regs *port = USB1_PORT_BASE; | |
67 | struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; | |
68 | ||
69 | writew(0x0100, &phy->reset); /* set reset */ | |
70 | /* port0 = USB0, port1 = USB1 */ | |
71 | writew(0x0002, &phy->portsel); | |
72 | writel(0x0001, &port->port1sel); /* port1 = Host */ | |
73 | writew(0x0111, &phy->reset); /* clear reset */ | |
74 | ||
75 | writew(0x4000, &common0->suspmode); | |
76 | writew(0x4000, &common1->suspmode); | |
77 | ||
78 | #if defined(__LITTLE_ENDIAN) | |
79 | writel(0x00000000, &align->ehcidatac); | |
80 | writel(0x00000000, &align->ohcidatac); | |
81 | #endif | |
82 | } | |
83 | ||
84 | static void init_gether_mdio(void) | |
85 | { | |
86 | struct gpio_regs *gpio = GPIO_BASE; | |
87 | ||
88 | writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); | |
89 | writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ | |
90 | } | |
91 | ||
92 | static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) | |
93 | { | |
94 | struct ether_mac_regs *ether; | |
95 | unsigned char mac[6]; | |
96 | unsigned long val; | |
97 | ||
fb8977c5 | 98 | string_to_enetaddr(mac_string, mac); |
1a2621ba YS |
99 | |
100 | if (!channel) | |
101 | ether = GETHER0_MAC_BASE; | |
102 | else | |
103 | ether = GETHER1_MAC_BASE; | |
104 | ||
105 | val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; | |
106 | writel(val, ðer->mahr); | |
107 | val = (mac[4] << 8) | mac[5]; | |
108 | writel(val, ðer->malr); | |
109 | } | |
110 | ||
111 | /***************************************************************** | |
112 | * This PMB must be set on this timing. The lowlevel_init is run on | |
113 | * Area 0(phys 0x00000000), so we have to map it. | |
114 | * | |
115 | * The new PMB table is following: | |
116 | * ent virt phys v sz c wt | |
117 | * 0 0xa0000000 0x40000000 1 128M 0 1 | |
118 | * 1 0xa8000000 0x48000000 1 128M 0 1 | |
119 | * 2 0xb0000000 0x50000000 1 128M 0 1 | |
120 | * 3 0xb8000000 0x58000000 1 128M 0 1 | |
121 | * 4 0x80000000 0x40000000 1 128M 1 1 | |
122 | * 5 0x88000000 0x48000000 1 128M 1 1 | |
123 | * 6 0x90000000 0x50000000 1 128M 1 1 | |
124 | * 7 0x98000000 0x58000000 1 128M 1 1 | |
125 | */ | |
126 | static void set_pmb_on_board_init(void) | |
127 | { | |
128 | struct mmu_regs *mmu = MMU_BASE; | |
129 | ||
130 | /* clear ITLB */ | |
131 | writel(0x00000004, &mmu->mmucr); | |
132 | ||
133 | /* delete PMB for SPIBOOT */ | |
134 | writel(0, PMB_ADDR_BASE(0)); | |
135 | writel(0, PMB_DATA_BASE(0)); | |
136 | ||
137 | /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ | |
138 | /* ppn ub v s1 s0 c wt */ | |
139 | writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); | |
140 | writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); | |
141 | writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); | |
142 | writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); | |
143 | writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); | |
144 | writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); | |
145 | writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); | |
146 | writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); | |
147 | writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); | |
148 | writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); | |
149 | writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); | |
150 | writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); | |
151 | } | |
152 | ||
153 | int board_init(void) | |
154 | { | |
155 | init_gpio(); | |
156 | set_pmb_on_board_init(); | |
157 | ||
158 | init_usb_phy(); | |
159 | init_gether_mdio(); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
1a2621ba YS |
164 | int board_mmc_init(bd_t *bis) |
165 | { | |
166 | struct gpio_regs *gpio = GPIO_BASE; | |
167 | ||
168 | writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); | |
169 | writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ | |
170 | udelay(1); | |
171 | writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ | |
172 | udelay(200); | |
173 | ||
174 | return mmcif_mmc_init(); | |
175 | } | |
176 | ||
177 | static int get_sh_eth_mac_raw(unsigned char *buf, int size) | |
178 | { | |
88369d33 | 179 | #ifdef CONFIG_DEPRECATED |
1a2621ba YS |
180 | struct spi_flash *spi; |
181 | int ret; | |
182 | ||
183 | spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); | |
184 | if (spi == NULL) { | |
185 | printf("%s: spi_flash probe failed.\n", __func__); | |
186 | return 1; | |
187 | } | |
188 | ||
189 | ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf); | |
190 | if (ret) { | |
191 | printf("%s: spi_flash read failed.\n", __func__); | |
192 | spi_flash_free(spi); | |
193 | return 1; | |
194 | } | |
195 | spi_flash_free(spi); | |
88369d33 | 196 | #endif |
1a2621ba YS |
197 | |
198 | return 0; | |
199 | } | |
200 | ||
201 | static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) | |
202 | { | |
203 | memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)], | |
204 | SH7752EVB_ETHERNET_MAC_SIZE); | |
205 | mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ | |
206 | ||
207 | return 0; | |
208 | } | |
209 | ||
210 | static void init_ethernet_mac(void) | |
211 | { | |
212 | char mac_string[64]; | |
213 | char env_string[64]; | |
214 | int i; | |
215 | unsigned char *buf; | |
216 | ||
217 | buf = malloc(256); | |
218 | if (!buf) { | |
219 | printf("%s: malloc failed.\n", __func__); | |
220 | return; | |
221 | } | |
222 | get_sh_eth_mac_raw(buf, 256); | |
223 | ||
224 | /* Gigabit Ethernet */ | |
225 | for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { | |
226 | get_sh_eth_mac(i, mac_string, buf); | |
227 | if (i == 0) | |
382bee57 | 228 | env_set("ethaddr", mac_string); |
1a2621ba YS |
229 | else { |
230 | sprintf(env_string, "eth%daddr", i); | |
382bee57 | 231 | env_set(env_string, mac_string); |
1a2621ba YS |
232 | } |
233 | set_mac_to_sh_giga_eth_register(i, mac_string); | |
234 | } | |
235 | ||
236 | free(buf); | |
237 | } | |
238 | ||
239 | int board_late_init(void) | |
240 | { | |
241 | init_ethernet_mac(); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
88369d33 | 246 | #ifdef CONFIG_DEPRECATED |
1a2621ba YS |
247 | int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
248 | { | |
249 | int i, ret; | |
250 | char mac_string[256]; | |
251 | struct spi_flash *spi; | |
252 | unsigned char *buf; | |
253 | ||
254 | if (argc != 3) { | |
255 | buf = malloc(256); | |
256 | if (!buf) { | |
257 | printf("%s: malloc failed.\n", __func__); | |
258 | return 1; | |
259 | } | |
260 | ||
261 | get_sh_eth_mac_raw(buf, 256); | |
262 | ||
263 | /* print current MAC address */ | |
264 | for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { | |
265 | get_sh_eth_mac(i, mac_string, buf); | |
266 | printf("GETHERC ch%d = %s\n", i, mac_string); | |
267 | } | |
268 | free(buf); | |
269 | return 0; | |
270 | } | |
271 | ||
272 | /* new setting */ | |
273 | memset(mac_string, 0xff, sizeof(mac_string)); | |
274 | sprintf(mac_string, "%s\t%s", | |
275 | argv[1], argv[2]); | |
276 | ||
277 | /* write MAC data to SPI rom */ | |
278 | spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); | |
279 | if (!spi) { | |
280 | printf("%s: spi_flash probe failed.\n", __func__); | |
281 | return 1; | |
282 | } | |
283 | ||
284 | ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, | |
285 | SH7752EVB_SPI_SECTOR_SIZE); | |
286 | if (ret) { | |
287 | printf("%s: spi_flash erase failed.\n", __func__); | |
288 | return 1; | |
289 | } | |
290 | ||
291 | ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, | |
292 | sizeof(mac_string), mac_string); | |
293 | if (ret) { | |
294 | printf("%s: spi_flash write failed.\n", __func__); | |
295 | spi_flash_free(spi); | |
296 | return 1; | |
297 | } | |
298 | spi_flash_free(spi); | |
299 | ||
300 | puts("The writing of the MAC address to SPI ROM was completed.\n"); | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | U_BOOT_CMD( | |
306 | write_mac, 3, 1, do_write_mac, | |
307 | "write MAC address for GETHERC", | |
308 | "[GETHERC ch0] [GETHERC ch1]\n" | |
309 | ); | |
88369d33 | 310 | #endif |