[people/ms/u-boot.git] / board / renesas / sh7757lcr / lowlevel_init.S

/*
 * Copyright (C) 2011  Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>

.macro	or32, addr, data
	mov.l \addr, r1
	mov.l \data, r0
	mov.l @r1, r2
	or    r2, r0
	mov.l r0, @r1
.endm

.macro	wait_DBCMD
	mov.l	DBWAIT_A, r0
	mov.l	@r0, r1
.endm

	.global lowlevel_init
	.section	.spiboot1.text
	.align  2

lowlevel_init:

	/*------- GPIO -------*/
	write8 PGDR_A,	PGDR_D	/* eMMC power off */

	write16 PACR_A,	PACR_D
	write16 PBCR_A,	PBCR_D
	write16 PCCR_A,	PCCR_D
	write16 PDCR_A,	PDCR_D
	write16 PECR_A,	PECR_D
	write16 PFCR_A,	PFCR_D
	write16 PGCR_A,	PGCR_D
	write16 PHCR_A,	PHCR_D
	write16 PICR_A,	PICR_D
	write16 PJCR_A,	PJCR_D
	write16 PKCR_A,	PKCR_D
	write16 PLCR_A,	PLCR_D
	write16 PMCR_A,	PMCR_D
	write16 PNCR_A,	PNCR_D
	write16 POCR_A,	POCR_D
	write16 PQCR_A,	PQCR_D
	write16 PRCR_A,	PRCR_D
	write16 PSCR_A,	PSCR_D
	write16 PTCR_A,	PTCR_D
	write16 PUCR_A,	PUCR_D
	write16 PVCR_A,	PVCR_D
	write16 PWCR_A,	PWCR_D
	write16 PXCR_A,	PXCR_D
	write16 PYCR_A,	PYCR_D
	write16 PZCR_A,	PZCR_D
	write16 PSEL0_A, PSEL0_D
	write16 PSEL1_A, PSEL1_D
	write16 PSEL2_A, PSEL2_D
	write16 PSEL3_A, PSEL3_D
	write16 PSEL4_A, PSEL4_D
	write16 PSEL5_A, PSEL5_D
	write16 PSEL6_A, PSEL6_D
	write16 PSEL7_A, PSEL7_D
	write16 PSEL8_A, PSEL8_D

	bra	exit_gpio
	nop

	.align	4

/*------- GPIO -------*/
PGDR_A:		.long	0xffec0040
PACR_A:		.long	0xffec0000
PBCR_A:		.long	0xffec0002
PCCR_A:		.long	0xffec0004
PDCR_A:		.long	0xffec0006
PECR_A:		.long	0xffec0008
PFCR_A:		.long	0xffec000a
PGCR_A:		.long	0xffec000c
PHCR_A:		.long	0xffec000e
PICR_A:		.long	0xffec0010
PJCR_A:		.long	0xffec0012
PKCR_A:		.long	0xffec0014
PLCR_A:		.long	0xffec0016
PMCR_A:		.long	0xffec0018
PNCR_A:		.long	0xffec001a
POCR_A:		.long	0xffec001c
PQCR_A:		.long	0xffec0020
PRCR_A:		.long	0xffec0022
PSCR_A:		.long	0xffec0024
PTCR_A:		.long	0xffec0026
PUCR_A:		.long	0xffec0028
PVCR_A:		.long	0xffec002a
PWCR_A:		.long	0xffec002c
PXCR_A:		.long	0xffec002e
PYCR_A:		.long	0xffec0030
PZCR_A:		.long	0xffec0032
PSEL0_A:	.long	0xffec0070
PSEL1_A:	.long	0xffec0072
PSEL2_A:	.long	0xffec0074
PSEL3_A:	.long	0xffec0076
PSEL4_A:	.long	0xffec0078
PSEL5_A:	.long	0xffec007a
PSEL6_A:	.long	0xffec007c
PSEL7_A:	.long	0xffec0082
PSEL8_A:	.long	0xffec0084

PGDR_D:		.long	0x80
PACR_D:		.long	0x0000
PBCR_D:		.long	0x0001
PCCR_D:		.long	0x0000
PDCR_D:		.long	0x0000
PECR_D:		.long	0x0000
PFCR_D:		.long	0x0000
PGCR_D:		.long	0x0000
PHCR_D:		.long	0x0000
PICR_D:		.long	0x0000
PJCR_D:		.long	0x0000
PKCR_D:		.long	0x0003
PLCR_D:		.long	0x0000
PMCR_D:		.long	0x0000
PNCR_D:		.long	0x0000
POCR_D:		.long	0x0000
PQCR_D:		.long	0xc000
PRCR_D:		.long	0x0000
PSCR_D:		.long	0x0000
PTCR_D:		.long	0x0000
#if defined(CONFIG_SH7757_OFFSET_SPI)
PUCR_D:		.long	0x0055
#else
PUCR_D:		.long	0x0000
#endif
PVCR_D:		.long	0x0000
PWCR_D:		.long	0x0000
PXCR_D:		.long	0x0000
PYCR_D:		.long	0x0000
PZCR_D:		.long	0x0000
PSEL0_D:	.long	0xfe00
PSEL1_D:	.long	0x0000
PSEL2_D:	.long	0x3000
PSEL3_D:	.long	0xff00
PSEL4_D:	.long	0x771f
PSEL5_D:	.long	0x0ffc
PSEL6_D:	.long	0x00ff
PSEL7_D:	.long	0xfc00
PSEL8_D:	.long	0x0000

	.align	2

exit_gpio:
	mov	#0, r14
	mova	2f, r0
	mov.l	PC_MASK, r1
	tst	r0, r1
	bf	2f

	bra	exit_pmb
	nop

	.align	2

/* If CPU runs on SDRAM, PC is 0x8???????. */
PC_MASK:	.long	0x20000000

2:
	mov	#1, r14

	mov.l	EXPEVT_A, r0
	mov.l	@r0, r0
	mov.l	EXPEVT_POWER_ON_RESET, r1
	cmp/eq	r0, r1
	bt	1f

	/*
	 * If EXPEVT value is manual reset or tlb multipul-hit,
	 * initialization of DDR3IF is not necessary.
	 */
	bra	exit_ddr
	nop

1:
	/* For Core Reset */
	mov.l	DBACEN_A, r0
	mov.l	@r0, r0
	cmp/eq	#0, r0
	bt	3f

	/*
	 * If DBACEN == 1(DBSC was already enabled), we have to avoid the
	 * initialization of DDR3-SDRAM.
	 */
	bra	exit_ddr
	nop

3:
	/*------- DDR3IF -------*/
	/* oscillation stabilization time */
	wait_timer	WAIT_OSC_TIME

	/* step 3 */
	write32 DBCMD_A, DBCMD_RSTL_VAL
	wait_timer	WAIT_30US

	/* step 4 */
	write32 DBCMD_A, DBCMD_PDEN_VAL

	/* step 5 */
	write32 DBKIND_A, DBKIND_D

	/* step 6 */
	write32 DBCONF_A, DBCONF_D
	write32 DBTR0_A, DBTR0_D
	write32 DBTR1_A, DBTR1_D
	write32 DBTR2_A, DBTR2_D
	write32 DBTR3_A, DBTR3_D
	write32 DBTR4_A, DBTR4_D
	write32 DBTR5_A, DBTR5_D
	write32 DBTR6_A, DBTR6_D
	write32 DBTR7_A, DBTR7_D
	write32 DBTR8_A, DBTR8_D
	write32 DBTR9_A, DBTR9_D
	write32 DBTR10_A, DBTR10_D
	write32 DBTR11_A, DBTR11_D
	write32 DBTR12_A, DBTR12_D
	write32 DBTR13_A, DBTR13_D
	write32 DBTR14_A, DBTR14_D
	write32 DBTR15_A, DBTR15_D
	write32 DBTR16_A, DBTR16_D
	write32 DBTR17_A, DBTR17_D
	write32 DBTR18_A, DBTR18_D
	write32 DBTR19_A, DBTR19_D
	write32 DBRNK0_A, DBRNK0_D

	/* step 7 */
	write32 DBPDCNT3_A, DBPDCNT3_D

	/* step 8 */
	write32 DBPDCNT1_A, DBPDCNT1_D
	write32 DBPDCNT2_A, DBPDCNT2_D
	write32 DBPDLCK_A, DBPDLCK_D
	write32 DBPDRGA_A, DBPDRGA_D
	write32 DBPDRGD_A, DBPDRGD_D

	/* step 9 */
	wait_timer	WAIT_30US

	/* step 10 */
	write32 DBPDCNT0_A, DBPDCNT0_D

	/* step 11 */
	wait_timer	WAIT_30US
	wait_timer	WAIT_30US

	/* step 12 */
	write32 DBCMD_A, DBCMD_WAIT_VAL
	wait_DBCMD

	/* step 13 */
	write32 DBCMD_A, DBCMD_RSTH_VAL
	wait_DBCMD

	/* step 14 */
	write32 DBCMD_A, DBCMD_WAIT_VAL
	write32 DBCMD_A, DBCMD_WAIT_VAL
	write32 DBCMD_A, DBCMD_WAIT_VAL
	write32 DBCMD_A, DBCMD_WAIT_VAL

	/* step 15 */
	write32 DBCMD_A, DBCMD_PDXT_VAL

	/* step 16 */
	write32 DBCMD_A, DBCMD_MRS2_VAL

	/* step 17 */
	write32 DBCMD_A, DBCMD_MRS3_VAL

	/* step 18 */
	write32 DBCMD_A, DBCMD_MRS1_VAL

	/* step 19 */
	write32 DBCMD_A, DBCMD_MRS0_VAL

	/* step 20 */
	write32 DBCMD_A, DBCMD_ZQCL_VAL

	write32 DBCMD_A, DBCMD_REF_VAL
	write32 DBCMD_A, DBCMD_REF_VAL
	wait_DBCMD

	/* step 21 */
	write32 DBADJ0_A, DBADJ0_D
	write32 DBADJ1_A, DBADJ1_D
	write32 DBADJ2_A, DBADJ2_D

	/* step 22 */
	write32 DBRFCNF0_A, DBRFCNF0_D
	write32 DBRFCNF1_A, DBRFCNF1_D
	write32 DBRFCNF2_A, DBRFCNF2_D

	/* step 23 */
	write32 DBCALCNF_A, DBCALCNF_D

	/* step 24 */
	write32 DBRFEN_A, DBRFEN_D
	write32 DBCMD_A, DBCMD_SRXT_VAL

	/* step 25 */
	write32 DBACEN_A, DBACEN_D

	/* step 26 */
	wait_DBCMD

#if defined(CONFIG_SH7757LCR_DDR_ECC)
	/* enable DDR-ECC */
	write32 ECD_ECDEN_A, ECD_ECDEN_D
	write32 ECD_INTSR_A, ECD_INTSR_D
	write32 ECD_SPACER_A, ECD_SPACER_D
	write32 ECD_MCR_A, ECD_MCR_D
#endif
	bra	exit_ddr
	nop

	.align 4

EXPEVT_A:		.long	0xff000024
EXPEVT_POWER_ON_RESET:	.long	0x00000000

/*------- DDR3IF -------*/
DBCMD_A:	.long	0xfe800018
DBKIND_A:	.long	0xfe800020
DBCONF_A:	.long	0xfe800024
DBTR0_A:	.long	0xfe800040
DBTR1_A:	.long	0xfe800044
DBTR2_A:	.long	0xfe800048
DBTR3_A:	.long	0xfe800050
DBTR4_A:	.long	0xfe800054
DBTR5_A:	.long	0xfe800058
DBTR6_A:	.long	0xfe80005c
DBTR7_A:	.long	0xfe800060
DBTR8_A:	.long	0xfe800064
DBTR9_A:	.long	0xfe800068
DBTR10_A:	.long	0xfe80006c
DBTR11_A:	.long	0xfe800070
DBTR12_A:	.long	0xfe800074
DBTR13_A:	.long	0xfe800078
DBTR14_A:	.long	0xfe80007c
DBTR15_A:	.long	0xfe800080
DBTR16_A:	.long	0xfe800084
DBTR17_A:	.long	0xfe800088
DBTR18_A:	.long	0xfe80008c
DBTR19_A:	.long	0xfe800090
DBRNK0_A:	.long	0xfe800100
DBPDCNT0_A:	.long	0xfe800200
DBPDCNT1_A:	.long	0xfe800204
DBPDCNT2_A:	.long	0xfe800208
DBPDCNT3_A:	.long	0xfe80020c
DBPDLCK_A:	.long	0xfe800280
DBPDRGA_A:	.long	0xfe800290
DBPDRGD_A:	.long	0xfe8002a0
DBADJ0_A:	.long	0xfe8000c0
DBADJ1_A:	.long	0xfe8000c4
DBADJ2_A:	.long	0xfe8000c8
DBRFCNF0_A:	.long	0xfe8000e0
DBRFCNF1_A:	.long	0xfe8000e4
DBRFCNF2_A:	.long	0xfe8000e8
DBCALCNF_A:	.long	0xfe8000f4
DBRFEN_A:	.long	0xfe800014
DBACEN_A:	.long	0xfe800010
DBWAIT_A:	.long	0xfe80001c

WAIT_OSC_TIME:	.long	6000
WAIT_30US:	.long	13333

DBCMD_RSTL_VAL:	.long	0x20000000
DBCMD_PDEN_VAL:	.long	0x1000d73c
DBCMD_WAIT_VAL:	.long	0x0000d73c
DBCMD_RSTH_VAL:	.long	0x2100d73c
DBCMD_PDXT_VAL:	.long	0x110000c8
DBCMD_MRS0_VAL:	.long	0x28000930
DBCMD_MRS1_VAL:	.long	0x29000004
DBCMD_MRS2_VAL:	.long	0x2a000008
DBCMD_MRS3_VAL:	.long	0x2b000000
DBCMD_ZQCL_VAL:	.long	0x03000200
DBCMD_REF_VAL:	.long	0x0c000000
DBCMD_SRXT_VAL:	.long	0x19000000
DBKIND_D:	.long	0x00000007
DBCONF_D:	.long	0x0f030a01
DBTR0_D:	.long	0x00000007
DBTR1_D:	.long	0x00000006
DBTR2_D:	.long	0x00000000
DBTR3_D:	.long	0x00000007
DBTR4_D:	.long	0x00070007
DBTR5_D:	.long	0x0000001b
DBTR6_D:	.long	0x00000014
DBTR7_D:	.long	0x00000005
DBTR8_D:	.long	0x00000015
DBTR9_D:	.long	0x00000006
DBTR10_D:	.long	0x00000008
DBTR11_D:	.long	0x00000007
DBTR12_D:	.long	0x0000000e
DBTR13_D:	.long	0x00000056
DBTR14_D:	.long	0x00000006
DBTR15_D:	.long	0x00000004
DBTR16_D:	.long	0x00150002
DBTR17_D:	.long	0x000c0017
DBTR18_D:	.long	0x00000200
DBTR19_D:	.long	0x00000040
DBRNK0_D:	.long	0x00000001
DBPDCNT0_D:	.long	0x00000001
DBPDCNT1_D:	.long	0x00000001
DBPDCNT2_D:	.long	0x00000000
DBPDCNT3_D:	.long	0x00004010
DBPDLCK_D:	.long	0x0000a55a
DBPDRGA_D:	.long	0x00000028
DBPDRGD_D:	.long	0x00017100

DBADJ0_D:	.long	0x00000000
DBADJ1_D:	.long	0x00000000
DBADJ2_D:	.long	0x18061806
DBRFCNF0_D:	.long	0x000001ff
DBRFCNF1_D:	.long	0x08001000
DBRFCNF2_D:	.long	0x00000000
DBCALCNF_D:	.long	0x0000ffff
DBRFEN_D:	.long	0x00000001
DBACEN_D:	.long	0x00000001

/*------- DDR-ECC -------*/
ECD_ECDEN_A:	.long	0xffc1012c
ECD_ECDEN_D:	.long	0x00000001
ECD_INTSR_A:	.long	0xfe900024
ECD_INTSR_D:	.long	0xffffffff
ECD_SPACER_A:	.long	0xfe900018
ECD_SPACER_D:	.long	SH7757LCR_SDRAM_ECC_SETTING
ECD_MCR_A:	.long	0xfe900010
ECD_MCR_D:	.long	0x00000001

	.align 2
exit_ddr:

#if defined(CONFIG_SH_32BIT)
	/*------- set PMB -------*/
	write32	PASCR_A,	PASCR_29BIT_D
	write32	MMUCR_A,	MMUCR_D

	/*****************************************************************
	 * ent	virt		phys		v	sz	c	wt
	 * 0	0xa0000000	0x00000000	1	128M	0	1
	 * 1	0xa8000000	0x48000000	1	128M	0	1
	 * 5	0x88000000	0x48000000	1	128M	1	1
	 */
	write32	PMB_ADDR_SPIBOOT_A,	PMB_ADDR_SPIBOOT_D
	write32	PMB_DATA_SPIBOOT_A,	PMB_DATA_SPIBOOT_D
	write32	PMB_ADDR_DDR_C1_A,	PMB_ADDR_DDR_C1_D
	write32	PMB_DATA_DDR_C1_A,	PMB_DATA_DDR_C1_D
	write32	PMB_ADDR_DDR_N1_A,	PMB_ADDR_DDR_N1_D
	write32	PMB_DATA_DDR_N1_A,	PMB_DATA_DDR_N1_D

	write32	PMB_ADDR_ENTRY2,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY3,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY4,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY6,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY7,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY8,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY9,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY10,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY11,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY12,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY13,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY14,	PMB_ADDR_NOT_USE_D
	write32	PMB_ADDR_ENTRY15,	PMB_ADDR_NOT_USE_D

	write32	PASCR_A,	PASCR_INIT
	mov.l	DUMMY_ADDR, r0
	icbi	@r0
#endif	/* if defined(CONFIG_SH_32BIT) */

exit_pmb:
	/* CPU is running on ILRAM? */
	mov	r14, r0
	tst	#1, r0
	bt	1f

	mov.l	_bss_start, r15
	mov.l	_spiboot_main, r0
100:	bsrf	r0
	nop

	.align	2
_spiboot_main:	.long	(spiboot_main - (100b + 4))
_bss_start:	.long	bss_start

1:

	write32	CCR_A,	CCR_D

	rts
	 nop

	.align 4

#if defined(CONFIG_SH_32BIT)
/*------- set PMB -------*/
PMB_ADDR_SPIBOOT_A:	.long	PMB_ADDR_BASE(0)
PMB_ADDR_DDR_N1_A:	.long	PMB_ADDR_BASE(1)
PMB_ADDR_DDR_C1_A:	.long	PMB_ADDR_BASE(5)
PMB_ADDR_ENTRY2:	.long	PMB_ADDR_BASE(2)
PMB_ADDR_ENTRY3:	.long	PMB_ADDR_BASE(3)
PMB_ADDR_ENTRY4:	.long	PMB_ADDR_BASE(4)
PMB_ADDR_ENTRY6:	.long	PMB_ADDR_BASE(6)
PMB_ADDR_ENTRY7:	.long	PMB_ADDR_BASE(7)
PMB_ADDR_ENTRY8:	.long	PMB_ADDR_BASE(8)
PMB_ADDR_ENTRY9:	.long	PMB_ADDR_BASE(9)
PMB_ADDR_ENTRY10:	.long	PMB_ADDR_BASE(10)
PMB_ADDR_ENTRY11:	.long	PMB_ADDR_BASE(11)
PMB_ADDR_ENTRY12:	.long	PMB_ADDR_BASE(12)
PMB_ADDR_ENTRY13:	.long	PMB_ADDR_BASE(13)
PMB_ADDR_ENTRY14:	.long	PMB_ADDR_BASE(14)
PMB_ADDR_ENTRY15:	.long	PMB_ADDR_BASE(15)

PMB_ADDR_SPIBOOT_D:	.long	mk_pmb_addr_val(0xa0)
PMB_ADDR_DDR_C1_D:	.long	mk_pmb_addr_val(0x88)
PMB_ADDR_DDR_N1_D:	.long	mk_pmb_addr_val(0xa8)
PMB_ADDR_NOT_USE_D:	.long	0x00000000

PMB_DATA_SPIBOOT_A:	.long	PMB_DATA_BASE(0)
PMB_DATA_DDR_N1_A:	.long	PMB_DATA_BASE(1)
PMB_DATA_DDR_C1_A:	.long	PMB_DATA_BASE(5)

/*						ppn   ub v s1 s0  c  wt */
PMB_DATA_SPIBOOT_D:	.long	mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
PMB_DATA_DDR_C1_D:	.long	mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
PMB_DATA_DDR_N1_D:	.long	mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)

PASCR_A:		.long	0xff000070
DUMMY_ADDR:		.long	0xa0000000
PASCR_29BIT_D:		.long	0x00000000
PASCR_INIT:		.long	0x80000080
MMUCR_A:		.long	0xff000010
MMUCR_D:		.long	0x00000004	/* clear ITLB */
#endif	/* CONFIG_SH_32BIT */

CCR_A:		.long	CCR
CCR_D:		.long	CCR_CACHE_INIT
Commit	Line	Data
8e9c897b YS	1	/*
	2	* Copyright (C) 2011 Renesas Solutions Corp.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
8e9c897b YS	5	*/
	6
	7	#include <config.h>
	8	#include <version.h>
	9	#include <asm/processor.h>
	10	#include <asm/macro.h>
	11
	12	.macro or32, addr, data
	13	mov.l \addr, r1
	14	mov.l \data, r0
	15	mov.l @r1, r2
	16	or r2, r0
	17	mov.l r0, @r1
	18	.endm
	19
	20	.macro wait_DBCMD
	21	mov.l DBWAIT_A, r0
	22	mov.l @r0, r1
	23	.endm
	24
	25	.global lowlevel_init
	26	.section .spiboot1.text
	27	.align 2
	28
	29	lowlevel_init:
	30
	31	/------- GPIO -------/
	32	write8 PGDR_A, PGDR_D /* eMMC power off */
	33
	34	write16 PACR_A, PACR_D
	35	write16 PBCR_A, PBCR_D
	36	write16 PCCR_A, PCCR_D
	37	write16 PDCR_A, PDCR_D
	38	write16 PECR_A, PECR_D
	39	write16 PFCR_A, PFCR_D
	40	write16 PGCR_A, PGCR_D
	41	write16 PHCR_A, PHCR_D
	42	write16 PICR_A, PICR_D
	43	write16 PJCR_A, PJCR_D
	44	write16 PKCR_A, PKCR_D
	45	write16 PLCR_A, PLCR_D
	46	write16 PMCR_A, PMCR_D
	47	write16 PNCR_A, PNCR_D
	48	write16 POCR_A, POCR_D
	49	write16 PQCR_A, PQCR_D
	50	write16 PRCR_A, PRCR_D
	51	write16 PSCR_A, PSCR_D
	52	write16 PTCR_A, PTCR_D
	53	write16 PUCR_A, PUCR_D
	54	write16 PVCR_A, PVCR_D
	55	write16 PWCR_A, PWCR_D
	56	write16 PXCR_A, PXCR_D
	57	write16 PYCR_A, PYCR_D
	58	write16 PZCR_A, PZCR_D
	59	write16 PSEL0_A, PSEL0_D
	60	write16 PSEL1_A, PSEL1_D
	61	write16 PSEL2_A, PSEL2_D
	62	write16 PSEL3_A, PSEL3_D
	63	write16 PSEL4_A, PSEL4_D
	64	write16 PSEL5_A, PSEL5_D
	65	write16 PSEL6_A, PSEL6_D
	66	write16 PSEL7_A, PSEL7_D
	67	write16 PSEL8_A, PSEL8_D
	68
69	bra exit_gpio
70	nop
71
72	.align 4
73
74	/------- GPIO -------/
75	PGDR_A: .long 0xffec0040
76	PACR_A: .long 0xffec0000
77	PBCR_A: .long 0xffec0002
78	PCCR_A: .long 0xffec0004
79	PDCR_A: .long 0xffec0006
80	PECR_A: .long 0xffec0008
81	PFCR_A: .long 0xffec000a
82	PGCR_A: .long 0xffec000c
83	PHCR_A: .long 0xffec000e
84	PICR_A: .long 0xffec0010
85	PJCR_A: .long 0xffec0012
86	PKCR_A: .long 0xffec0014
87	PLCR_A: .long 0xffec0016
88	PMCR_A: .long 0xffec0018
89	PNCR_A: .long 0xffec001a
90	POCR_A: .long 0xffec001c
91	PQCR_A: .long 0xffec0020
92	PRCR_A: .long 0xffec0022
93	PSCR_A: .long 0xffec0024
94	PTCR_A: .long 0xffec0026
95	PUCR_A: .long 0xffec0028
96	PVCR_A: .long 0xffec002a
97	PWCR_A: .long 0xffec002c
98	PXCR_A: .long 0xffec002e
99	PYCR_A: .long 0xffec0030
100	PZCR_A: .long 0xffec0032
101	PSEL0_A: .long 0xffec0070
102	PSEL1_A: .long 0xffec0072
103	PSEL2_A: .long 0xffec0074
104	PSEL3_A: .long 0xffec0076
105	PSEL4_A: .long 0xffec0078
106	PSEL5_A: .long 0xffec007a
107	PSEL6_A: .long 0xffec007c
108	PSEL7_A: .long 0xffec0082
109	PSEL8_A: .long 0xffec0084
110
111	PGDR_D: .long 0x80
112	PACR_D: .long 0x0000
113	PBCR_D: .long 0x0001
114	PCCR_D: .long 0x0000
115	PDCR_D: .long 0x0000
116	PECR_D: .long 0x0000
117	PFCR_D: .long 0x0000
118	PGCR_D: .long 0x0000
119	PHCR_D: .long 0x0000
120	PICR_D: .long 0x0000
121	PJCR_D: .long 0x0000
122	PKCR_D: .long 0x0003
123	PLCR_D: .long 0x0000
124	PMCR_D: .long 0x0000
125	PNCR_D: .long 0x0000
126	POCR_D: .long 0x0000
127	PQCR_D: .long 0xc000
128	PRCR_D: .long 0x0000
129	PSCR_D: .long 0x0000
130	PTCR_D: .long 0x0000
131	#if defined(CONFIG_SH7757_OFFSET_SPI)
132	PUCR_D: .long 0x0055
133	#else
134	PUCR_D: .long 0x0000
135	#endif
136	PVCR_D: .long 0x0000
137	PWCR_D: .long 0x0000
138	PXCR_D: .long 0x0000
139	PYCR_D: .long 0x0000
140	PZCR_D: .long 0x0000
141	PSEL0_D: .long 0xfe00
142	PSEL1_D: .long 0x0000
143	PSEL2_D: .long 0x3000
144	PSEL3_D: .long 0xff00
145	PSEL4_D: .long 0x771f
146	PSEL5_D: .long 0x0ffc
147	PSEL6_D: .long 0x00ff
148	PSEL7_D: .long 0xfc00
149	PSEL8_D: .long 0x0000
150
151	.align 2
152
153	exit_gpio:
154	mov #0, r14
155	mova 2f, r0
156	mov.l PC_MASK, r1
157	tst r0, r1
158	bf 2f
159
160	bra exit_pmb
161	nop
162
163	.align 2
164
165	/* If CPU runs on SDRAM, PC is 0x8???????. */
166	PC_MASK: .long 0x20000000
167
168	2:
169	mov #1, r14
170
171	mov.l EXPEVT_A, r0
172	mov.l @r0, r0
173	mov.l EXPEVT_POWER_ON_RESET, r1
174	cmp/eq r0, r1
175	bt 1f
176
177	/*
178	* If EXPEVT value is manual reset or tlb multipul-hit,
179	* initialization of DDR3IF is not necessary.
180	*/
181	bra exit_ddr
182	nop
183
184	1:
185	/* For Core Reset */
186	mov.l DBACEN_A, r0
187	mov.l @r0, r0
188	cmp/eq #0, r0
189	bt 3f
190
191	/*
192	* If DBACEN == 1(DBSC was already enabled), we have to avoid the
193	* initialization of DDR3-SDRAM.
194	*/
195	bra exit_ddr
196	nop
197
198	3:
199	/------- DDR3IF -------/
200	/* oscillation stabilization time */
201	wait_timer WAIT_OSC_TIME
202
203	/* step 3 */
204	write32 DBCMD_A, DBCMD_RSTL_VAL
205	wait_timer WAIT_30US
206
207	/* step 4 */
208	write32 DBCMD_A, DBCMD_PDEN_VAL
209
210	/* step 5 */
211	write32 DBKIND_A, DBKIND_D
212
213	/* step 6 */
214	write32 DBCONF_A, DBCONF_D
215	write32 DBTR0_A, DBTR0_D
216	write32 DBTR1_A, DBTR1_D
217	write32 DBTR2_A, DBTR2_D
218	write32 DBTR3_A, DBTR3_D
219	write32 DBTR4_A, DBTR4_D
220	write32 DBTR5_A, DBTR5_D
221	write32 DBTR6_A, DBTR6_D
222	write32 DBTR7_A, DBTR7_D
223	write32 DBTR8_A, DBTR8_D
224	write32 DBTR9_A, DBTR9_D
225	write32 DBTR10_A, DBTR10_D
226	write32 DBTR11_A, DBTR11_D
227	write32 DBTR12_A, DBTR12_D
228	write32 DBTR13_A, DBTR13_D
229	write32 DBTR14_A, DBTR14_D
230	write32 DBTR15_A, DBTR15_D
231	write32 DBTR16_A, DBTR16_D
232	write32 DBTR17_A, DBTR17_D
233	write32 DBTR18_A, DBTR18_D
234	write32 DBTR19_A, DBTR19_D
235	write32 DBRNK0_A, DBRNK0_D
236
237	/* step 7 */
238	write32 DBPDCNT3_A, DBPDCNT3_D
239
240	/* step 8 */
241	write32 DBPDCNT1_A, DBPDCNT1_D
242	write32 DBPDCNT2_A, DBPDCNT2_D
243	write32 DBPDLCK_A, DBPDLCK_D
244	write32 DBPDRGA_A, DBPDRGA_D
245	write32 DBPDRGD_A, DBPDRGD_D
246
247	/* step 9 */
248	wait_timer WAIT_30US
249
250	/* step 10 */
251	write32 DBPDCNT0_A, DBPDCNT0_D
252
253	/* step 11 */
254	wait_timer WAIT_30US
255	wait_timer WAIT_30US
256
257	/* step 12 */
258	write32 DBCMD_A, DBCMD_WAIT_VAL
259	wait_DBCMD
260
261	/* step 13 */
262	write32 DBCMD_A, DBCMD_RSTH_VAL
263	wait_DBCMD
264
265	/* step 14 */
266	write32 DBCMD_A, DBCMD_WAIT_VAL
267	write32 DBCMD_A, DBCMD_WAIT_VAL
268	write32 DBCMD_A, DBCMD_WAIT_VAL
269	write32 DBCMD_A, DBCMD_WAIT_VAL
270
271	/* step 15 */
272	write32 DBCMD_A, DBCMD_PDXT_VAL
273
274	/* step 16 */
275	write32 DBCMD_A, DBCMD_MRS2_VAL
276
277	/* step 17 */
278	write32 DBCMD_A, DBCMD_MRS3_VAL
279
280	/* step 18 */
281	write32 DBCMD_A, DBCMD_MRS1_VAL
282
283	/* step 19 */
284	write32 DBCMD_A, DBCMD_MRS0_VAL
285
286	/* step 20 */
287	write32 DBCMD_A, DBCMD_ZQCL_VAL
288
289	write32 DBCMD_A, DBCMD_REF_VAL
290	write32 DBCMD_A, DBCMD_REF_VAL
291	wait_DBCMD
292
293	/* step 21 */
294	write32 DBADJ0_A, DBADJ0_D
295	write32 DBADJ1_A, DBADJ1_D
296	write32 DBADJ2_A, DBADJ2_D
297
298	/* step 22 */
299	write32 DBRFCNF0_A, DBRFCNF0_D
300	write32 DBRFCNF1_A, DBRFCNF1_D
301	write32 DBRFCNF2_A, DBRFCNF2_D
302
303	/* step 23 */
304	write32 DBCALCNF_A, DBCALCNF_D
305
306	/* step 24 */
307	write32 DBRFEN_A, DBRFEN_D
308	write32 DBCMD_A, DBCMD_SRXT_VAL
309
310	/* step 25 */
311	write32 DBACEN_A, DBACEN_D
312
313	/* step 26 */
314	wait_DBCMD
315
3ed81645	316	#if defined(CONFIG_SH7757LCR_DDR_ECC)
8e9c897b YS	317	/* enable DDR-ECC */
	318	write32 ECD_ECDEN_A, ECD_ECDEN_D
	319	write32 ECD_INTSR_A, ECD_INTSR_D
	320	write32 ECD_SPACER_A, ECD_SPACER_D
	321	write32 ECD_MCR_A, ECD_MCR_D
3ed81645	322	#endif
8e9c897b YS	323	bra exit_ddr
	324	nop
	325
	326	.align 4
	327
	328	EXPEVT_A: .long 0xff000024
	329	EXPEVT_POWER_ON_RESET: .long 0x00000000
	330
	331	/------- DDR3IF -------/
	332	DBCMD_A: .long 0xfe800018
	333	DBKIND_A: .long 0xfe800020
	334	DBCONF_A: .long 0xfe800024
	335	DBTR0_A: .long 0xfe800040
	336	DBTR1_A: .long 0xfe800044
	337	DBTR2_A: .long 0xfe800048
	338	DBTR3_A: .long 0xfe800050
	339	DBTR4_A: .long 0xfe800054
	340	DBTR5_A: .long 0xfe800058
	341	DBTR6_A: .long 0xfe80005c
	342	DBTR7_A: .long 0xfe800060
	343	DBTR8_A: .long 0xfe800064
	344	DBTR9_A: .long 0xfe800068
	345	DBTR10_A: .long 0xfe80006c
	346	DBTR11_A: .long 0xfe800070
	347	DBTR12_A: .long 0xfe800074
	348	DBTR13_A: .long 0xfe800078
	349	DBTR14_A: .long 0xfe80007c
	350	DBTR15_A: .long 0xfe800080
	351	DBTR16_A: .long 0xfe800084
	352	DBTR17_A: .long 0xfe800088
	353	DBTR18_A: .long 0xfe80008c
	354	DBTR19_A: .long 0xfe800090
	355	DBRNK0_A: .long 0xfe800100
	356	DBPDCNT0_A: .long 0xfe800200
	357	DBPDCNT1_A: .long 0xfe800204
	358	DBPDCNT2_A: .long 0xfe800208
	359	DBPDCNT3_A: .long 0xfe80020c
	360	DBPDLCK_A: .long 0xfe800280
	361	DBPDRGA_A: .long 0xfe800290
	362	DBPDRGD_A: .long 0xfe8002a0
	363	DBADJ0_A: .long 0xfe8000c0
	364	DBADJ1_A: .long 0xfe8000c4
	365	DBADJ2_A: .long 0xfe8000c8
	366	DBRFCNF0_A: .long 0xfe8000e0
	367	DBRFCNF1_A: .long 0xfe8000e4
	368	DBRFCNF2_A: .long 0xfe8000e8
	369	DBCALCNF_A: .long 0xfe8000f4
	370	DBRFEN_A: .long 0xfe800014
	371	DBACEN_A: .long 0xfe800010
	372	DBWAIT_A: .long 0xfe80001c
	373
	374	WAIT_OSC_TIME: .long 6000
	375	WAIT_30US: .long 13333
	376
	377	DBCMD_RSTL_VAL: .long 0x20000000
	378	DBCMD_PDEN_VAL: .long 0x1000d73c
	379	DBCMD_WAIT_VAL: .long 0x0000d73c
	380	DBCMD_RSTH_VAL: .long 0x2100d73c
	381	DBCMD_PDXT_VAL: .long 0x110000c8
	382	DBCMD_MRS0_VAL: .long 0x28000930
	383	DBCMD_MRS1_VAL: .long 0x29000004
	384	DBCMD_MRS2_VAL: .long 0x2a000008
	385	DBCMD_MRS3_VAL: .long 0x2b000000
	386	DBCMD_ZQCL_VAL: .long 0x03000200
387	DBCMD_REF_VAL: .long 0x0c000000
388	DBCMD_SRXT_VAL: .long 0x19000000
389	DBKIND_D: .long 0x00000007
390	DBCONF_D: .long 0x0f030a01
391	DBTR0_D: .long 0x00000007
392	DBTR1_D: .long 0x00000006
393	DBTR2_D: .long 0x00000000
394	DBTR3_D: .long 0x00000007
395	DBTR4_D: .long 0x00070007
396	DBTR5_D: .long 0x0000001b
397	DBTR6_D: .long 0x00000014
398	DBTR7_D: .long 0x00000005
399	DBTR8_D: .long 0x00000015
400	DBTR9_D: .long 0x00000006
401	DBTR10_D: .long 0x00000008
402	DBTR11_D: .long 0x00000007
403	DBTR12_D: .long 0x0000000e
404	DBTR13_D: .long 0x00000056
405	DBTR14_D: .long 0x00000006
406	DBTR15_D: .long 0x00000004
407	DBTR16_D: .long 0x00150002
408	DBTR17_D: .long 0x000c0017
409	DBTR18_D: .long 0x00000200
410	DBTR19_D: .long 0x00000040
411	DBRNK0_D: .long 0x00000001
412	DBPDCNT0_D: .long 0x00000001
413	DBPDCNT1_D: .long 0x00000001
414	DBPDCNT2_D: .long 0x00000000
415	DBPDCNT3_D: .long 0x00004010
416	DBPDLCK_D: .long 0x0000a55a
417	DBPDRGA_D: .long 0x00000028
418	DBPDRGD_D: .long 0x00017100
419
420	DBADJ0_D: .long 0x00000000
421	DBADJ1_D: .long 0x00000000
422	DBADJ2_D: .long 0x18061806
423	DBRFCNF0_D: .long 0x000001ff
424	DBRFCNF1_D: .long 0x08001000
425	DBRFCNF2_D: .long 0x00000000
426	DBCALCNF_D: .long 0x0000ffff
427	DBRFEN_D: .long 0x00000001
428	DBACEN_D: .long 0x00000001
429
430	/------- DDR-ECC -------/
431	ECD_ECDEN_A: .long 0xffc1012c
432	ECD_ECDEN_D: .long 0x00000001
433	ECD_INTSR_A: .long 0xfe900024
434	ECD_INTSR_D: .long 0xffffffff
435	ECD_SPACER_A: .long 0xfe900018
436	ECD_SPACER_D: .long SH7757LCR_SDRAM_ECC_SETTING
437	ECD_MCR_A: .long 0xfe900010
438	ECD_MCR_D: .long 0x00000001
439
440	.align 2
441	exit_ddr:
442
443	#if defined(CONFIG_SH_32BIT)
444	/------- set PMB -------/
445	write32 PASCR_A, PASCR_29BIT_D
446	write32 MMUCR_A, MMUCR_D
447
448	/*****************************************************************
449	* ent virt phys v sz c wt
450	* 0 0xa0000000 0x00000000 1 128M 0 1
451	* 1 0xa8000000 0x48000000 1 128M 0 1
452	* 5 0x88000000 0x48000000 1 128M 1 1
453	*/
454	write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D
455	write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D
456	write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
457	write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
458	write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
459	write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
460
461	write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D
462	write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D
463	write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D
464	write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D
465	write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D
466	write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D
467	write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D
468	write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D
469	write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D
470	write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D
471	write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D
472	write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D
473	write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D
474
475	write32 PASCR_A, PASCR_INIT
476	mov.l DUMMY_ADDR, r0
477	icbi @r0
478	#endif /* if defined(CONFIG_SH_32BIT) */
479
480	exit_pmb:
481	/* CPU is running on ILRAM? */
482	mov r14, r0
483	tst #1, r0
484	bt 1f
485
486	mov.l _bss_start, r15
487	mov.l _spiboot_main, r0
488	100: bsrf r0
489	nop
490
491	.align 2
492	_spiboot_main: .long (spiboot_main - (100b + 4))
493	_bss_start: .long bss_start
494
495	1:
496
497	write32 CCR_A, CCR_D
498
499	rts
500	nop
501
502	.align 4
503
504	#if defined(CONFIG_SH_32BIT)
505	/------- set PMB -------/
506	PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0)
507	PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1)
508	PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5)
509	PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2)
510	PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3)
511	PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4)
512	PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6)
513	PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7)
514	PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8)
515	PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9)
516	PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10)
517	PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11)
518	PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12)
519	PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13)
520	PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14)
521	PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15)
522
523	PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0)
524	PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
525	PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
526	PMB_ADDR_NOT_USE_D: .long 0x00000000
527
528	PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0)
529	PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1)
530	PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5)
531
532	/* ppn ub v s1 s0 c wt */
533	PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
534	PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
535	PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
536
537	PASCR_A: .long 0xff000070
538	DUMMY_ADDR: .long 0xa0000000
539	PASCR_29BIT_D: .long 0x00000000
540	PASCR_INIT: .long 0x80000080
541	MMUCR_A: .long 0xff000010
542	MMUCR_D: .long 0x00000004 /* clear ITLB */
543	#endif /* CONFIG_SH_32BIT */
544
545	CCR_A: .long CCR
546	CCR_D: .long CCR_CACHE_INIT