[thirdparty/u-boot.git] / board / renesas / sh7757lcr / sh7757lcr.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2011  Renesas Solutions Corp.
 */

#include <common.h>
#include <command.h>
#include <env.h>
#include <flash.h>
#include <init.h>
#include <malloc.h>
#include <net.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmc.h>
#include <spi.h>
#include <spi_flash.h>

int checkboard(void)
{
	puts("BOARD: R0P7757LC0030RL board\n");

	return 0;
}

static void init_gctrl(void)
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	unsigned long graofst;

	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	writel(graofst | 0x20000f00, &gctrl->gracr3);
}

static int init_pcie_bridge_from_spi(void *buf, size_t size)
{
#ifdef CONFIG_DEPRECATED
	struct spi_flash *spi;
	int ret;
	unsigned long pcie_addr;

	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (!spi) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	if (is_sh7757_b0())
		pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
	else
		pcie_addr = SH7757LCR_PCIEBRG_ADDR;

	ret = spi_flash_read(spi, pcie_addr, size, buf);
	if (ret) {
		printf("%s: spi_flash read error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	return 0;
#else
	printf("No SPI support so no PCIe support\n");
	return 1;
#endif
}

static void init_pcie_bridge(void)
{
	struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	int i;
	unsigned char *data;
	unsigned short tmp;
	unsigned long pcie_size;

	if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
		return;

	if (is_sh7757_b0())
		pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
	else
		pcie_size = SH7757LCR_PCIEBRG_SIZE;

	data = malloc(pcie_size);
	if (!data) {
		printf("%s: malloc error.\n", __func__);
		return;
	}
	if (init_pcie_bridge_from_spi(data, pcie_size)) {
		free(data);
		return;
	}

	if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
	    data[3] == 0xff) {
		free(data);
		printf("%s: skipped initialization\n", __func__);
		return;
	}

	writew(0xa501, &pciebrg->ctrl_h8s);	/* reset */
	writew(0x0000, &pciebrg->cp_ctrl);
	writew(0x0000, &pciebrg->cp_addr);

	for (i = 0; i < pcie_size; i += 2) {
		tmp = (data[i] << 8) | data[i + 1];
		writew(tmp, &pciebrg->cp_data);
	}

	writew(0xa500, &pciebrg->ctrl_h8s);	/* start */
	if (!is_sh7757_b0())
		writel(0x00000001, &pcie_setup->pbictl3);

	free(data);
}

static void init_usb_phy(void)
{
	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	struct usb1_port_regs *port = USB1_PORT_BASE;
	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;

	writew(0x0100, &phy->reset);		/* set reset */
	/* port0 = USB0, port1 = USB1 */
	writew(0x0002, &phy->portsel);
	writel(0x0001, &port->port1sel);	/* port1 = Host */
	writew(0x0111, &phy->reset);		/* clear reset */

	writew(0x4000, &common0->suspmode);
	writew(0x4000, &common1->suspmode);

#if defined(__LITTLE_ENDIAN)
	writel(0x00000000, &align->ehcidatac);
	writel(0x00000000, &align->ohcidatac);
#endif
}

static void set_mac_to_sh_eth_register(int channel, char *mac_string)
{
	struct ether_mac_regs *ether;
	unsigned char mac[6];
	unsigned long val;

	string_to_enetaddr(mac_string, mac);

	if (!channel)
		ether = ETHER0_MAC_BASE;
	else
		ether = ETHER1_MAC_BASE;

	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
	writel(val, &ether->mahr);
	val = (mac[4] << 8) | mac[5];
	writel(val, &ether->malr);
}

static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
{
	struct ether_mac_regs *ether;
	unsigned char mac[6];
	unsigned long val;

	string_to_enetaddr(mac_string, mac);

	if (!channel)
		ether = GETHER0_MAC_BASE;
	else
		ether = GETHER1_MAC_BASE;

	val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
	writel(val, &ether->mahr);
	val = (mac[4] << 8) | mac[5];
	writel(val, &ether->malr);
}

/*****************************************************************
 * This PMB must be set on this timing. The lowlevel_init is run on
 * Area 0(phys 0x00000000), so we have to map it.
 *
 * The new PMB table is following:
 * ent	virt		phys		v	sz	c	wt
 * 0	0xa0000000	0x40000000	1	128M	0	1
 * 1	0xa8000000	0x48000000	1	128M	0	1
 * 2	0xb0000000	0x50000000	1	128M	0	1
 * 3	0xb8000000	0x58000000	1	128M	0	1
 * 4	0x80000000	0x40000000	1	128M	1	1
 * 5	0x88000000	0x48000000	1	128M	1	1
 * 6	0x90000000	0x50000000	1	128M	1	1
 * 7	0x98000000	0x58000000	1	128M	1	1
 */
static void set_pmb_on_board_init(void)
{
	struct mmu_regs *mmu = MMU_BASE;

	/* clear ITLB */
	writel(0x00000004, &mmu->mmucr);

	/* delete PMB for SPIBOOT */
	writel(0, PMB_ADDR_BASE(0));
	writel(0, PMB_DATA_BASE(0));

	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	/*			ppn  ub v s1 s0  c  wt */
	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
}

int board_init(void)
{
	struct gether_control_regs *gether = GETHER_CONTROL_BASE;

	set_pmb_on_board_init();

	/* enable RMII's MDIO (disable GRMII's MDIO) */
	writel(0x00030000, &gether->gbecont);

	init_gctrl();
	init_usb_phy();

	return 0;
}

int board_mmc_init(bd_t *bis)
{
	return mmcif_mmc_init();
}

static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
#ifdef CONFIG_DEPRECATED
	struct spi_flash *spi;
	int ret;

	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (spi == NULL) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
	if (ret) {
		printf("%s: spi_flash read error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);
#endif

	return 0;
}

static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
{
	memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
		SH7757LCR_ETHERNET_MAC_SIZE);
	mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00;	/* terminate */

	return 0;
}

static void init_ethernet_mac(void)
{
	char mac_string[64];
	char env_string[64];
	int i;
	unsigned char *buf;

	buf = malloc(256);
	if (!buf) {
		printf("%s: malloc error.\n", __func__);
		return;
	}
	get_sh_eth_mac_raw(buf, 256);

	/* Fast Ethernet */
	for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
		get_sh_eth_mac(i, mac_string, buf);
		if (i == 0)
			env_set("ethaddr", mac_string);
		else {
			sprintf(env_string, "eth%daddr", i);
			env_set(env_string, mac_string);
		}

		set_mac_to_sh_eth_register(i, mac_string);
	}

	/* Gigabit Ethernet */
	for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
		get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
		sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
		env_set(env_string, mac_string);

		set_mac_to_sh_giga_eth_register(i, mac_string);
	}

	free(buf);
}

static void init_pcie(void)
{
	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;

	writel(0x00000ff2, &pcie_setup->ladmsk0);
	writel(0x00000001, &pcie_setup->barmap);
	writel(0xffcaa000, &pcie_setup->lad0);
	writel(0x00030000, &pcie_sysbus->endictl0);
	writel(0x00000003, &pcie_sysbus->endictl1);
	writel(0x00000004, &pcie_setup->pbictl2);
}

static void finish_spiboot(void)
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	/*
	 *  SH7757 B0 does not use LBSC.
	 *  So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
	 *  This setting is not cleared by manual reset, So we have to set it
	 *  to 0.
	 */
	writel(0x00000000, &gctrl->spibootcan);
}

int board_late_init(void)
{
	init_ethernet_mac();
	init_pcie_bridge();
	init_pcie();
	finish_spiboot();

	return 0;
}

int do_sh_g200(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	struct gctrl_regs *gctrl = GCTRL_BASE;
	unsigned long graofst;

	writel(0xfedcba98, &gctrl->wprotect);
	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	writel(graofst | 0xa0000f00, &gctrl->gracr3);

	return 0;
}

U_BOOT_CMD(
	sh_g200,	1,	1,	do_sh_g200,
	"enable sh-g200",
	"enable SH-G200 bus (disable PCIe-G200)"
);

#ifdef CONFIG_DEPRECATED
int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	int i, ret;
	char mac_string[256];
	struct spi_flash *spi;
	unsigned char *buf;

	if (argc != 5) {
		buf = malloc(256);
		if (!buf) {
			printf("%s: malloc error.\n", __func__);
			return 1;
		}

		get_sh_eth_mac_raw(buf, 256);

		/* print current MAC address */
		for (i = 0; i < 4; i++) {
			get_sh_eth_mac(i, mac_string, buf);
			if (i < 2)
				printf(" ETHERC ch%d = %s\n", i, mac_string);
			else
				printf("GETHERC ch%d = %s\n", i-2, mac_string);
		}
		free(buf);
		return 0;
	}

	/* new setting */
	memset(mac_string, 0xff, sizeof(mac_string));
	sprintf(mac_string, "%s\t%s\t%s\t%s",
		argv[1], argv[2], argv[3], argv[4]);

	/* write MAC data to SPI rom */
	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	if (!spi) {
		printf("%s: spi_flash probe error.\n", __func__);
		return 1;
	}

	ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
				SH7757LCR_SPI_SECTOR_SIZE);
	if (ret) {
		printf("%s: spi_flash erase error.\n", __func__);
		return 1;
	}

	ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
				sizeof(mac_string), mac_string);
	if (ret) {
		printf("%s: spi_flash write error.\n", __func__);
		spi_flash_free(spi);
		return 1;
	}
	spi_flash_free(spi);

	puts("The writing of the MAC address to SPI ROM was completed.\n");

	return 0;
}

U_BOOT_CMD(
	write_mac,	5,	1,	do_write_mac,
	"write MAC address for ETHERC/GETHERC",
	"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
);
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8e9c897b YS	2	/*
8e9c897b YS	3	* Copyright (C) 2011 Renesas Solutions Corp.
8e9c897b YS	4	*/
	5
	6	#include <common.h>
09140113	7	#include <command.h>
9fb625ce	8	#include <env.h>
b79fdc76	9	#include <flash.h>
5255932f	10	#include <init.h>
8e9c897b	11	#include <malloc.h>
90526e9f	12	#include <net.h>
8e9c897b YS	13	#include <asm/processor.h>
8e9c897b YS	14	#include <asm/io.h>
4f0e8477	15	#include <asm/mmc.h>
ff0960f9	16	#include <spi.h>
8e9c897b YS	17	#include <spi_flash.h>
	18
	19	int checkboard(void)
	20	{
	21	puts("BOARD: R0P7757LC0030RL board\n");
	22
	23	return 0;
	24	}
	25
	26	static void init_gctrl(void)
	27	{
	28	struct gctrl_regs *gctrl = GCTRL_BASE;
	29	unsigned long graofst;
	30
	31	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	32	writel(graofst \| 0x20000f00, &gctrl->gracr3);
	33	}
	34
	35	static int init_pcie_bridge_from_spi(void *buf, size_t size)
	36	{
88369d33	37	#ifdef CONFIG_DEPRECATED
8e9c897b YS	38	struct spi_flash *spi;
	39	int ret;
	40	unsigned long pcie_addr;
	41
	42	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	43	if (!spi) {
	44	printf("%s: spi_flash probe error.\n", __func__);
	45	return 1;
	46	}
	47
	48	if (is_sh7757_b0())
	49	pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
	50	else
	51	pcie_addr = SH7757LCR_PCIEBRG_ADDR;
	52
	53	ret = spi_flash_read(spi, pcie_addr, size, buf);
	54	if (ret) {
	55	printf("%s: spi_flash read error.\n", __func__);
	56	spi_flash_free(spi);
	57	return 1;
	58	}
	59	spi_flash_free(spi);
	60
	61	return 0;
88369d33 TR	62	#else
	63	printf("No SPI support so no PCIe support\n");
	64	return 1;
	65	#endif
8e9c897b YS	66	}
	67
	68	static void init_pcie_bridge(void)
	69	{
	70	struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
	71	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	72	int i;
	73	unsigned char *data;
	74	unsigned short tmp;
	75	unsigned long pcie_size;
	76
	77	if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
	78	return;
	79
	80	if (is_sh7757_b0())
	81	pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
	82	else
	83	pcie_size = SH7757LCR_PCIEBRG_SIZE;
	84
	85	data = malloc(pcie_size);
	86	if (!data) {
	87	printf("%s: malloc error.\n", __func__);
	88	return;
	89	}
	90	if (init_pcie_bridge_from_spi(data, pcie_size)) {
	91	free(data);
	92	return;
	93	}
	94
	95	if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
	96	data[3] == 0xff) {
	97	free(data);
	98	printf("%s: skipped initialization\n", __func__);
	99	return;
	100	}
	101
	102	writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
	103	writew(0x0000, &pciebrg->cp_ctrl);
	104	writew(0x0000, &pciebrg->cp_addr);
	105
	106	for (i = 0; i < pcie_size; i += 2) {
	107	tmp = (data[i] << 8) \| data[i + 1];
	108	writew(tmp, &pciebrg->cp_data);
	109	}
	110
	111	writew(0xa500, &pciebrg->ctrl_h8s); /* start */
	112	if (!is_sh7757_b0())
	113	writel(0x00000001, &pcie_setup->pbictl3);
	114
	115	free(data);
	116	}
	117
	118	static void init_usb_phy(void)
	119	{
	120	struct usb_common_regs *common0 = USB0_COMMON_BASE;
	121	struct usb_common_regs *common1 = USB1_COMMON_BASE;
	122	struct usb0_phy_regs *phy = USB0_PHY_BASE;
	123	struct usb1_port_regs *port = USB1_PORT_BASE;
	124	struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
	125
	126	writew(0x0100, &phy->reset); /* set reset */
	127	/* port0 = USB0, port1 = USB1 */
	128	writew(0x0002, &phy->portsel);
	129	writel(0x0001, &port->port1sel); /* port1 = Host */
130	writew(0x0111, &phy->reset); /* clear reset */
131
132	writew(0x4000, &common0->suspmode);
133	writew(0x4000, &common1->suspmode);
134
135	#if defined(__LITTLE_ENDIAN)
136	writel(0x00000000, &align->ehcidatac);
137	writel(0x00000000, &align->ohcidatac);
138	#endif
139	}
140
141	static void set_mac_to_sh_eth_register(int channel, char *mac_string)
142	{
143	struct ether_mac_regs *ether;
144	unsigned char mac[6];
145	unsigned long val;
146
fb8977c5	147	string_to_enetaddr(mac_string, mac);
8e9c897b YS	148
	149	if (!channel)
	150	ether = ETHER0_MAC_BASE;
	151	else
	152	ether = ETHER1_MAC_BASE;
	153
	154	val = (mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3];
	155	writel(val, &ether->mahr);
	156	val = (mac[4] << 8) \| mac[5];
	157	writel(val, &ether->malr);
	158	}
	159
	160	static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
	161	{
	162	struct ether_mac_regs *ether;
	163	unsigned char mac[6];
	164	unsigned long val;
	165
fb8977c5	166	string_to_enetaddr(mac_string, mac);
8e9c897b YS	167
	168	if (!channel)
	169	ether = GETHER0_MAC_BASE;
	170	else
	171	ether = GETHER1_MAC_BASE;
	172
	173	val = (mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3];
	174	writel(val, &ether->mahr);
	175	val = (mac[4] << 8) \| mac[5];
	176	writel(val, &ether->malr);
	177	}
	178
	179	/*****************************************************************
	180	* This PMB must be set on this timing. The lowlevel_init is run on
	181	* Area 0(phys 0x00000000), so we have to map it.
	182	*
	183	* The new PMB table is following:
	184	* ent virt phys v sz c wt
	185	* 0 0xa0000000 0x40000000 1 128M 0 1
	186	* 1 0xa8000000 0x48000000 1 128M 0 1
	187	* 2 0xb0000000 0x50000000 1 128M 0 1
	188	* 3 0xb8000000 0x58000000 1 128M 0 1
	189	* 4 0x80000000 0x40000000 1 128M 1 1
	190	* 5 0x88000000 0x48000000 1 128M 1 1
	191	* 6 0x90000000 0x50000000 1 128M 1 1
	192	* 7 0x98000000 0x58000000 1 128M 1 1
	193	*/
	194	static void set_pmb_on_board_init(void)
	195	{
	196	struct mmu_regs *mmu = MMU_BASE;
	197
	198	/* clear ITLB */
	199	writel(0x00000004, &mmu->mmucr);
	200
	201	/* delete PMB for SPIBOOT */
	202	writel(0, PMB_ADDR_BASE(0));
	203	writel(0, PMB_DATA_BASE(0));
	204
	205	/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
	206	/* ppn ub v s1 s0 c wt */
	207	writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
	208	writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
	209	writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
	210	writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
	211	writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
	212	writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
	213	writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
	214	writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
	215	writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
	216	writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
	217	writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
	218	writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
	219	}
	220
	221	int board_init(void)
	222	{
	223	struct gether_control_regs *gether = GETHER_CONTROL_BASE;
	224
	225	set_pmb_on_board_init();
	226
	227	/* enable RMII's MDIO (disable GRMII's MDIO) */
	228	writel(0x00030000, &gether->gbecont);
	229
	230	init_gctrl();
231	init_usb_phy();
232
233	return 0;
234	}
235
566f63d5 YS	236	int board_mmc_init(bd_t *bis)
	237	{
	238	return mmcif_mmc_init();
	239	}
	240
8e9c897b YS	241	static int get_sh_eth_mac_raw(unsigned char *buf, int size)
8e9c897b YS	242	{
88369d33	243	#ifdef CONFIG_DEPRECATED
8e9c897b YS	244	struct spi_flash *spi;
	245	int ret;
	246
	247	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	248	if (spi == NULL) {
	249	printf("%s: spi_flash probe error.\n", __func__);
	250	return 1;
	251	}
	252
	253	ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
	254	if (ret) {
	255	printf("%s: spi_flash read error.\n", __func__);
	256	spi_flash_free(spi);
	257	return 1;
	258	}
	259	spi_flash_free(spi);
88369d33	260	#endif
8e9c897b YS	261
	262	return 0;
	263	}
	264
	265	static int get_sh_eth_mac(int channel, char mac_string, unsigned char buf)
	266	{
	267	memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
	268	SH7757LCR_ETHERNET_MAC_SIZE);
	269	mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
	270
	271	return 0;
	272	}
	273
	274	static void init_ethernet_mac(void)
	275	{
	276	char mac_string[64];
	277	char env_string[64];
	278	int i;
	279	unsigned char *buf;
	280
	281	buf = malloc(256);
	282	if (!buf) {
	283	printf("%s: malloc error.\n", __func__);
	284	return;
	285	}
	286	get_sh_eth_mac_raw(buf, 256);
	287
	288	/* Fast Ethernet */
	289	for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
	290	get_sh_eth_mac(i, mac_string, buf);
	291	if (i == 0)
382bee57	292	env_set("ethaddr", mac_string);
8e9c897b YS	293	else {
8e9c897b YS	294	sprintf(env_string, "eth%daddr", i);
382bee57	295	env_set(env_string, mac_string);
8e9c897b YS	296	}
	297
	298	set_mac_to_sh_eth_register(i, mac_string);
	299	}
	300
	301	/* Gigabit Ethernet */
	302	for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
	303	get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
	304	sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
382bee57	305	env_set(env_string, mac_string);
8e9c897b YS	306
	307	set_mac_to_sh_giga_eth_register(i, mac_string);
	308	}
	309
	310	free(buf);
	311	}
	312
	313	static void init_pcie(void)
	314	{
	315	struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
	316	struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
	317
	318	writel(0x00000ff2, &pcie_setup->ladmsk0);
	319	writel(0x00000001, &pcie_setup->barmap);
	320	writel(0xffcaa000, &pcie_setup->lad0);
	321	writel(0x00030000, &pcie_sysbus->endictl0);
	322	writel(0x00000003, &pcie_sysbus->endictl1);
	323	writel(0x00000004, &pcie_setup->pbictl2);
	324	}
	325
	326	static void finish_spiboot(void)
	327	{
	328	struct gctrl_regs *gctrl = GCTRL_BASE;
	329	/*
	330	* SH7757 B0 does not use LBSC.
	331	* So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
	332	* This setting is not cleared by manual reset, So we have to set it
	333	* to 0.
	334	*/
	335	writel(0x00000000, &gctrl->spibootcan);
	336	}
	337
	338	int board_late_init(void)
	339	{
	340	init_ethernet_mac();
	341	init_pcie_bridge();
	342	init_pcie();
	343	finish_spiboot();
	344
	345	return 0;
	346	}
	347
09140113	348	int do_sh_g200(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
8e9c897b YS	349	{
	350	struct gctrl_regs *gctrl = GCTRL_BASE;
	351	unsigned long graofst;
	352
	353	writel(0xfedcba98, &gctrl->wprotect);
	354	graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
	355	writel(graofst \| 0xa0000f00, &gctrl->gracr3);
	356
	357	return 0;
	358	}
	359
	360	U_BOOT_CMD(
	361	sh_g200, 1, 1, do_sh_g200,
	362	"enable sh-g200",
	363	"enable SH-G200 bus (disable PCIe-G200)"
	364	);
	365
88369d33	366	#ifdef CONFIG_DEPRECATED
09140113	367	int do_write_mac(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
8e9c897b YS	368	{
	369	int i, ret;
	370	char mac_string[256];
	371	struct spi_flash *spi;
	372	unsigned char *buf;
	373
	374	if (argc != 5) {
	375	buf = malloc(256);
	376	if (!buf) {
	377	printf("%s: malloc error.\n", __func__);
	378	return 1;
	379	}
	380
	381	get_sh_eth_mac_raw(buf, 256);
	382
	383	/* print current MAC address */
	384	for (i = 0; i < 4; i++) {
	385	get_sh_eth_mac(i, mac_string, buf);
	386	if (i < 2)
	387	printf(" ETHERC ch%d = %s\n", i, mac_string);
	388	else
	389	printf("GETHERC ch%d = %s\n", i-2, mac_string);
	390	}
	391	free(buf);
	392	return 0;
	393	}
	394
	395	/* new setting */
	396	memset(mac_string, 0xff, sizeof(mac_string));
	397	sprintf(mac_string, "%s\t%s\t%s\t%s",
	398	argv[1], argv[2], argv[3], argv[4]);
	399
	400	/* write MAC data to SPI rom */
	401	spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
	402	if (!spi) {
	403	printf("%s: spi_flash probe error.\n", __func__);
	404	return 1;
	405	}
	406
	407	ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
	408	SH7757LCR_SPI_SECTOR_SIZE);
	409	if (ret) {
	410	printf("%s: spi_flash erase error.\n", __func__);
	411	return 1;
	412	}
	413
	414	ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
	415	sizeof(mac_string), mac_string);
	416	if (ret) {
	417	printf("%s: spi_flash write error.\n", __func__);
	418	spi_flash_free(spi);
	419	return 1;
	420	}
	421	spi_flash_free(spi);
	422
	423	puts("The writing of the MAC address to SPI ROM was completed.\n");
	424
	425	return 0;
	426	}
	427
	428	U_BOOT_CMD(
	429	write_mac, 5, 1, do_write_mac,
	430	"write MAC address for ETHERC/GETHERC",
	431	"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
432	);
88369d33	433	#endif