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7faddaec NI |
1 | /* |
2 | * Copyright (C) 2008 Renesas Solutions Corp. | |
3 | * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
4 | * Copyright (C) 2007 Kenati Technologies, Inc. | |
5 | * | |
6 | * board/sh7763rdp/lowlevel_init.S | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <config.h> | |
25 | #include <version.h> | |
26 | ||
27 | #include <asm/processor.h> | |
28 | ||
29 | .global lowlevel_init | |
30 | ||
31 | .text | |
32 | .align 2 | |
33 | ||
34 | lowlevel_init: | |
35 | ||
e4430779 JCPV |
36 | mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ |
37 | mov.l WDTCSR_D, r0 | |
38 | mov.l r0, @r1 | |
7faddaec | 39 | |
e4430779 JCPV |
40 | mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ |
41 | mov.l WDTST_D, r0 | |
42 | mov.l r0, @r1 | |
7faddaec | 43 | |
e4430779 JCPV |
44 | mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ |
45 | mov.l WDTBST_D, r0 | |
46 | mov.l r0, @r1 | |
7faddaec NI |
47 | |
48 | mov.l CCR_A, r1 /* Address of Cache Control Register */ | |
49 | mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ | |
50 | mov.l r0, @r1 | |
51 | ||
52 | mov.l MMUCR_A, r1 /* Address of MMU Control Register */ | |
53 | mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */ | |
54 | mov.l r0, @r1 | |
55 | ||
56 | mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */ | |
57 | mov.l MSTPCR0_D, r0 | |
58 | mov.l r0, @r1 | |
59 | ||
60 | mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */ | |
61 | mov.l MSTPCR1_D, r0 | |
62 | mov.l r0, @r1 | |
63 | ||
e4430779 JCPV |
64 | mov.l RAMCR_A, r1 |
65 | mov.l RAMCR_D, r0 | |
7faddaec NI |
66 | mov.l r0, @r1 |
67 | ||
e4430779 JCPV |
68 | mov.l MMSELR_A, r1 |
69 | mov.l MMSELR_D, r0 | |
7faddaec NI |
70 | synco |
71 | mov.l r0, @r1 | |
72 | ||
e4430779 JCPV |
73 | mov.l @r1, r2 /* execute two reads after setting MMSELR*/ |
74 | mov.l @r1, r2 | |
7faddaec NI |
75 | synco |
76 | ||
77 | /* issue memory read */ | |
e4430779 JCPV |
78 | mov.l DDRSD_START_A, r1 /* memory address to read*/ |
79 | mov.l @r1, r0 | |
7faddaec NI |
80 | synco |
81 | ||
e4430779 JCPV |
82 | mov.l MIM8_A, r1 |
83 | mov.l MIM8_D, r0 | |
84 | mov.l r0, @r1 | |
7faddaec | 85 | |
e4430779 JCPV |
86 | mov.l MIMC_A, r1 |
87 | mov.l MIMC_D1, r0 | |
88 | mov.l r0, @r1 | |
7faddaec | 89 | |
e4430779 JCPV |
90 | mov.l STRC_A, r1 |
91 | mov.l STRC_D, r0 | |
92 | mov.l r0, @r1 | |
7faddaec | 93 | |
e4430779 JCPV |
94 | mov.l SDR4_A, r1 |
95 | mov.l SDR4_D, r0 | |
96 | mov.l r0, @r1 | |
7faddaec | 97 | |
e4430779 JCPV |
98 | mov.l MIMC_A, r1 |
99 | mov.l MIMC_D2, r0 | |
100 | mov.l r0, @r1 | |
7faddaec NI |
101 | |
102 | nop | |
103 | nop | |
104 | nop | |
105 | ||
e4430779 JCPV |
106 | mov.l SCR4_A, r1 |
107 | mov.l SCR4_D3, r0 | |
108 | mov.l r0, @r1 | |
7faddaec | 109 | |
e4430779 JCPV |
110 | mov.l SCR4_A, r1 |
111 | mov.l SCR4_D2, r0 | |
112 | mov.l r0, @r1 | |
7faddaec | 113 | |
e4430779 JCPV |
114 | mov.l SDMR02000_A, r1 |
115 | mov.l SDMR02000_D, r0 | |
116 | mov.l r0, @r1 | |
7faddaec | 117 | |
e4430779 JCPV |
118 | mov.l SDMR00B08_A, r1 |
119 | mov.l SDMR00B08_D, r0 | |
120 | mov.l r0, @r1 | |
7faddaec | 121 | |
e4430779 JCPV |
122 | mov.l SCR4_A, r1 |
123 | mov.l SCR4_D2, r0 | |
124 | mov.l r0, @r1 | |
7faddaec | 125 | |
e4430779 JCPV |
126 | mov.l SCR4_A, r1 |
127 | mov.l SCR4_D4, r0 | |
128 | mov.l r0, @r1 | |
7faddaec NI |
129 | |
130 | nop | |
131 | nop | |
132 | nop | |
133 | nop | |
134 | ||
e4430779 JCPV |
135 | mov.l SCR4_A, r1 |
136 | mov.l SCR4_D4, r0 | |
137 | mov.l r0, @r1 | |
7faddaec NI |
138 | |
139 | nop | |
140 | nop | |
141 | nop | |
142 | nop | |
143 | ||
e4430779 JCPV |
144 | mov.l SDMR00308_A, r1 |
145 | mov.l SDMR00308_D, r0 | |
146 | mov.l r0, @r1 | |
7faddaec | 147 | |
e4430779 JCPV |
148 | mov.l MIMC_A, r1 |
149 | mov.l MIMC_D3, r0 | |
150 | mov.l r0, @r1 | |
7faddaec | 151 | |
e4430779 JCPV |
152 | mov.l SCR4_A, r1 |
153 | mov.l SCR4_D1, r0 | |
154 | mov.l DELAY60_D, r3 | |
7faddaec NI |
155 | |
156 | delay_loop_60: | |
e4430779 | 157 | mov.l r0, @r1 |
7faddaec NI |
158 | dt r3 |
159 | bf delay_loop_60 | |
160 | nop | |
161 | ||
e4430779 JCPV |
162 | mov.l CCR_A, r1 /* Address of Cache Control Register */ |
163 | mov.l CCR_CACHE_D_2, r0 | |
164 | mov.l r0, @r1 | |
7faddaec NI |
165 | |
166 | bsc_init: | |
167 | mov.l BCR_A, r1 | |
168 | mov.l BCR_D, r0 | |
169 | mov.l r0, @r1 | |
170 | ||
171 | mov.l CS0BCR_A, r1 | |
172 | mov.l CS0BCR_D, r0 | |
173 | mov.l r0, @r1 | |
174 | ||
e4430779 JCPV |
175 | mov.l CS1BCR_A, r1 |
176 | mov.l CS1BCR_D, r0 | |
177 | mov.l r0, @r1 | |
7faddaec NI |
178 | |
179 | mov.l CS2BCR_A, r1 | |
180 | mov.l CS2BCR_D, r0 | |
181 | mov.l r0, @r1 | |
182 | ||
183 | mov.l CS4BCR_A, r1 | |
184 | mov.l CS4BCR_D, r0 | |
185 | mov.l r0, @r1 | |
186 | ||
187 | mov.l CS5BCR_A, r1 | |
188 | mov.l CS5BCR_D, r0 | |
189 | mov.l r0, @r1 | |
190 | ||
191 | mov.l CS6BCR_A, r1 | |
192 | mov.l CS6BCR_D, r0 | |
193 | mov.l r0, @r1 | |
194 | ||
195 | mov.l CS0WCR_A, r1 | |
196 | mov.l CS0WCR_D, r0 | |
197 | mov.l r0, @r1 | |
198 | ||
199 | mov.l CS1WCR_A, r1 | |
200 | mov.l CS1WCR_D, r0 | |
201 | mov.l r0, @r1 | |
202 | ||
203 | mov.l CS2WCR_A, r1 | |
204 | mov.l CS2WCR_D, r0 | |
205 | mov.l r0, @r1 | |
206 | ||
207 | mov.l CS4WCR_A, r1 | |
208 | mov.l CS4WCR_D, r0 | |
209 | mov.l r0, @r1 | |
210 | ||
211 | mov.l CS5WCR_A, r1 | |
212 | mov.l CS5WCR_D, r0 | |
213 | mov.l r0, @r1 | |
214 | ||
215 | mov.l CS6WCR_A, r1 | |
216 | mov.l CS6WCR_D, r0 | |
217 | mov.l r0, @r1 | |
218 | ||
219 | mov.l CS5PCR_A, r1 | |
220 | mov.l CS5PCR_D, r0 | |
221 | mov.l r0, @r1 | |
222 | ||
223 | mov.l CS6PCR_A, r1 | |
224 | mov.l CS6PCR_D, r0 | |
225 | mov.l r0, @r1 | |
226 | ||
e4430779 | 227 | mov.l DELAY200_D, r3 |
7faddaec NI |
228 | |
229 | delay_loop_200: | |
230 | dt r3 | |
231 | bf delay_loop_200 | |
232 | nop | |
233 | ||
e4430779 JCPV |
234 | mov.l PSEL0_A, r1 |
235 | mov.l PSEL0_D, r0 | |
236 | mov.w r0, @r1 | |
7faddaec | 237 | |
e4430779 JCPV |
238 | mov.l PSEL1_A, r1 |
239 | mov.l PSEL1_D, r0 | |
240 | mov.w r0, @r1 | |
7faddaec | 241 | |
e4430779 JCPV |
242 | mov.l ICR0_A, r1 |
243 | mov.l ICR0_D, r0 | |
244 | mov.l r0, @r1 | |
7faddaec NI |
245 | |
246 | stc sr, r0 /* BL bit off(init=ON) */ | |
e4430779 | 247 | mov.l SR_MASK_D, r1 |
7faddaec NI |
248 | and r1, r0 |
249 | ldc r0, sr | |
250 | ||
251 | rts | |
252 | nop | |
253 | ||
254 | .align 2 | |
255 | ||
256 | DELAY60_D: .long 60 | |
257 | DELAY200_D: .long 17800 | |
258 | ||
259 | CCR_A: .long 0xFF00001C | |
260 | MMUCR_A: .long 0xFF000010 | |
261 | RAMCR_A: .long 0xFF000074 | |
262 | ||
263 | /* Low power mode control */ | |
264 | MSTPCR0_A: .long 0xFFC80030 | |
265 | MSTPCR1_A: .long 0xFFC80038 | |
266 | ||
267 | /* RWBT */ | |
268 | WDTST_A: .long 0xFFCC0000 | |
269 | WDTCSR_A: .long 0xFFCC0004 | |
270 | WDTBST_A: .long 0xFFCC0008 | |
271 | ||
272 | /* BSC */ | |
273 | MMSELR_A: .long 0xFE600020 | |
274 | BCR_A: .long 0xFF801000 | |
275 | CS0BCR_A: .long 0xFF802000 | |
276 | CS1BCR_A: .long 0xFF802010 | |
277 | CS2BCR_A: .long 0xFF802020 | |
278 | CS4BCR_A: .long 0xFF802040 | |
279 | CS5BCR_A: .long 0xFF802050 | |
280 | CS6BCR_A: .long 0xFF802060 | |
281 | CS0WCR_A: .long 0xFF802008 | |
282 | CS1WCR_A: .long 0xFF802018 | |
283 | CS2WCR_A: .long 0xFF802028 | |
284 | CS4WCR_A: .long 0xFF802048 | |
285 | CS5WCR_A: .long 0xFF802058 | |
286 | CS6WCR_A: .long 0xFF802068 | |
287 | CS5PCR_A: .long 0xFF802070 | |
288 | CS6PCR_A: .long 0xFF802080 | |
289 | DDRSD_START_A: .long 0xAC000000 | |
290 | ||
291 | /* INTC */ | |
292 | ICR0_A: .long 0xFFD00000 | |
293 | ||
294 | /* DDR I/F */ | |
295 | MIM8_A: .long 0xFE800008 | |
296 | MIMC_A: .long 0xFE80000C | |
297 | SCR4_A: .long 0xFE800014 | |
298 | STRC_A: .long 0xFE80001C | |
299 | SDR4_A: .long 0xFE800034 | |
300 | SDMR00308_A: .long 0xFE900308 | |
301 | SDMR00B08_A: .long 0xFE900B08 | |
302 | SDMR02000_A: .long 0xFE902000 | |
303 | ||
304 | /* GPIO */ | |
305 | PSEL0_A: .long 0xFFEF0070 | |
306 | PSEL1_A: .long 0xFFEF0072 | |
307 | ||
308 | CCR_CACHE_ICI_D:.long 0x00000800 | |
309 | CCR_CACHE_D_2: .long 0x00000103 | |
310 | MMU_CONTROL_TI_D:.long 0x00000004 | |
311 | RAMCR_D: .long 0x00000200 | |
312 | MSTPCR0_D: .long 0x00000000 | |
313 | MSTPCR1_D: .long 0x00000000 | |
314 | ||
315 | MMSELR_D: .long 0xa5a50000 | |
316 | BCR_D: .long 0x00000000 | |
317 | CS0BCR_D: .long 0x77777770 | |
318 | CS1BCR_D: .long 0x77777670 | |
319 | CS2BCR_D: .long 0x77777670 | |
320 | CS4BCR_D: .long 0x77777670 | |
321 | CS5BCR_D: .long 0x77777670 | |
322 | CS6BCR_D: .long 0x77777670 | |
323 | CS0WCR_D: .long 0x7777770F | |
e4430779 | 324 | CS1WCR_D: .long 0x22000002 |
7faddaec NI |
325 | CS2WCR_D: .long 0x7777770F |
326 | CS4WCR_D: .long 0x7777770F | |
327 | CS5WCR_D: .long 0x7777770F | |
328 | CS6WCR_D: .long 0x7777770F | |
329 | CS5PCR_D: .long 0x77000000 | |
330 | CS6PCR_D: .long 0x77000000 | |
331 | ICR0_D: .long 0x00E00000 | |
332 | MIM8_D: .long 0x00000000 | |
333 | MIMC_D1: .long 0x01d10008 | |
334 | MIMC_D2: .long 0x01d10009 | |
335 | MIMC_D3: .long 0x01d10209 | |
336 | SCR4_D1: .long 0x00000001 | |
337 | SCR4_D2: .long 0x00000002 | |
338 | SCR4_D3: .long 0x00000003 | |
339 | SCR4_D4: .long 0x00000004 | |
340 | STRC_D: .long 0x000f3980 | |
341 | SDR4_D: .long 0x00000300 | |
342 | SDMR00308_D: .long 0x00000000 | |
343 | SDMR00B08_D: .long 0x00000000 | |
344 | SDMR02000_D: .long 0x00000000 | |
345 | PSEL0_D: .long 0x00000001 | |
346 | PSEL1_D: .long 0x00000244 | |
347 | SR_MASK_D: .long 0xEFFFFF0F | |
348 | WDTST_D: .long 0x5A000FFF | |
349 | WDTCSR_D: .long 0xA5000000 | |
350 | WDTBST_D: .long 0x55000000 |