[people/ms/u-boot.git] / board / renesas / silk / silk.c

/*
 * board/renesas/silk/silk.c
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#include <common.h>
#include <malloc.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <div64.h>
#include "qos.h"

DECLARE_GLOBAL_DATA_PTR;

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	/* QoS */
	qos_init();
}

#define TMU0_MSTP125	(1 << 25)
#define SCIF2_MSTP719	(1 << 19)
#define ETHER_MSTP813	(1 << 13)
#define IIC1_MSTP323	(1 << 23)
#define MMC0_MSTP315	(1 << 15)
#define SDHI1_MSTP312	(1 << 12)

#define SD1CKCR		0xE6150078
#define SD1_97500KHZ	0x7

int board_early_init_f(void)
{
	/* TMU */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);

	/* SCIF2 */
	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);

	/* ETHER */
	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);

	/* IIC1 / sh-i2c ch1 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);

#ifdef CONFIG_SH_MMCIF
	/* MMC */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
#endif

#ifdef CONFIG_SH_SDHI
	/* SDHI1 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312);

	/*
	 * Set SD1 to the 97.5MHz
	 */
	writel(SD1_97500KHZ, SD1CKCR);
#endif
	return 0;
}

/* LSI pin pull-up control */
#define PUPR3		0xe606010C
#define PUPR3_ETH	0x006FF800
#define PUPR1		0xe6060104
#define PUPR1_DREQ0_N	(1 << 20)
int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	/* Init PFC controller */
	r8a7794_pinmux_init();

	/* Ether Enable */
	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
	gpio_request(GPIO_FN_ETH_RXD0, NULL);
	gpio_request(GPIO_FN_ETH_RXD1, NULL);
	gpio_request(GPIO_FN_ETH_LINK, NULL);
	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
	gpio_request(GPIO_FN_ETH_MDIO, NULL);
	gpio_request(GPIO_FN_ETH_TXD1, NULL);
	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
	gpio_request(GPIO_FN_ETH_TXD0, NULL);
	gpio_request(GPIO_FN_ETH_MDC, NULL);
	gpio_request(GPIO_FN_IRQ8, NULL);

	/* PHY reset */
	mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH);
	gpio_request(GPIO_GP_1_24, NULL);
	mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N);

	gpio_direction_output(GPIO_GP_1_24, 0);
	mdelay(20);
	gpio_set_value(GPIO_GP_1_24, 1);
	udelay(1);

	return 0;
}

#define CXR24 0xEE7003C0 /* MAC address high register */
#define CXR25 0xEE7003C8 /* MAC address low register */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SH_ETHER
	int ret = -ENODEV;
	u32 val;
	unsigned char enetaddr[6];

	ret = sh_eth_initialize(bis);
	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
		return ret;

	/* Set Mac address */
	val = enetaddr[0] << 24 | enetaddr[1] << 16 |
		enetaddr[2] << 8 | enetaddr[3];
	writel(val, CXR24);

	val = enetaddr[4] << 8 | enetaddr[5];
	writel(val, CXR25);

	return ret;
#else
	return 0;
#endif
}

int board_mmc_init(bd_t *bis)
{
	int ret = -ENODEV;

#ifdef CONFIG_SH_MMCIF
	/* MMC0 */
	gpio_request(GPIO_GP_4_31, NULL);
	gpio_direction_output(GPIO_GP_4_31, 1);

	ret = mmcif_mmc_init();
#endif

#ifdef CONFIG_SH_SDHI
	gpio_request(GPIO_FN_SD1_DATA0, NULL);
	gpio_request(GPIO_FN_SD1_DATA1, NULL);
	gpio_request(GPIO_FN_SD1_DATA2, NULL);
	gpio_request(GPIO_FN_SD1_DATA3, NULL);
	gpio_request(GPIO_FN_SD1_CLK, NULL);
	gpio_request(GPIO_FN_SD1_CMD, NULL);
	gpio_request(GPIO_FN_SD1_CD, NULL);

	/* SDHI 1 */
	gpio_request(GPIO_GP_4_26, NULL);
	gpio_request(GPIO_GP_4_29, NULL);
	gpio_direction_output(GPIO_GP_4_26, 1);
	gpio_direction_output(GPIO_GP_4_29, 1);

	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
#endif
	return ret;
}

int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	return 0;
}

const struct rmobile_sysinfo sysinfo = {
	CONFIG_ARCH_RMOBILE_BOARD_STRING
};

void reset_cpu(ulong addr)
{
	u8 val;

	i2c_set_bus_num(1); /* PowerIC connected to ch1 */
	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
	val |= 0x02;
	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
}

static const struct sh_serial_platdata serial_platdata = {
	.base = SCIF2_BASE,
	.type = PORT_SCIF,
	.clk = 14745600,
	.clk_mode = EXT_CLK,
};

U_BOOT_DEVICE(silk_serials) = {
	.name = "serial_sh",
	.platdata = &serial_platdata,
};
Commit	Line	Data
3b7f0e10 VB	1	/*
	2	* board/renesas/silk/silk.c
	3	*
	4	* Copyright (C) 2015 Renesas Electronics Corporation
	5	* Copyright (C) 2015 Cogent Embedded, Inc.
	6	*
	7	* SPDX-License-Identifier: GPL-2.0
	8	*/
	9
	10	#include <common.h>
	11	#include <malloc.h>
3cfab108 NI	12	#include <dm.h>
3cfab108 NI	13	#include <dm/platform_data/serial_sh.h>
3b7f0e10 VB	14	#include <asm/processor.h>
	15	#include <asm/mach-types.h>
	16	#include <asm/io.h>
	17	#include <asm/errno.h>
	18	#include <asm/arch/sys_proto.h>
	19	#include <asm/gpio.h>
	20	#include <asm/arch/rmobile.h>
	21	#include <asm/arch/rcar-mstp.h>
	22	#include <asm/arch/mmc.h>
275ec28e	23	#include <asm/arch/sh_sdhi.h>
3b7f0e10 VB	24	#include <netdev.h>
	25	#include <miiphy.h>
	26	#include <i2c.h>
	27	#include <div64.h>
	28	#include "qos.h"
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	#define CLK2MHZ(clk) (clk / 1000 / 1000)
	33	void s_init(void)
	34	{
	35	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	36	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	37
	38	/* Watchdog init */
	39	writel(0xA5A5A500, &rwdt->rwtcsra);
	40	writel(0xA5A5A500, &swdt->swtcsra);
	41
	42	/* QoS */
	43	qos_init();
3b7f0e10 VB	44	}
	45
	46	#define TMU0_MSTP125 (1 << 25)
	47	#define SCIF2_MSTP719 (1 << 19)
	48	#define ETHER_MSTP813 (1 << 13)
	49	#define IIC1_MSTP323 (1 << 23)
	50	#define MMC0_MSTP315 (1 << 15)
275ec28e VB	51	#define SDHI1_MSTP312 (1 << 12)
	52
	53	#define SD1CKCR 0xE6150078
	54	#define SD1_97500KHZ 0x7
3b7f0e10 VB	55
	56	int board_early_init_f(void)
	57	{
	58	/* TMU */
	59	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	60
	61	/* SCIF2 */
	62	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
	63
	64	/* ETHER */
	65	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
	66
	67	/* IIC1 / sh-i2c ch1 */
	68	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
	69
	70	#ifdef CONFIG_SH_MMCIF
	71	/* MMC */
	72	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
	73	#endif
275ec28e VB	74
	75	#ifdef CONFIG_SH_SDHI
	76	/* SDHI1 */
	77	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312);
	78
	79	/*
	80	* Set SD1 to the 97.5MHz
	81	*/
	82	writel(SD1_97500KHZ, SD1CKCR);
	83	#endif
3b7f0e10 VB	84	return 0;
	85	}
	86
add4ec4d VB	87	/* LSI pin pull-up control */
	88	#define PUPR3 0xe606010C
	89	#define PUPR3_ETH 0x006FF800
	90	#define PUPR1 0xe6060104
	91	#define PUPR1_DREQ0_N (1 << 20)
3b7f0e10 VB	92	int board_init(void)
	93	{
	94	/* adress of boot parameters */
	95	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	96
	97	/* Init PFC controller */
	98	r8a7794_pinmux_init();
	99
	100	/* Ether Enable */
	101	gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
	102	gpio_request(GPIO_FN_ETH_RX_ER, NULL);
	103	gpio_request(GPIO_FN_ETH_RXD0, NULL);
	104	gpio_request(GPIO_FN_ETH_RXD1, NULL);
	105	gpio_request(GPIO_FN_ETH_LINK, NULL);
	106	gpio_request(GPIO_FN_ETH_REFCLK, NULL);
	107	gpio_request(GPIO_FN_ETH_MDIO, NULL);
	108	gpio_request(GPIO_FN_ETH_TXD1, NULL);
	109	gpio_request(GPIO_FN_ETH_TX_EN, NULL);
	110	gpio_request(GPIO_FN_ETH_MAGIC, NULL);
	111	gpio_request(GPIO_FN_ETH_TXD0, NULL);
	112	gpio_request(GPIO_FN_ETH_MDC, NULL);
	113	gpio_request(GPIO_FN_IRQ8, NULL);
	114
	115	/* PHY reset */
add4ec4d	116	mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH);
3b7f0e10	117	gpio_request(GPIO_GP_1_24, NULL);
add4ec4d VB	118	mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N);
add4ec4d VB	119
3b7f0e10 VB	120	gpio_direction_output(GPIO_GP_1_24, 0);
	121	mdelay(20);
	122	gpio_set_value(GPIO_GP_1_24, 1);
	123	udelay(1);
	124
	125	return 0;
	126	}
	127
	128	#define CXR24 0xEE7003C0 /* MAC address high register */
	129	#define CXR25 0xEE7003C8 /* MAC address low register */
	130	int board_eth_init(bd_t *bis)
	131	{
	132	#ifdef CONFIG_SH_ETHER
	133	int ret = -ENODEV;
	134	u32 val;
	135	unsigned char enetaddr[6];
	136
	137	ret = sh_eth_initialize(bis);
	138	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
	139	return ret;
	140
	141	/* Set Mac address */
	142	val = enetaddr[0] << 24 \| enetaddr[1] << 16 \|
	143	enetaddr[2] << 8 \| enetaddr[3];
	144	writel(val, CXR24);
	145
	146	val = enetaddr[4] << 8 \| enetaddr[5];
	147	writel(val, CXR25);
	148
	149	return ret;
	150	#else
	151	return 0;
	152	#endif
	153	}
	154
	155	int board_mmc_init(bd_t *bis)
	156	{
275ec28e	157	int ret = -ENODEV;
3b7f0e10 VB	158
	159	#ifdef CONFIG_SH_MMCIF
	160	/* MMC0 */
	161	gpio_request(GPIO_GP_4_31, NULL);
313ff58e	162	gpio_direction_output(GPIO_GP_4_31, 1);
3b7f0e10 VB	163
	164	ret = mmcif_mmc_init();
	165	#endif
275ec28e VB	166
	167	#ifdef CONFIG_SH_SDHI
	168	gpio_request(GPIO_FN_SD1_DATA0, NULL);
	169	gpio_request(GPIO_FN_SD1_DATA1, NULL);
	170	gpio_request(GPIO_FN_SD1_DATA2, NULL);
	171	gpio_request(GPIO_FN_SD1_DATA3, NULL);
	172	gpio_request(GPIO_FN_SD1_CLK, NULL);
	173	gpio_request(GPIO_FN_SD1_CMD, NULL);
	174	gpio_request(GPIO_FN_SD1_CD, NULL);
	175
	176	/* SDHI 1 */
	177	gpio_request(GPIO_GP_4_26, NULL);
	178	gpio_request(GPIO_GP_4_29, NULL);
	179	gpio_direction_output(GPIO_GP_4_26, 1);
	180	gpio_direction_output(GPIO_GP_4_29, 1);
	181
	182	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
	183	#endif
3b7f0e10 VB	184	return ret;
	185	}
	186
	187	int dram_init(void)
	188	{
	189	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	190
	191	return 0;
	192	}
	193
	194	const struct rmobile_sysinfo sysinfo = {
1cc95f6e	195	CONFIG_ARCH_RMOBILE_BOARD_STRING
3b7f0e10 VB	196	};
	197
	198	void reset_cpu(ulong addr)
	199	{
	200	u8 val;
	201
	202	i2c_set_bus_num(1); /* PowerIC connected to ch1 */
	203	i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
	204	val \|= 0x02;
	205	i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
	206	}
3cfab108 NI	207
	208	static const struct sh_serial_platdata serial_platdata = {
	209	.base = SCIF2_BASE,
	210	.type = PORT_SCIF,
	211	.clk = 14745600,
	212	.clk_mode = EXT_CLK,
	213	};
	214
80069b7e	215	U_BOOT_DEVICE(silk_serials) = {
3cfab108 NI	216	.name = "serial_sh",
	217	.platdata = &serial_platdata,
	218	};