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Commit | Line | Data |
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21871138 VB |
1 | /* |
2 | * board/renesas/stout/stout.c | |
3 | * This file is Stout board support. | |
4 | * | |
5 | * Copyright (C) 2015 Renesas Electronics Europe GmbH | |
6 | * Copyright (C) 2015 Renesas Electronics Corporation | |
7 | * Copyright (C) 2015 Cogent Embedded, Inc. | |
8 | * | |
9 | * SPDX-License-Identifier: GPL-2.0 | |
10 | */ | |
11 | ||
12 | #include <common.h> | |
13 | #include <malloc.h> | |
14 | #include <netdev.h> | |
15 | #include <dm.h> | |
16 | #include <dm/platform_data/serial_sh.h> | |
17 | #include <asm/processor.h> | |
18 | #include <asm/mach-types.h> | |
19 | #include <asm/io.h> | |
20 | #include <asm/errno.h> | |
21 | #include <asm/arch/sys_proto.h> | |
22 | #include <asm/gpio.h> | |
23 | #include <asm/arch/rmobile.h> | |
24 | #include <asm/arch/rcar-mstp.h> | |
25 | #include <asm/arch/mmc.h> | |
26 | #include <asm/arch/sh_sdhi.h> | |
27 | #include <miiphy.h> | |
28 | #include <i2c.h> | |
29 | #include <mmc.h> | |
30 | #include "qos.h" | |
31 | #include "cpld.h" | |
32 | ||
33 | DECLARE_GLOBAL_DATA_PTR; | |
34 | ||
35 | #define CLK2MHZ(clk) (clk / 1000 / 1000) | |
36 | void s_init(void) | |
37 | { | |
38 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; | |
39 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; | |
40 | ||
41 | /* Watchdog init */ | |
42 | writel(0xA5A5A500, &rwdt->rwtcsra); | |
43 | writel(0xA5A5A500, &swdt->swtcsra); | |
44 | ||
45 | /* CPU frequency setting. Set to 1.4GHz */ | |
46 | if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { | |
47 | u32 stat = 0; | |
48 | u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) | |
49 | << PLL0_STC_BIT; | |
50 | clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); | |
51 | ||
52 | do { | |
53 | stat = readl(PLLECR) & PLL0ST; | |
54 | } while (stat == 0x0); | |
55 | } | |
56 | ||
57 | /* QoS(Quality-of-Service) Init */ | |
58 | qos_init(); | |
59 | } | |
60 | ||
61 | #define TMU0_MSTP125 (1 << 25) | |
62 | #define SCIFA0_MSTP204 (1 << 4) | |
63 | #define SDHI0_MSTP314 (1 << 14) | |
64 | #define SDHI2_MSTP312 (1 << 12) | |
65 | #define ETHER_MSTP813 (1 << 13) | |
66 | ||
67 | #define MSTPSR3 0xE6150048 | |
68 | #define SMSTPCR3 0xE615013C | |
69 | ||
70 | #define SD2CKCR 0xE6150078 | |
71 | #define SD2_97500KHZ 0x7 | |
72 | ||
73 | int board_early_init_f(void) | |
74 | { | |
75 | /* TMU0 */ | |
76 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); | |
77 | /* SCIFA0 */ | |
78 | mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204); | |
79 | /* ETHER */ | |
80 | mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); | |
81 | /* SDHI0,2 */ | |
82 | mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); | |
83 | ||
84 | /* | |
85 | * SD0 clock is set to 97.5MHz by default. | |
86 | * Set SD2 to the 97.5MHz as well. | |
87 | */ | |
88 | writel(SD2_97500KHZ, SD2CKCR); | |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
93 | int board_init(void) | |
94 | { | |
95 | /* adress of boot parameters */ | |
96 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; | |
97 | ||
98 | /* Init PFC controller */ | |
99 | r8a7790_pinmux_init(); | |
100 | ||
101 | cpld_init(); | |
102 | ||
103 | #ifdef CONFIG_SH_ETHER | |
104 | /* ETHER Enable */ | |
105 | gpio_request(GPIO_FN_ETH_CRS_DV, NULL); | |
106 | gpio_request(GPIO_FN_ETH_RX_ER, NULL); | |
107 | gpio_request(GPIO_FN_ETH_RXD0, NULL); | |
108 | gpio_request(GPIO_FN_ETH_RXD1, NULL); | |
109 | gpio_request(GPIO_FN_ETH_LINK, NULL); | |
110 | gpio_request(GPIO_FN_ETH_REF_CLK, NULL); | |
111 | gpio_request(GPIO_FN_ETH_MDIO, NULL); | |
112 | gpio_request(GPIO_FN_ETH_TXD1, NULL); | |
113 | gpio_request(GPIO_FN_ETH_TX_EN, NULL); | |
114 | gpio_request(GPIO_FN_ETH_MAGIC, NULL); | |
115 | gpio_request(GPIO_FN_ETH_TXD0, NULL); | |
116 | gpio_request(GPIO_FN_ETH_MDC, NULL); | |
117 | gpio_request(GPIO_FN_IRQ1, NULL); | |
118 | ||
119 | gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */ | |
120 | gpio_direction_output(GPIO_GP_3_31, 0); | |
121 | mdelay(20); | |
122 | gpio_set_value(GPIO_GP_3_31, 1); | |
123 | udelay(1); | |
124 | #endif | |
125 | ||
126 | return 0; | |
127 | } | |
128 | ||
129 | #define CXR24 0xEE7003C0 /* MAC address high register */ | |
130 | #define CXR25 0xEE7003C8 /* MAC address low register */ | |
131 | int board_eth_init(bd_t *bis) | |
132 | { | |
133 | int ret = -ENODEV; | |
134 | ||
135 | #ifdef CONFIG_SH_ETHER | |
136 | u32 val; | |
137 | unsigned char enetaddr[6]; | |
138 | ||
139 | ret = sh_eth_initialize(bis); | |
140 | if (!eth_getenv_enetaddr("ethaddr", enetaddr)) | |
141 | return ret; | |
142 | ||
143 | /* Set Mac address */ | |
144 | val = enetaddr[0] << 24 | enetaddr[1] << 16 | | |
145 | enetaddr[2] << 8 | enetaddr[3]; | |
146 | writel(val, CXR24); | |
147 | ||
148 | val = enetaddr[4] << 8 | enetaddr[5]; | |
149 | writel(val, CXR25); | |
150 | #endif | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
155 | /* Stout has KSZ8041NL/RNL */ | |
156 | #define PHY_CONTROL1 0x1E | |
157 | #define PHY_LED_MODE 0xC0000 | |
158 | #define PHY_LED_MODE_ACK 0x4000 | |
159 | int board_phy_config(struct phy_device *phydev) | |
160 | { | |
161 | int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); | |
162 | ret &= ~PHY_LED_MODE; | |
163 | ret |= PHY_LED_MODE_ACK; | |
164 | ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
169 | int board_mmc_init(bd_t *bis) | |
170 | { | |
171 | int ret = -ENODEV; | |
172 | ||
173 | #ifdef CONFIG_SH_SDHI | |
174 | gpio_request(GPIO_FN_SD0_DAT0, NULL); | |
175 | gpio_request(GPIO_FN_SD0_DAT1, NULL); | |
176 | gpio_request(GPIO_FN_SD0_DAT2, NULL); | |
177 | gpio_request(GPIO_FN_SD0_DAT3, NULL); | |
178 | gpio_request(GPIO_FN_SD0_CLK, NULL); | |
179 | gpio_request(GPIO_FN_SD0_CMD, NULL); | |
180 | gpio_request(GPIO_FN_SD0_CD, NULL); | |
181 | gpio_request(GPIO_FN_SD2_DAT0, NULL); | |
182 | gpio_request(GPIO_FN_SD2_DAT1, NULL); | |
183 | gpio_request(GPIO_FN_SD2_DAT2, NULL); | |
184 | gpio_request(GPIO_FN_SD2_DAT3, NULL); | |
185 | gpio_request(GPIO_FN_SD2_CLK, NULL); | |
186 | gpio_request(GPIO_FN_SD2_CMD, NULL); | |
187 | gpio_request(GPIO_FN_SD2_CD, NULL); | |
188 | ||
189 | /* SDHI0 - needs CPLD mux setup */ | |
190 | gpio_request(GPIO_GP_3_30, NULL); | |
191 | gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */ | |
192 | gpio_request(GPIO_GP_5_24, NULL); | |
193 | gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ | |
194 | ||
195 | ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, | |
196 | SH_SDHI_QUIRK_16BIT_BUF); | |
197 | if (ret) | |
198 | return ret; | |
199 | ||
200 | /* SDHI2 - needs CPLD mux setup */ | |
201 | gpio_request(GPIO_GP_3_29, NULL); | |
202 | gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */ | |
203 | gpio_request(GPIO_GP_5_25, NULL); | |
204 | gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ | |
205 | ||
206 | ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); | |
207 | #endif | |
208 | return ret; | |
209 | } | |
210 | ||
211 | ||
212 | int dram_init(void) | |
213 | { | |
214 | gd->ram_size = CONFIG_SYS_SDRAM_SIZE; | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | const struct rmobile_sysinfo sysinfo = { | |
1cc95f6e | 220 | CONFIG_ARCH_RMOBILE_BOARD_STRING |
21871138 VB |
221 | }; |
222 | ||
223 | static const struct sh_serial_platdata serial_platdata = { | |
224 | .base = SCIFA0_BASE, | |
225 | .type = PORT_SCIFA, | |
226 | .clk = CONFIG_MP_CLK_FREQ, | |
227 | }; | |
228 | ||
229 | U_BOOT_DEVICE(stout_serials) = { | |
230 | .name = "serial_sh", | |
231 | .platdata = &serial_platdata, | |
232 | }; |