[people/ms/u-boot.git] / board / renesas / ulcb / ulcb.c

/*
 * board/renesas/ulcb/ulcb.c
 *     This file is ULCB board support.
 *
 * Copyright (C) 2017 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>

DECLARE_GLOBAL_DATA_PTR;

#define CPGWPCR	0xE6150904
#define CPGWPR  0xE615090C

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	writel(0xA5A50000, CPGWPCR);
	writel(0xFFFFFFFF, CPGWPR);
}

#define GSX_MSTP112		BIT(12)	/* 3DG */
#define TMU0_MSTP125		BIT(25)	/* secure */
#define TMU1_MSTP124		BIT(24)	/* non-secure */
#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
#define ETHERAVB_MSTP812	BIT(12)
#define DVFS_MSTP926		BIT(26)
#define SD0_MSTP314		BIT(14)
#define SD1_MSTP313		BIT(13)
#define SD2_MSTP312		BIT(12)	/* either MMC0 */

#define SD0CKCR			0xE6150074
#define SD1CKCR			0xE6150078
#define SD2CKCR			0xE6150268
#define SD3CKCR			0xE615026C

int board_early_init_f(void)
{
	/* TMU0,1 */		/* which use ? */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
	/* SCIF2 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
	/* EHTERAVB */
	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
	/* eMMC */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
	/* SDHI0 */
	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);

	writel(0, SD0CKCR);
	writel(0, SD1CKCR);
	writel(0, SD2CKCR);
	writel(0, SD3CKCR);

#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
	/* DVFS for reset */
	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
#endif
	return 0;
}

/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define	SYSC_PWRSR2	0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define	SYSC_PWRONCR2	0xE618010C

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;

	/* Init PFC controller */
#if defined(CONFIG_R8A7795)
	r8a7795_pinmux_init();
#elif defined(CONFIG_R8A7796)
	r8a7796_pinmux_init();
#endif

	/* USB1 pull-up */
	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);

#ifdef CONFIG_RAVB
	/* EtherAVB Enable */
	/* GPSR2 */
	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
	gpio_request(GPIO_GFN_AVB_LINK, NULL);
	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
	gpio_request(GPIO_GFN_AVB_MDC, NULL);

	/* IPSR0 */
	gpio_request(GPIO_IFN_AVB_MDC, NULL);
	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
	gpio_request(GPIO_IFN_AVB_LINK, NULL);
	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
	/* IPSR1 */
	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
	/* IPSR2 */
	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
	/* IPSR3 */
	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);

	/* AVB_PHY_RST */
	gpio_request(GPIO_GP_2_10, NULL);
	gpio_direction_output(GPIO_GP_2_10, 0);
	mdelay(20);
	gpio_set_value(GPIO_GP_2_10, 1);
	udelay(1);
#endif

	return 0;
}

#ifdef CONFIG_SH_SDHI
int board_mmc_init(bd_t *bis)
{
	/* SDHI0 */
	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	gpio_request(GPIO_GFN_SD0_CLK, NULL);
	gpio_request(GPIO_GFN_SD0_CMD, NULL);
	gpio_request(GPIO_GFN_SD0_CD, NULL);
	gpio_request(GPIO_GFN_SD0_WP, NULL);

	gpio_request(GPIO_GP_5_2, NULL);
	gpio_request(GPIO_GP_5_1, NULL);
	gpio_direction_output(GPIO_GP_5_2, 1);	/* power on */
	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */

	/* SDHI1/SDHI2 eMMC */
	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	gpio_request(GPIO_GFN_SD2_CLK, NULL);
#if defined(CONFIG_R8A7795)
	gpio_request(GPIO_GFN_SD2_CMD, NULL);
#elif defined(CONFIG_R8A7796)
	gpio_request(GPIO_FN_SD2_CMD, NULL);
#else
#error Only R8A7795 and R87796 is supported
#endif
	gpio_request(GPIO_GP_5_3, NULL);
	gpio_request(GPIO_GP_5_9, NULL);
	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */
	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */

	return 0;
}
#endif

int dram_init(void)
{
	gd->ram_size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
	gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
	gd->ram_size += PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
	gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#if (CONFIG_NR_DRAM_BANKS >= 2)
	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 3)
	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
#endif
#if (CONFIG_NR_DRAM_BANKS >= 4)
	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
#endif
	return 0;
}

const struct rmobile_sysinfo sysinfo = {
	CONFIG_RCAR_BOARD_STRING
};
Commit	Line	Data
bd39050c MV	1	/*
	2	* board/renesas/ulcb/ulcb.c
	3	* This file is ULCB board support.
	4	*
	5	* Copyright (C) 2017 Renesas Electronics Corporation
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#include <common.h>
	11	#include <malloc.h>
	12	#include <netdev.h>
	13	#include <dm.h>
	14	#include <dm/platform_data/serial_sh.h>
	15	#include <asm/processor.h>
	16	#include <asm/mach-types.h>
	17	#include <asm/io.h>
	18	#include <linux/errno.h>
	19	#include <asm/arch/sys_proto.h>
	20	#include <asm/gpio.h>
	21	#include <asm/arch/gpio.h>
	22	#include <asm/arch/rmobile.h>
	23	#include <asm/arch/rcar-mstp.h>
	24	#include <asm/arch/sh_sdhi.h>
	25	#include <i2c.h>
	26	#include <mmc.h>
	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	#define CPGWPCR 0xE6150904
	31	#define CPGWPR 0xE615090C
	32
	33	#define CLK2MHZ(clk) (clk / 1000 / 1000)
	34	void s_init(void)
	35	{
	36	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	37	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	38
	39	/* Watchdog init */
	40	writel(0xA5A5A500, &rwdt->rwtcsra);
	41	writel(0xA5A5A500, &swdt->swtcsra);
	42
	43	writel(0xA5A50000, CPGWPCR);
	44	writel(0xFFFFFFFF, CPGWPR);
	45	}
	46
	47	#define GSX_MSTP112 BIT(12) /* 3DG */
	48	#define TMU0_MSTP125 BIT(25) /* secure */
	49	#define TMU1_MSTP124 BIT(24) /* non-secure */
	50	#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
	51	#define ETHERAVB_MSTP812 BIT(12)
	52	#define DVFS_MSTP926 BIT(26)
	53	#define SD0_MSTP314 BIT(14)
	54	#define SD1_MSTP313 BIT(13)
	55	#define SD2_MSTP312 BIT(12) /* either MMC0 */
	56
	57	#define SD0CKCR 0xE6150074
	58	#define SD1CKCR 0xE6150078
	59	#define SD2CKCR 0xE6150268
	60	#define SD3CKCR 0xE615026C
	61
	62	int board_early_init_f(void)
	63	{
	64	/* TMU0,1 / / which use ? */
65	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 \| TMU1_MSTP124);
66	/* SCIF2 */
67	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
68	/* EHTERAVB */
69	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
70	/* eMMC */
71	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 \| SD2_MSTP312);
72	/* SDHI0 */
73	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
74
75	writel(0, SD0CKCR);
76	writel(0, SD1CKCR);
77	writel(0, SD2CKCR);
78	writel(0, SD3CKCR);
79
80	#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
81	/* DVFS for reset */
82	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
83	#endif
84	return 0;
85	}
86
87	/* SYSC */
88	/* R/- 32 Power status register 2(3DG) */
89	#define SYSC_PWRSR2 0xE6180100
90	/* -/W 32 Power resume control register 2 (3DG) */
91	#define SYSC_PWRONCR2 0xE618010C
92
93	int board_init(void)
94	{
95	/* adress of boot parameters */
96	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
97
98	/* Init PFC controller */
99	#if defined(CONFIG_R8A7795)
100	r8a7795_pinmux_init();
101	#elif defined(CONFIG_R8A7796)
102	r8a7796_pinmux_init();
103	#endif
104
105	/* USB1 pull-up */
106	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC \| PUEN_USB1_PWEN);
107
108	#ifdef CONFIG_RAVB
109	/* EtherAVB Enable */
110	/* GPSR2 */
111	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
112	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
113	gpio_request(GPIO_GFN_AVB_LINK, NULL);
114	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
115	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
116	gpio_request(GPIO_GFN_AVB_MDC, NULL);
117
118	/* IPSR0 */
119	gpio_request(GPIO_IFN_AVB_MDC, NULL);
120	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
121	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
122	gpio_request(GPIO_IFN_AVB_LINK, NULL);
123	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
124	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
125	/* IPSR1 */
126	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
127	/* IPSR2 */
128	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
129	/* IPSR3 */
130	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
131
132	/* AVB_PHY_RST */
133	gpio_request(GPIO_GP_2_10, NULL);
134	gpio_direction_output(GPIO_GP_2_10, 0);
135	mdelay(20);
136	gpio_set_value(GPIO_GP_2_10, 1);
137	udelay(1);
138	#endif
139
140	return 0;
141	}
142
bd39050c MV	143	#ifdef CONFIG_SH_SDHI
	144	int board_mmc_init(bd_t *bis)
	145	{
bd39050c MV	146	/* SDHI0 */
	147	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
	148	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
	149	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
	150	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
	151	gpio_request(GPIO_GFN_SD0_CLK, NULL);
	152	gpio_request(GPIO_GFN_SD0_CMD, NULL);
	153	gpio_request(GPIO_GFN_SD0_CD, NULL);
	154	gpio_request(GPIO_GFN_SD0_WP, NULL);
	155
	156	gpio_request(GPIO_GP_5_2, NULL);
	157	gpio_request(GPIO_GP_5_1, NULL);
	158	gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
	159	gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
	160
bd39050c MV	161	/* SDHI1/SDHI2 eMMC */
	162	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
	163	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
	164	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
	165	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
	166	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
	167	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
	168	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
	169	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
	170	gpio_request(GPIO_GFN_SD2_CLK, NULL);
	171	#if defined(CONFIG_R8A7795)
	172	gpio_request(GPIO_GFN_SD2_CMD, NULL);
	173	#elif defined(CONFIG_R8A7796)
	174	gpio_request(GPIO_FN_SD2_CMD, NULL);
	175	#else
	176	#error Only R8A7795 and R87796 is supported
	177	#endif
	178	gpio_request(GPIO_GP_5_3, NULL);
	179	gpio_request(GPIO_GP_5_9, NULL);
	180	gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
	181	gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
	182
6f380854	183	return 0;
bd39050c MV	184	}
	185	#endif
	186
	187	int dram_init(void)
	188	{
	189	gd->ram_size = PHYS_SDRAM_1_SIZE;
	190	#if (CONFIG_NR_DRAM_BANKS >= 2)
	191	gd->ram_size += PHYS_SDRAM_2_SIZE;
	192	#endif
	193	#if (CONFIG_NR_DRAM_BANKS >= 3)
	194	gd->ram_size += PHYS_SDRAM_3_SIZE;
	195	#endif
	196	#if (CONFIG_NR_DRAM_BANKS >= 4)
	197	gd->ram_size += PHYS_SDRAM_4_SIZE;
	198	#endif
	199
	200	return 0;
	201	}
	202
	203	int dram_init_banksize(void)
	204	{
	205	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	206	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	207	#if (CONFIG_NR_DRAM_BANKS >= 2)
	208	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	209	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
	210	#endif
	211	#if (CONFIG_NR_DRAM_BANKS >= 3)
	212	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
	213	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
	214	#endif
	215	#if (CONFIG_NR_DRAM_BANKS >= 4)
	216	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
	217	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
	218	#endif
	219	return 0;
	220	}
	221
	222	const struct rmobile_sysinfo sysinfo = {
	223	CONFIG_RCAR_BOARD_STRING
	224	};