[thirdparty/u-boot.git] / board / ronetix / pm9263 / pm9263.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 */

#include <common.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
#include <netdev.h>
#include <asm/mach-types.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void pm9263_nand_hw_init(void)
{
	unsigned long csa;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	/* Enable CS3 */
	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
	writel(csa, &matrix->csa[0]);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
		&smc->cs[3].setup);

	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);

	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);

	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		AT91_SMC_MODE_DBW_8 |
#endif
		AT91_SMC_MODE_TDF_CYCLE(2),
		&smc->cs[3].mode);

	/* Configure RDY/BSY */
	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);

	/* Enable NandFlash */
	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif

#ifdef CONFIG_MACB
static void pm9263_macb_hw_init(void)
{
	/*
	 * PB27 enables the 50MHz oscillator for Ethernet PHY
	 * 1 - enable
	 * 0 - disable
	 */
	at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
	at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */

	at91_periph_clk_enable(ATMEL_ID_EMAC);

	/*
	 * Disable pull-up on:
	 *	RXDV (PC25) => PHY normal mode (not Test mode)
	 *	ERX0 (PE25) => PHY ADDR0
	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */

	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);

	/* Re-enable pull-up */
	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);

	at91_macb_hw_init();
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col =		240,
	.vl_row =		320,
	.vl_clk =		4965000,
	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
					ATMEL_LCDC_INVFRAME_INVERTED,
	.vl_bpix =		3,
	.vl_tft =		1,
	.vl_hsync_len =		5,
	.vl_left_margin =	1,
	.vl_right_margin =	33,
	.vl_vsync_len =		1,
	.vl_upper_margin =	1,
	.vl_lower_margin =	0,
	.mmio =			ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
}

void lcd_disable(void)
{
	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
}

#ifdef CONFIG_LCD_IN_PSRAM

#define PSRAM_CRE_PIN	AT91_PIO_PORTB, 29
#define PSRAM_CTRL_REG	(PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)

/* Initialize the PSRAM memory */
static int pm9263_lcd_hw_psram_init(void)
{
	unsigned long csa;
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;

	/* Enable CS3  3.3v, no pull-ups */
	csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
		AT91_MATRIX_CSA_VDDIOMSEL_3_3V;

	writel(csa, &matrix->csa[1]);

	/* Configure SMC1 CS0 for PSRAM - 16-bit */
	writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[0].setup);

	writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
		AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
		&smc->cs[0].pulse);

	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
		&smc->cs[0].cycle);

	writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
		&smc->cs[0].mode);

	/* setup PB29 as output */
	at91_set_pio_output(PSRAM_CRE_PIN, 1);

	at91_set_pio_value(PSRAM_CRE_PIN, 0);	/* set PSRAM_CRE_PIN to '0' */

	/* PSRAM: write BCR */
	readw(PSRAM_CTRL_REG);
	readw(PSRAM_CTRL_REG);
	writew(1, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
	writew(0x9d4f, PSRAM_CTRL_REG);	/* write the BCR */

	/* write RCR of the PSRAM */
	readw(PSRAM_CTRL_REG);
	readw(PSRAM_CTRL_REG);
	writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
	/* set RCR; 0x10-async mode,0x90-page mode */
	writew(0x90, PSRAM_CTRL_REG);

	/*
	 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
	 * MT45W2M16B - CRE must be 0
	 * MT45W2M16A - CRE must be 1
	 */
	writew(0x1234, PHYS_PSRAM);
	writew(0x5678, PHYS_PSRAM + 2);

	/* test if the chip is MT45W2M16B */
	if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
		/* try with CRE=1 (MT45W2M16A) */
		at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */

		/* write RCR of the PSRAM */
		readw(PSRAM_CTRL_REG);
		readw(PSRAM_CTRL_REG);
		writew(0, PSRAM_CTRL_REG);	/* 0 - RCR,1 - BCR */
		/* set RCR;0x10-async mode,0x90-page mode */
		writew(0x90, PSRAM_CTRL_REG);


		writew(0x1234, PHYS_PSRAM);
		writew(0x5678, PHYS_PSRAM+2);
		if ((readw(PHYS_PSRAM) != 0x1234)
		  || (readw(PHYS_PSRAM + 2) != 0x5678))
			return 1;

	}

	/* Bus matrix */
	writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
	writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);

	return 0;
}
#endif

static void pm9263_lcd_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */

	at91_periph_clk_enable(ATMEL_ID_LCDC);

	/* Power Control */
	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);	/* power down */

#ifdef CONFIG_LCD_IN_PSRAM
	/* initialize te PSRAM */
	int stat = pm9263_lcd_hw_psram_init();

	gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
#else
	gd->fb_base = ATMEL_BASE_SRAM0;
#endif

}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

extern flash_info_t flash_info[];

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size, flash_size;
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	lcd_printf ("support@ronetix.at\n");
	lcd_printf ("%s CPU at %s MHz",
		CONFIG_SYS_AT91_CPU_NAME,
		strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += get_nand_dev_by_index(i)->size;

	flash_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
		flash_size += flash_info[i].size;

	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
			"4 MB PSRAM\n",
		dram_size >> 20,
		nand_size >> 20,
		flash_size >> 20);
}
#endif /* CONFIG_LCD_INFO */

#endif /* CONFIG_LCD */

int board_early_init_f(void)
{
	return 0;
}

int board_init(void)
{
	/* arch number of AT91SAM9263EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_PM9263;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_CMD_NAND
	pm9263_nand_hw_init();
#endif
#ifdef CONFIG_MACB
	pm9263_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
	at91_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
	pm9263_lcd_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	/* dram_init must store complete ramsize in gd->ram_size */
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
				PHYS_SDRAM_SIZE);
	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
}
#endif

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_MACB
	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
#endif
	return rc;
}

#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard (void)
{
	char *ss;

	printf ("Board : Ronetix PM9263\n");

	switch (gd->fb_base) {
	case PHYS_PSRAM:
		ss = "(PSRAM)";
		break;

	case ATMEL_BASE_SRAM0:
		ss = "(Internal SRAM)";
		break;

	default:
		ss = "";
		break;
	}
	printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );

	printf ("\n");
	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
f0a2c7b4 II	2	/*
f0a2c7b4 II	3	* (C) Copyright 2007-2008
c9e798d3	4	* Stelian Pop <stelian@popies.net>
f0a2c7b4 II	5	* Lead Tech Design <www.leadtechdesign.com>
	6	* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
	7	* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
f0a2c7b4 II	8	*/
	9
	10	#include <common.h>
1ace4022	11	#include <linux/sizes.h>
684a567a	12	#include <asm/io.h>
ac45bb16	13	#include <asm/gpio.h>
f0a2c7b4 II	14	#include <asm/arch/at91sam9_smc.h>
f0a2c7b4 II	15	#include <asm/arch/at91_common.h>
f0a2c7b4	16	#include <asm/arch/at91_rstc.h>
20d98c2c	17	#include <asm/arch/at91_matrix.h>
f0a2c7b4	18	#include <asm/arch/clk.h>
684a567a	19	#include <asm/arch/gpio.h>
f0a2c7b4 II	20	#include <lcd.h>
f0a2c7b4 II	21	#include <atmel_lcdc.h>
f0a2c7b4 II	22	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
	23	#include <net.h>
	24	#endif
	25	#include <netdev.h>
c62db35d	26	#include <asm/mach-types.h>
f0a2c7b4 II	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	/* ------------------------------------------------------------------------- */
	31	/*
	32	* Miscelaneous platform dependent initialisations
	33	*/
	34
	35	#ifdef CONFIG_CMD_NAND
	36	static void pm9263_nand_hw_init(void)
	37	{
	38	unsigned long csa;
684a567a AD	39	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC0;
684a567a AD	40	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
f0a2c7b4 II	41
f0a2c7b4 II	42	/* Enable CS3 */
20d98c2c AD	43	csa = readl(&matrix->csa[0]) \| AT91_MATRIX_CSA_EBI_CS3A;
20d98c2c AD	44	writel(csa, &matrix->csa[0]);
f0a2c7b4 II	45
f0a2c7b4 II	46	/* Configure SMC CS3 for NAND/SmartMedia */
20d98c2c AD	47	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(1) \|
	48	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(1),
	49	&smc->cs[3].setup);
	50
	51	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	52	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	53	&smc->cs[3].pulse);
	54
	55	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	56	&smc->cs[3].cycle);
	57
	58	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	59	AT91_SMC_MODE_EXNW_DISABLE \|
f0a2c7b4	60	#ifdef CONFIG_SYS_NAND_DBW_16
20d98c2c	61	AT91_SMC_MODE_DBW_16 \|
f0a2c7b4	62	#else /* CONFIG_SYS_NAND_DBW_8 */
20d98c2c	63	AT91_SMC_MODE_DBW_8 \|
f0a2c7b4	64	#endif
20d98c2c AD	65	AT91_SMC_MODE_TDF_CYCLE(2),
20d98c2c AD	66	&smc->cs[3].mode);
f0a2c7b4 II	67
f0a2c7b4 II	68	/* Configure RDY/BSY */
ac45bb16	69	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
f0a2c7b4 II	70
f0a2c7b4 II	71	/* Enable NandFlash */
ac45bb16	72	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
f0a2c7b4 II	73	}
	74	#endif
	75
	76	#ifdef CONFIG_MACB
	77	static void pm9263_macb_hw_init(void)
	78	{
	79	/*
	80	* PB27 enables the 50MHz oscillator for Ethernet PHY
	81	* 1 - enable
	82	* 0 - disable
	83	*/
20d98c2c AD	84	at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
20d98c2c AD	85	at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
f0a2c7b4	86
70341e2e	87	at91_periph_clk_enable(ATMEL_ID_EMAC);
f0a2c7b4 II	88
	89	/*
	90	* Disable pull-up on:
	91	* RXDV (PC25) => PHY normal mode (not Test mode)
	92	* ERX0 (PE25) => PHY ADDR0
	93	* ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
	94	*
	95	* PHY has internal pull-down
	96	*/
f0a2c7b4	97
20d98c2c AD	98	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
	99	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
	100	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
f0a2c7b4 II	101
f0a2c7b4 II	102	/* Re-enable pull-up */
20d98c2c AD	103	at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
	104	at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
	105	at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
f0a2c7b4 II	106
	107	at91_macb_hw_init();
	108	}
	109	#endif
	110
	111	#ifdef CONFIG_LCD
	112	vidinfo_t panel_info = {
1b34e880 JH	113	.vl_col = 240,
	114	.vl_row = 320,
	115	.vl_clk = 4965000,
	116	.vl_sync = ATMEL_LCDC_INVLINE_INVERTED \|
	117	ATMEL_LCDC_INVFRAME_INVERTED,
	118	.vl_bpix = 3,
	119	.vl_tft = 1,
	120	.vl_hsync_len = 5,
	121	.vl_left_margin = 1,
	122	.vl_right_margin = 33,
	123	.vl_vsync_len = 1,
	124	.vl_upper_margin = 1,
	125	.vl_lower_margin = 0,
	126	.mmio = ATMEL_BASE_LCDC,
f0a2c7b4 II	127	};
	128
	129	void lcd_enable(void)
	130	{
20d98c2c	131	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
f0a2c7b4 II	132	}
	133
	134	void lcd_disable(void)
	135	{
20d98c2c	136	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
f0a2c7b4 II	137	}
	138
	139	#ifdef CONFIG_LCD_IN_PSRAM
	140
20d98c2c	141	#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
f0a2c7b4 II	142	#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
	143
	144	/* Initialize the PSRAM memory */
	145	static int pm9263_lcd_hw_psram_init(void)
	146	{
7a11c7f9	147	unsigned long csa;
684a567a AD	148	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC1;
684a567a AD	149	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
7a11c7f9 JCPV	150
7a11c7f9 JCPV	151	/* Enable CS3 3.3v, no pull-ups */
20d98c2c AD	152	csa = readl(&matrix->csa[1]) \| AT91_MATRIX_CSA_DBPUC \|
	153	AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
	154
	155	writel(csa, &matrix->csa[1]);
7a11c7f9 JCPV	156
7a11c7f9 JCPV	157	/* Configure SMC1 CS0 for PSRAM - 16-bit */
20d98c2c AD	158	writel(AT91_SMC_SETUP_NWE(0) \| AT91_SMC_SETUP_NCS_WR(0) \|
	159	AT91_SMC_SETUP_NRD(0) \| AT91_SMC_SETUP_NCS_RD(0),
	160	&smc->cs[0].setup);
	161
	162	writel(AT91_SMC_PULSE_NWE(7) \| AT91_SMC_PULSE_NCS_WR(7) \|
	163	AT91_SMC_PULSE_NRD(2) \| AT91_SMC_PULSE_NCS_RD(7),
	164	&smc->cs[0].pulse);
	165
	166	writel(AT91_SMC_CYCLE_NWE(8) \| AT91_SMC_CYCLE_NRD(8),
	167	&smc->cs[0].cycle);
	168
	169	writel(AT91_SMC_MODE_DBW_16 \| AT91_SMC_MODE_PMEN \| AT91_SMC_MODE_PS_32,
	170	&smc->cs[0].mode);
f0a2c7b4 II	171
f0a2c7b4 II	172	/* setup PB29 as output */
20d98c2c	173	at91_set_pio_output(PSRAM_CRE_PIN, 1);
f0a2c7b4	174
20d98c2c	175	at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
f0a2c7b4 II	176
f0a2c7b4 II	177	/* PSRAM: write BCR */
0a59b711 AG	178	readw(PSRAM_CTRL_REG);
0a59b711 AG	179	readw(PSRAM_CTRL_REG);
f0a2c7b4 II	180	writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
	181	writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
	182
	183	/* write RCR of the PSRAM */
0a59b711 AG	184	readw(PSRAM_CTRL_REG);
0a59b711 AG	185	readw(PSRAM_CTRL_REG);
f0a2c7b4 II	186	writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
	187	/* set RCR; 0x10-async mode,0x90-page mode */
	188	writew(0x90, PSRAM_CTRL_REG);
	189
	190	/*
	191	* test to see if the PSRAM is MT45W2M16A or MT45W2M16B
	192	* MT45W2M16B - CRE must be 0
	193	* MT45W2M16A - CRE must be 1
	194	*/
	195	writew(0x1234, PHYS_PSRAM);
	196	writew(0x5678, PHYS_PSRAM + 2);
	197
	198	/* test if the chip is MT45W2M16B */
	199	if ((readw(PHYS_PSRAM) != 0x1234) \|\| (readw(PHYS_PSRAM+2) != 0x5678)) {
	200	/* try with CRE=1 (MT45W2M16A) */
20d98c2c	201	at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
f0a2c7b4 II	202
f0a2c7b4 II	203	/* write RCR of the PSRAM */
0a59b711 AG	204	readw(PSRAM_CTRL_REG);
0a59b711 AG	205	readw(PSRAM_CTRL_REG);
f0a2c7b4 II	206	writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
	207	/* set RCR;0x10-async mode,0x90-page mode */
	208	writew(0x90, PSRAM_CTRL_REG);
	209
	210
	211	writew(0x1234, PHYS_PSRAM);
	212	writew(0x5678, PHYS_PSRAM+2);
	213	if ((readw(PHYS_PSRAM) != 0x1234)
20d98c2c	214	\|\| (readw(PHYS_PSRAM + 2) != 0x5678))
f0a2c7b4 II	215	return 1;
	216
	217	}
	218
	219	/* Bus matrix */
20d98c2c AD	220	writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
20d98c2c AD	221	writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
f0a2c7b4 II	222
	223	return 0;
	224	}
	225	#endif
	226
	227	static void pm9263_lcd_hw_init(void)
	228	{
20d98c2c AD	229	at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
	230	at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
	231	at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
	232	at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
	233	at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
	234	at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
	235	at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
	236	at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
	237	at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
	238	at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
	239	at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
	240	at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
	241	at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
	242	at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
	243	at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
	244	at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
	245	at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
	246	at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
	247	at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
	248	at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
	249	at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
	250	at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
	251	at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
	252
70341e2e	253	at91_periph_clk_enable(ATMEL_ID_LCDC);
f0a2c7b4 II	254
f0a2c7b4 II	255	/* Power Control */
20d98c2c AD	256	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
20d98c2c AD	257	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
f0a2c7b4 II	258
	259	#ifdef CONFIG_LCD_IN_PSRAM
	260	/* initialize te PSRAM */
	261	int stat = pm9263_lcd_hw_psram_init();
	262
684a567a	263	gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
f0a2c7b4	264	#else
684a567a	265	gd->fb_base = ATMEL_BASE_SRAM0;
f0a2c7b4 II	266	#endif
	267
	268	}
	269
	270	#ifdef CONFIG_LCD_INFO
	271	#include <nand.h>
	272	#include <version.h>
	273
	274	extern flash_info_t flash_info[];
	275
	276	void lcd_show_board_info(void)
	277	{
0dfe3ffe	278	ulong dram_size, nand_size, flash_size;
f0a2c7b4 II	279	int i;
	280	char temp[32];
	281
	282	lcd_printf ("%s\n", U_BOOT_VERSION);
	283	lcd_printf ("(C) 2009 Ronetix GmbH\n");
	284	lcd_printf ("support@ronetix.at\n");
	285	lcd_printf ("%s CPU at %s MHz",
7c966a8b	286	CONFIG_SYS_AT91_CPU_NAME,
f0a2c7b4 II	287	strmhz(temp, get_cpu_clk_rate()));
	288
	289	dram_size = 0;
	290	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	291	dram_size += gd->bd->bi_dram[i].size;
	292
	293	nand_size = 0;
	294	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
2ecba112	295	nand_size += get_nand_dev_by_index(i)->size;
f0a2c7b4 II	296
	297	flash_size = 0;
	298	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
	299	flash_size += flash_info[i].size;
	300
f0a2c7b4	301	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
0dfe3ffe	302	"4 MB PSRAM\n",
f0a2c7b4 II	303	dram_size >> 20,
f0a2c7b4 II	304	nand_size >> 20,
0dfe3ffe	305	flash_size >> 20);
f0a2c7b4 II	306	}
	307	#endif /* CONFIG_LCD_INFO */
	308
	309	#endif /* CONFIG_LCD */
	310
52b26016	311	int board_early_init_f(void)
f0a2c7b4	312	{
52b26016 AD	313	return 0;
	314	}
	315
	316	int board_init(void)
	317	{
	318	/* arch number of AT91SAM9263EK-Board */
	319	gd->bd->bi_arch_number = MACH_TYPE_PM9263;
	320
f0a2c7b4 II	321	/* adress of boot parameters */
	322	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	323
f0a2c7b4 II	324	#ifdef CONFIG_CMD_NAND
	325	pm9263_nand_hw_init();
	326	#endif
f0a2c7b4 II	327	#ifdef CONFIG_MACB
	328	pm9263_macb_hw_init();
	329	#endif
	330	#ifdef CONFIG_USB_OHCI_NEW
	331	at91_uhp_hw_init();
	332	#endif
	333	#ifdef CONFIG_LCD
	334	pm9263_lcd_hw_init();
	335	#endif
	336	return 0;
	337	}
	338
	339	int dram_init(void)
9a2a05a4 AD	340	{
9a2a05a4 AD	341	/* dram_init must store complete ramsize in gd->ram_size */
a55d23cc	342	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
9a2a05a4 AD	343	PHYS_SDRAM_SIZE);
	344	return 0;
	345	}
	346
76b00aca	347	int dram_init_banksize(void)
f0a2c7b4 II	348	{
	349	gd->bd->bi_dram[0].start = PHYS_SDRAM;
	350	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
76b00aca SG	351
76b00aca SG	352	return 0;
f0a2c7b4 II	353	}
	354
	355	#ifdef CONFIG_RESET_PHY_R
	356	void reset_phy(void)
	357	{
f0a2c7b4 II	358	}
	359	#endif
	360
	361	int board_eth_init(bd_t *bis)
	362	{
	363	int rc = 0;
	364	#ifdef CONFIG_MACB
684a567a	365	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
f0a2c7b4 II	366	#endif
	367	return rc;
	368	}
	369
	370	#ifdef CONFIG_DISPLAY_BOARDINFO
	371	int checkboard (void)
	372	{
	373	char *ss;
f0a2c7b4 II	374
f0a2c7b4 II	375	printf ("Board : Ronetix PM9263\n");
f0a2c7b4 II	376
	377	switch (gd->fb_base) {
	378	case PHYS_PSRAM:
	379	ss = "(PSRAM)";
	380	break;
	381
684a567a	382	case ATMEL_BASE_SRAM0:
f0a2c7b4 II	383	ss = "(Internal SRAM)";
	384	break;
	385
	386	default:
	387	ss = "";
	388	break;
	389	}
	390	printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
	391
	392	printf ("\n");
	393	return 0;
	394	}
	395	#endif