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bf3a08be PM |
1 | /* |
2 | * Copyright (C) 2014 Samsung Electronics | |
3 | * Przemyslaw Marczak <p.marczak@samsung.com> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/arch/pinmux.h> | |
10 | #include <asm/arch/power.h> | |
11 | #include <asm/arch/clock.h> | |
12 | #include <asm/arch/gpio.h> | |
13 | #include <asm/gpio.h> | |
14 | #include <asm/arch/cpu.h> | |
15 | #include <power/pmic.h> | |
16 | #include <power/max77686_pmic.h> | |
17 | #include <errno.h> | |
18 | #include <usb.h> | |
19 | #include <usb/s3c_udc.h> | |
20 | #include <samsung/misc.h> | |
21 | #include "setup.h" | |
22 | ||
23 | DECLARE_GLOBAL_DATA_PTR; | |
24 | ||
25 | #ifdef CONFIG_BOARD_TYPES | |
26 | /* Odroid board types */ | |
27 | enum { | |
28 | ODROID_TYPE_U3, | |
29 | ODROID_TYPE_X2, | |
30 | ODROID_TYPES, | |
31 | }; | |
32 | ||
33 | void set_board_type(void) | |
34 | { | |
35 | /* Set GPA1 pin 1 to HI - enable XCL205 output */ | |
36 | writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON); | |
37 | writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4); | |
38 | writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8); | |
39 | writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc); | |
40 | ||
41 | /* Set GPC1 pin 2 to IN - check XCL205 output state */ | |
42 | writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON); | |
43 | writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8); | |
44 | ||
45 | /* XCL205 - needs some latch time */ | |
46 | sdelay(200000); | |
47 | ||
48 | /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */ | |
49 | if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN)) | |
50 | gd->board_type = ODROID_TYPE_X2; | |
51 | else | |
52 | gd->board_type = ODROID_TYPE_U3; | |
53 | } | |
54 | ||
55 | const char *get_board_type(void) | |
56 | { | |
57 | const char *board_type[] = {"u3", "x2"}; | |
58 | ||
59 | return board_type[gd->board_type]; | |
60 | } | |
61 | #endif | |
62 | ||
63 | #ifdef CONFIG_SET_DFU_ALT_INFO | |
64 | char *get_dfu_alt_system(void) | |
65 | { | |
66 | return getenv("dfu_alt_system"); | |
67 | } | |
68 | ||
69 | char *get_dfu_alt_boot(void) | |
70 | { | |
71 | char *alt_boot; | |
72 | ||
73 | switch (get_boot_mode()) { | |
74 | case BOOT_MODE_SD: | |
75 | alt_boot = CONFIG_DFU_ALT_BOOT_SD; | |
76 | break; | |
77 | case BOOT_MODE_EMMC: | |
78 | case BOOT_MODE_EMMC_SD: | |
79 | alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; | |
80 | break; | |
81 | default: | |
82 | alt_boot = NULL; | |
83 | break; | |
84 | } | |
85 | return alt_boot; | |
86 | } | |
87 | #endif | |
88 | ||
89 | static void board_clock_init(void) | |
90 | { | |
91 | unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; | |
92 | struct exynos4x12_clock *clk = (struct exynos4x12_clock *) | |
93 | samsung_get_base_clock(); | |
94 | ||
95 | /* | |
96 | * CMU_CPU clocks src to MPLL | |
97 | * Bit values: 0 ; 1 | |
98 | * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL | |
99 | * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL | |
100 | * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C | |
101 | * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL | |
102 | */ | |
103 | clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) | | |
104 | MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1); | |
105 | set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) | | |
106 | MUX_MPLL_USER_SEL_C(1); | |
107 | ||
108 | clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); | |
109 | ||
110 | /* Wait for mux change */ | |
111 | while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) | |
112 | continue; | |
113 | ||
114 | /* Set APLL to 1000MHz */ | |
115 | clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); | |
116 | set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); | |
117 | ||
118 | clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); | |
119 | ||
120 | /* Wait for PLL to be locked */ | |
121 | while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) | |
122 | continue; | |
123 | ||
124 | /* Set CMU_CPU clocks src to APLL */ | |
125 | set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) | | |
126 | MUX_MPLL_USER_SEL_C(1); | |
127 | clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); | |
128 | ||
129 | /* Wait for mux change */ | |
130 | while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) | |
131 | continue; | |
132 | ||
133 | set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) | | |
134 | PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) | | |
135 | APLL_RATIO(0) | CORE2_RATIO(0); | |
136 | /* | |
137 | * Set dividers for MOUTcore = 1000 MHz | |
138 | * coreout = MOUT / (ratio + 1) = 1000 MHz (0) | |
139 | * corem0 = armclk / (ratio + 1) = 333 MHz (2) | |
140 | * corem1 = armclk / (ratio + 1) = 166 MHz (5) | |
141 | * periph = armclk / (ratio + 1) = 1000 MHz (0) | |
142 | * atbout = MOUT / (ratio + 1) = 200 MHz (4) | |
143 | * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) | |
144 | * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) | |
145 | * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) | |
146 | */ | |
147 | clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | | |
148 | PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) | | |
149 | APLL_RATIO(7) | CORE2_RATIO(7); | |
150 | ||
151 | clrsetbits_le32(&clk->div_cpu0, clr, set); | |
152 | ||
153 | /* Wait for divider ready status */ | |
154 | while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) | |
155 | continue; | |
156 | ||
157 | /* | |
158 | * For MOUThpm = 1000 MHz (MOUTapll) | |
159 | * doutcopy = MOUThpm / (ratio + 1) = 200 (4) | |
160 | * sclkhpm = doutcopy / (ratio + 1) = 200 (4) | |
b2197739 | 161 | * cores_out = armclk / (ratio + 1) = 200 (4) |
bf3a08be PM |
162 | */ |
163 | clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); | |
b2197739 | 164 | set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); |
bf3a08be PM |
165 | |
166 | clrsetbits_le32(&clk->div_cpu1, clr, set); | |
167 | ||
168 | /* Wait for divider ready status */ | |
169 | while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING) | |
170 | continue; | |
171 | ||
172 | /* | |
173 | * Set CMU_DMC clocks src to APLL | |
174 | * Bit values: 0 ; 1 | |
175 | * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL | |
176 | * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL | |
177 | * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL | |
178 | * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT | |
179 | * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) | |
180 | * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL | |
181 | * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL | |
182 | * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1 | |
183 | */ | |
184 | clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | | |
185 | MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) | | |
186 | MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) | | |
187 | MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); | |
188 | set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) | | |
189 | MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) | | |
190 | MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); | |
191 | ||
192 | clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); | |
193 | ||
194 | /* Wait for mux change */ | |
195 | while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) | |
196 | continue; | |
197 | ||
bd99e6d0 MK |
198 | /* Set MPLL to 800MHz */ |
199 | set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); | |
bf3a08be PM |
200 | |
201 | clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); | |
202 | ||
203 | /* Wait for PLL to be locked */ | |
204 | while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) | |
205 | continue; | |
206 | ||
207 | /* Switch back CMU_DMC mux */ | |
208 | set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) | | |
209 | MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) | | |
210 | MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0); | |
211 | ||
212 | clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); | |
213 | ||
214 | /* Wait for mux change */ | |
215 | while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) | |
216 | continue; | |
217 | ||
218 | /* CLK_DIV_DMC0 */ | |
219 | clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | | |
220 | DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); | |
221 | /* | |
222 | * For: | |
bd99e6d0 MK |
223 | * MOUTdmc = 800 MHz |
224 | * MOUTdphy = 800 MHz | |
bf3a08be | 225 | * |
bd99e6d0 MK |
226 | * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) |
227 | * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) | |
228 | * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) | |
229 | * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) | |
230 | * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) | |
231 | * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) | |
bf3a08be PM |
232 | */ |
233 | set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | | |
234 | DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); | |
235 | ||
236 | clrsetbits_le32(&clk->div_dmc0, clr, set); | |
237 | ||
238 | /* Wait for divider ready status */ | |
239 | while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING) | |
240 | continue; | |
241 | ||
242 | /* CLK_DIV_DMC1 */ | |
243 | clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | | |
244 | C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); | |
245 | /* | |
246 | * For: | |
bd99e6d0 MK |
247 | * MOUTg2d = 800 MHz |
248 | * MOUTc2c = 800 Mhz | |
bf3a08be PM |
249 | * MOUTpwi = 108 MHz |
250 | * | |
bd99e6d0 MK |
251 | * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) |
252 | * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) | |
253 | * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) | |
bf3a08be PM |
254 | * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) |
255 | */ | |
256 | set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | | |
257 | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); | |
258 | ||
259 | clrsetbits_le32(&clk->div_dmc1, clr, set); | |
260 | ||
261 | /* Wait for divider ready status */ | |
262 | while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING) | |
263 | continue; | |
264 | ||
265 | /* CLK_SRC_PERIL0 */ | |
266 | clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | | |
267 | UART3_SEL(15) | UART4_SEL(15); | |
268 | /* | |
269 | * Set CLK_SRC_PERIL0 clocks src to MPLL | |
270 | * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0); | |
271 | * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL); | |
272 | * 8(SCLK_VPLL) | |
273 | * | |
274 | * Set all to SCLK_MPLL_USER_T | |
275 | */ | |
276 | set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) | | |
277 | UART4_SEL(6); | |
278 | ||
279 | clrsetbits_le32(&clk->src_peril0, clr, set); | |
280 | ||
281 | /* CLK_DIV_PERIL0 */ | |
282 | clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | | |
283 | UART3_RATIO(15) | UART4_RATIO(15); | |
284 | /* | |
bd99e6d0 | 285 | * For MOUTuart0-4: 800MHz |
bf3a08be | 286 | * |
bd99e6d0 | 287 | * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) |
bf3a08be PM |
288 | */ |
289 | set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | | |
290 | UART3_RATIO(7) | UART4_RATIO(7); | |
291 | ||
292 | clrsetbits_le32(&clk->div_peril0, clr, set); | |
293 | ||
294 | while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING) | |
295 | continue; | |
296 | ||
297 | /* CLK_DIV_FSYS1 */ | |
298 | clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | | |
299 | MMC1_PRE_RATIO(255); | |
300 | /* | |
bd99e6d0 | 301 | * For MOUTmmc0-3 = 800 MHz (MPLL) |
bf3a08be | 302 | * |
bd99e6d0 MK |
303 | * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) |
304 | * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) | |
305 | * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) | |
306 | * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) | |
bf3a08be PM |
307 | */ |
308 | set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | | |
309 | MMC1_PRE_RATIO(1); | |
310 | ||
311 | clrsetbits_le32(&clk->div_fsys1, clr, set); | |
312 | ||
313 | /* Wait for divider ready status */ | |
314 | while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) | |
315 | continue; | |
316 | ||
317 | /* CLK_DIV_FSYS2 */ | |
318 | clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | | |
319 | MMC3_PRE_RATIO(255); | |
320 | /* | |
bd99e6d0 | 321 | * For MOUTmmc0-3 = 800 MHz (MPLL) |
bf3a08be | 322 | * |
bd99e6d0 MK |
323 | * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) |
324 | * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) | |
325 | * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) | |
326 | * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) | |
bf3a08be PM |
327 | */ |
328 | set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | | |
329 | MMC3_PRE_RATIO(1); | |
330 | ||
331 | clrsetbits_le32(&clk->div_fsys2, clr, set); | |
332 | ||
333 | /* Wait for divider ready status */ | |
334 | while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING) | |
335 | continue; | |
336 | ||
337 | /* CLK_DIV_FSYS3 */ | |
338 | clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); | |
339 | /* | |
bd99e6d0 | 340 | * For MOUTmmc4 = 800 MHz (MPLL) |
bf3a08be | 341 | * |
bd99e6d0 MK |
342 | * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) |
343 | * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) | |
bf3a08be PM |
344 | */ |
345 | set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); | |
346 | ||
347 | clrsetbits_le32(&clk->div_fsys3, clr, set); | |
348 | ||
349 | /* Wait for divider ready status */ | |
350 | while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING) | |
351 | continue; | |
352 | ||
353 | return; | |
354 | } | |
355 | ||
356 | static void board_gpio_init(void) | |
357 | { | |
358 | /* eMMC Reset Pin */ | |
4aa97312 PM |
359 | gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset"); |
360 | ||
bf3a08be PM |
361 | gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); |
362 | gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); | |
363 | gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); | |
364 | ||
365 | /* Enable FAN (Odroid U3) */ | |
4aa97312 PM |
366 | gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control"); |
367 | ||
bf3a08be PM |
368 | gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); |
369 | gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); | |
370 | gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); | |
371 | ||
372 | /* OTG Vbus output (Odroid U3+) */ | |
4aa97312 PM |
373 | gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus"); |
374 | ||
bf3a08be PM |
375 | gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); |
376 | gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); | |
377 | gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); | |
378 | ||
379 | /* OTG INT (Odroid U3+) */ | |
4aa97312 PM |
380 | gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT"); |
381 | ||
bf3a08be PM |
382 | gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); |
383 | gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); | |
384 | gpio_direction_input(EXYNOS4X12_GPIO_X31); | |
385 | } | |
386 | ||
387 | static int pmic_init_max77686(void) | |
388 | { | |
389 | struct pmic *p = pmic_get("MAX77686_PMIC"); | |
390 | ||
391 | if (pmic_probe(p)) | |
392 | return -ENODEV; | |
393 | ||
394 | /* Set LDO Voltage */ | |
395 | max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */ | |
396 | max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */ | |
397 | max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */ | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | #ifdef CONFIG_SYS_I2C_INIT_BOARD | |
403 | static void board_init_i2c(void) | |
404 | { | |
405 | /* I2C_0 */ | |
406 | if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE)) | |
407 | debug("I2C%d not configured\n", (I2C_0)); | |
408 | } | |
409 | #endif | |
410 | ||
411 | int exynos_early_init_f(void) | |
412 | { | |
413 | board_clock_init(); | |
bf3a08be PM |
414 | |
415 | return 0; | |
416 | } | |
417 | ||
418 | int exynos_init(void) | |
419 | { | |
420 | /* The last MB of memory is reserved for secure firmware */ | |
421 | gd->ram_size -= SZ_1M; | |
422 | gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M; | |
423 | ||
4aa97312 PM |
424 | board_gpio_init(); |
425 | ||
bf3a08be PM |
426 | return 0; |
427 | } | |
428 | ||
429 | int exynos_power_init(void) | |
430 | { | |
431 | #ifdef CONFIG_SYS_I2C_INIT_BOARD | |
432 | board_init_i2c(); | |
433 | #endif | |
434 | pmic_init(I2C_0); | |
435 | pmic_init_max77686(); | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | #ifdef CONFIG_USB_GADGET | |
441 | static int s5pc210_phy_control(int on) | |
442 | { | |
443 | struct pmic *p_pmic; | |
444 | ||
445 | p_pmic = pmic_get("MAX77686_PMIC"); | |
446 | if (!p_pmic) | |
447 | return -ENODEV; | |
448 | ||
449 | if (pmic_probe(p_pmic)) | |
450 | return -1; | |
451 | ||
452 | if (on) | |
453 | return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON); | |
454 | else | |
455 | return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM); | |
456 | } | |
457 | ||
458 | struct s3c_plat_otg_data s5pc210_otg_data = { | |
459 | .phy_control = s5pc210_phy_control, | |
460 | .regs_phy = EXYNOS4X12_USBPHY_BASE, | |
461 | .regs_otg = EXYNOS4X12_USBOTG_BASE, | |
462 | .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, | |
463 | .usb_flags = PHY0_SLEEP, | |
464 | }; | |
465 | ||
466 | int board_usb_init(int index, enum usb_init_type init) | |
467 | { | |
468 | debug("USB_udc_probe\n"); | |
469 | return s3c_udc_probe(&s5pc210_otg_data); | |
470 | } | |
471 | #endif | |
472 | ||
473 | void reset_misc(void) | |
474 | { | |
475 | /* Reset eMMC*/ | |
476 | gpio_set_value(EXYNOS4X12_GPIO_K12, 0); | |
477 | mdelay(10); | |
478 | gpio_set_value(EXYNOS4X12_GPIO_K12, 1); | |
479 | } |