[people/ms/u-boot.git] / board / samsung / origen / mem_setup.S

/*
 * Memory setup for ORIGEN board based on EXYNOS4210
 *
 * Copyright (C) 2011 Samsung Electronics
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include "origen_setup.h"
#define SET_MIU

	.globl mem_ctrl_asm_init
mem_ctrl_asm_init:
	/*
	 * Async bridge configuration at CPU_core:
	 * 1: half_sync
	 * 0: full_sync
	 */
	ldr r0, =ASYNC_CONFIG
	mov r1, #1
	str r1, [r0]

#ifdef SET_MIU
	ldr	r0, =EXYNOS4_MIU_BASE
	/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
	ldr	r1, =0x20001507
	str	r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]

	/* Update MIU Configuration */
	ldr	r1, =0x00000001
	str	r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
#endif
	/* DREX0 */
	ldr	r0, =EXYNOS4_DMC0_BASE

	/*
	 * DLL Parameter Setting:
	 * Termination: Enable R/W
	 * Phase Delay for DQS Cleaning: 180' Shift
	 */
	ldr	r1, =0xe0000086
	str	r1, [r0, #DMC_PHYCONTROL1]

	/*
	 * ZQ Calibration
	 * Termination: Disable
	 * Auto Calibration Start: Enable
	 */
	ldr	r1, =0xE3855703
	str	r1, [r0, #DMC_PHYZQCONTROL]

	/* Wait ?us*/
	mov	r2, #0x100000
1:	subs	r2, r2, #1
	bne	1b

	/*
	 * Update DLL Information:
	 * Force DLL Resyncronization
	 */
	ldr	r1, =0xe000008e
	str	r1, [r0, #DMC_PHYCONTROL1]

	/* Reset Force DLL Resyncronization */
	ldr	r1, =0xe0000086
	str	r1, [r0, #DMC_PHYCONTROL1]

	/* Enable Differential DQS, DLL Off*/
	ldr	r1, =0x71101008
	str	r1, [r0, #DMC_PHYCONTROL0]

	/* Activate PHY DLL: DLL On */
	ldr	r1, =0x7110100A
	str	r1, [r0, #DMC_PHYCONTROL0]

	/* Set DLL Parameters */
	ldr	r1, =0xe0000086
	str	r1, [r0, #DMC_PHYCONTROL1]

	/* DLL Start */
	ldr	r1, =0x7110100B
	str	r1, [r0, #DMC_PHYCONTROL0]

	ldr	r1, =0x00000000
	str	r1, [r0, #DMC_PHYCONTROL2]

	/* Set Clock Ratio of Bus clock to Memory Clock */
	ldr	r1, =0x0FFF301a
	str	r1, [r0, #DMC_CONCONTROL]

	/*
	 * Memor Burst length: 8
	 * Number of chips: 2
	 * Memory Bus width: 32 bit
	 * Memory Type: DDR3
	 * Additional Latancy for PLL: 1 Cycle
	 */
	ldr	r1, =0x00312640
	str	r1, [r0, #DMC_MEMCONTROL]

	/*
	 * Memory Configuration Chip 0
	 * Address Mapping: Interleaved
	 * Number of Column address Bits: 10 bits
	 * Number of Rows Address Bits: 14
	 * Number of Banks: 8
	 */
	ldr	r1, =0x20e01323
	str	r1, [r0, #DMC_MEMCONFIG0]

	/*
	 * Memory Configuration Chip 1
	 * Address Mapping: Interleaved
	 * Number of Column address Bits: 10 bits
	 * Number of Rows Address Bits: 14
	 * Number of Banks: 8
	 */
	ldr	r1, =0x40e01323
	str	r1, [r0, #DMC_MEMCONFIG1]

	/* Config Precharge Policy */
	ldr	r1, =0xff000000
	str	r1, [r0, #DMC_PRECHCONFIG]

	/*
	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
	 * Values as per Memory AC Parameters
	 */
	ldr	r1, =0x000000BB
	str	r1, [r0, #DMC_TIMINGAREF]
	ldr	r1, =0x4046654f
	str	r1, [r0, #DMC_TIMINGROW]
	ldr	r1, =0x46400506
	str	r1, [r0, #DMC_TIMINGDATA]
	ldr	r1, =0x52000A3C
	str	r1, [r0, #DMC_TIMINGPOWER]

	/* Chip0: NOP Command: Assert and Hold CKE to high level */
	ldr	r1, =0x07000000
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
2:	subs	r2, r2, #1
	bne	2b

	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
	ldr	r1, =0x00020000
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00030000
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00010002
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00000328
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
3:	subs	r2, r2, #1
	bne	3b

	/* Chip0: ZQINIT */
	ldr	r1, =0x0a000000
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
4:	subs	r2, r2, #1
	bne	4b

	/* Chip1: NOP Command: Assert and Hold CKE to high level */
	ldr	r1, =0x07100000
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
5:	subs	r2, r2, #1
	bne	5b

	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
	ldr	r1, =0x00120000
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00130000
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00110002
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00100328
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
6:	subs	r2, r2, #1
	bne	6b

	/* Chip1: ZQINIT */
	ldr	r1, =0x0a100000
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
7:	subs	r2, r2, #1
	bne	7b

	ldr	r1, =0xe000008e
	str	r1, [r0, #DMC_PHYCONTROL1]
	ldr	r1, =0xe0000086
	str	r1, [r0, #DMC_PHYCONTROL1]

	/* Wait ?us*/
	mov	r2, #0x100000
8:	subs	r2, r2, #1
	bne	8b

	/* DREX1 */
	ldr	r0, =EXYNOS4_DMC1_BASE	@0x10410000

	/*
	 * DLL Parameter Setting:
	 * Termination: Enable R/W
	 * Phase Delay for DQS Cleaning: 180' Shift
	 */
	ldr	r1, =0xe0000086
	str	r1, [r0, #DMC_PHYCONTROL1]

	/*
	 * ZQ Calibration:
	 * Termination: Disable
	 * Auto Calibration Start: Enable
	 */
	ldr	r1, =0xE3855703
	str	r1, [r0, #DMC_PHYZQCONTROL]

	/* Wait ?us*/
	mov	r2, #0x100000
1:	subs	r2, r2, #1
	bne	1b

	/*
	 * Update DLL Information:
	 * Force DLL Resyncronization
	 */
	ldr	r1, =0xe000008e
	str	r1, [r0, #DMC_PHYCONTROL1]

	/* Reset Force DLL Resyncronization */
	ldr	r1, =0xe0000086
	str	r1, [r0, #DMC_PHYCONTROL1]

	/* Enable Differential DQS, DLL Off*/
	ldr	r1, =0x71101008
	str	r1, [r0, #DMC_PHYCONTROL0]

	/* Activate PHY DLL: DLL On */
	ldr	r1, =0x7110100A
	str	r1, [r0, #DMC_PHYCONTROL0]

	/* Set DLL Parameters */
	ldr	r1, =0xe0000086
	str	r1, [r0, #DMC_PHYCONTROL1]

	/* DLL Start */
	ldr	r1, =0x7110100B
	str	r1, [r0, #DMC_PHYCONTROL0]

	ldr	r1, =0x00000000
	str	r1, [r0, #DMC_PHYCONTROL2]

	/* Set Clock Ratio of Bus clock to Memory Clock */
	ldr	r1, =0x0FFF301a
	str	r1, [r0, #DMC_CONCONTROL]

	/*
	 * Memor Burst length: 8
	 * Number of chips: 2
	 * Memory Bus width: 32 bit
	 * Memory Type: DDR3
	 * Additional Latancy for PLL: 1 Cycle
	 */
	ldr	r1, =0x00312640
	str	r1, [r0, #DMC_MEMCONTROL]

	/*
	 * Memory Configuration Chip 0
	 * Address Mapping: Interleaved
	 * Number of Column address Bits: 10 bits
	 * Number of Rows Address Bits: 14
	 * Number of Banks: 8
	 */
	ldr	r1, =0x20e01323
	str	r1, [r0, #DMC_MEMCONFIG0]

	/*
	 * Memory Configuration Chip 1
	 * Address Mapping: Interleaved
	 * Number of Column address Bits: 10 bits
	 * Number of Rows Address Bits: 14
	 * Number of Banks: 8
	 */
	ldr	r1, =0x40e01323
	str	r1, [r0, #DMC_MEMCONFIG1]

	/* Config Precharge Policy */
	ldr	r1, =0xff000000
	str	r1, [r0, #DMC_PRECHCONFIG]

	/*
	 * TimingAref, TimingRow, TimingData, TimingPower Setting:
	 * Values as per Memory AC Parameters
	 */
	ldr	r1, =0x000000BB
	str	r1, [r0, #DMC_TIMINGAREF]
	ldr	r1, =0x4046654f
	str	r1, [r0, #DMC_TIMINGROW]
	ldr	r1, =0x46400506
	str	r1, [r0, #DMC_TIMINGDATA]
	ldr	r1, =0x52000A3C
	str	r1, [r0, #DMC_TIMINGPOWER]

	/* Chip0: NOP Command: Assert and Hold CKE to high level */
	ldr	r1, =0x07000000
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
2:	subs	r2, r2, #1
	bne	2b

	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
	ldr	r1, =0x00020000
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00030000
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00010002
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00000328
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
3:	subs	r2, r2, #1
	bne	3b

	/* Chip 0: ZQINIT */
	ldr	r1, =0x0a000000
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
4:	subs	r2, r2, #1
	bne	4b

	/* Chip1: NOP Command: Assert and Hold CKE to high level */
	ldr	r1, =0x07100000
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
5:	subs	r2, r2, #1
	bne	5b

	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
	ldr	r1, =0x00120000
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00130000
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00110002
	str	r1, [r0, #DMC_DIRECTCMD]
	ldr	r1, =0x00100328
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
6:	subs	r2, r2, #1
	bne	6b

	/* Chip1: ZQINIT */
	ldr	r1, =0x0a100000
	str	r1, [r0, #DMC_DIRECTCMD]

	/* Wait ?us*/
	mov	r2, #0x100000
7:	subs	r2, r2, #1
	bne	7b

	ldr	r1, =0xe000008e
	str	r1, [r0, #DMC_PHYCONTROL1]
	ldr	r1, =0xe0000086
	str	r1, [r0, #DMC_PHYCONTROL1]

	/* Wait ?us*/
	mov	r2, #0x100000
8:	subs	r2, r2, #1
	bne	8b

	/* turn on DREX0, DREX1 */
	ldr	r0, =EXYNOS4_DMC0_BASE
	ldr	r1, =0x0FFF303a
	str	r1, [r0, #DMC_CONCONTROL]

	ldr	r0, =EXYNOS4_DMC1_BASE
	ldr	r1, =0x0FFF303a
	str	r1, [r0, #DMC_CONCONTROL]

	mov	pc, lr
Commit	Line	Data
b9a1ef21	1	/*
393cb361	2	* Memory setup for ORIGEN board based on EXYNOS4210
b9a1ef21 CK	3	*
	4	* Copyright (C) 2011 Samsung Electronics
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <config.h>
	26	#include "origen_setup.h"
	27	#define SET_MIU
	28
	29	.globl mem_ctrl_asm_init
	30	mem_ctrl_asm_init:
	31	/*
	32	* Async bridge configuration at CPU_core:
	33	* 1: half_sync
	34	* 0: full_sync
	35	*/
	36	ldr r0, =ASYNC_CONFIG
	37	mov r1, #1
	38	str r1, [r0]
	39
	40	#ifdef SET_MIU
393cb361	41	ldr r0, =EXYNOS4_MIU_BASE
b9a1ef21 CK	42	/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
	43	ldr r1, =0x20001507
	44	str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
	45
	46	/* Update MIU Configuration */
	47	ldr r1, =0x00000001
	48	str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
	49	#endif
	50	/* DREX0 */
393cb361	51	ldr r0, =EXYNOS4_DMC0_BASE
b9a1ef21 CK	52
	53	/*
	54	* DLL Parameter Setting:
	55	* Termination: Enable R/W
	56	* Phase Delay for DQS Cleaning: 180' Shift
	57	*/
	58	ldr r1, =0xe0000086
	59	str r1, [r0, #DMC_PHYCONTROL1]
	60
	61	/*
	62	* ZQ Calibration
	63	* Termination: Disable
	64	* Auto Calibration Start: Enable
	65	*/
	66	ldr r1, =0xE3855703
	67	str r1, [r0, #DMC_PHYZQCONTROL]
	68
	69	/* Wait ?us*/
	70	mov r2, #0x100000
	71	1: subs r2, r2, #1
	72	bne 1b
	73
	74	/*
	75	* Update DLL Information:
	76	* Force DLL Resyncronization
	77	*/
	78	ldr r1, =0xe000008e
	79	str r1, [r0, #DMC_PHYCONTROL1]
	80
	81	/* Reset Force DLL Resyncronization */
	82	ldr r1, =0xe0000086
	83	str r1, [r0, #DMC_PHYCONTROL1]
	84
	85	/* Enable Differential DQS, DLL Off*/
	86	ldr r1, =0x71101008
	87	str r1, [r0, #DMC_PHYCONTROL0]
	88
	89	/* Activate PHY DLL: DLL On */
	90	ldr r1, =0x7110100A
	91	str r1, [r0, #DMC_PHYCONTROL0]
	92
	93	/* Set DLL Parameters */
	94	ldr r1, =0xe0000086
	95	str r1, [r0, #DMC_PHYCONTROL1]
	96
	97	/* DLL Start */
	98	ldr r1, =0x7110100B
	99	str r1, [r0, #DMC_PHYCONTROL0]
	100
	101	ldr r1, =0x00000000
	102	str r1, [r0, #DMC_PHYCONTROL2]
	103
	104	/* Set Clock Ratio of Bus clock to Memory Clock */
	105	ldr r1, =0x0FFF301a
	106	str r1, [r0, #DMC_CONCONTROL]
	107
	108	/*
	109	* Memor Burst length: 8
	110	* Number of chips: 2
	111	* Memory Bus width: 32 bit
	112	* Memory Type: DDR3
	113	* Additional Latancy for PLL: 1 Cycle
	114	*/
	115	ldr r1, =0x00312640
116	str r1, [r0, #DMC_MEMCONTROL]
117
118	/*
119	* Memory Configuration Chip 0
120	* Address Mapping: Interleaved
121	* Number of Column address Bits: 10 bits
122	* Number of Rows Address Bits: 14
123	* Number of Banks: 8
124	*/
125	ldr r1, =0x20e01323
126	str r1, [r0, #DMC_MEMCONFIG0]
127
128	/*
129	* Memory Configuration Chip 1
130	* Address Mapping: Interleaved
131	* Number of Column address Bits: 10 bits
132	* Number of Rows Address Bits: 14
133	* Number of Banks: 8
134	*/
135	ldr r1, =0x40e01323
136	str r1, [r0, #DMC_MEMCONFIG1]
137
138	/* Config Precharge Policy */
139	ldr r1, =0xff000000
140	str r1, [r0, #DMC_PRECHCONFIG]
141
142	/*
143	* TimingAref, TimingRow, TimingData, TimingPower Setting:
144	* Values as per Memory AC Parameters
145	*/
146	ldr r1, =0x000000BB
147	str r1, [r0, #DMC_TIMINGAREF]
148	ldr r1, =0x4046654f
149	str r1, [r0, #DMC_TIMINGROW]
150	ldr r1, =0x46400506
151	str r1, [r0, #DMC_TIMINGDATA]
152	ldr r1, =0x52000A3C
153	str r1, [r0, #DMC_TIMINGPOWER]
154
155	/* Chip0: NOP Command: Assert and Hold CKE to high level */
156	ldr r1, =0x07000000
157	str r1, [r0, #DMC_DIRECTCMD]
158
159	/* Wait ?us*/
160	mov r2, #0x100000
161	2: subs r2, r2, #1
162	bne 2b
163
164	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
165	ldr r1, =0x00020000
166	str r1, [r0, #DMC_DIRECTCMD]
167	ldr r1, =0x00030000
168	str r1, [r0, #DMC_DIRECTCMD]
169	ldr r1, =0x00010002
170	str r1, [r0, #DMC_DIRECTCMD]
171	ldr r1, =0x00000328
172	str r1, [r0, #DMC_DIRECTCMD]
173
174	/* Wait ?us*/
175	mov r2, #0x100000
176	3: subs r2, r2, #1
177	bne 3b
178
179	/* Chip0: ZQINIT */
180	ldr r1, =0x0a000000
181	str r1, [r0, #DMC_DIRECTCMD]
182
183	/* Wait ?us*/
184	mov r2, #0x100000
185	4: subs r2, r2, #1
186	bne 4b
187
188	/* Chip1: NOP Command: Assert and Hold CKE to high level */
189	ldr r1, =0x07100000
190	str r1, [r0, #DMC_DIRECTCMD]
191
192	/* Wait ?us*/
193	mov r2, #0x100000
194	5: subs r2, r2, #1
195	bne 5b
196
197	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
198	ldr r1, =0x00120000
199	str r1, [r0, #DMC_DIRECTCMD]
200	ldr r1, =0x00130000
201	str r1, [r0, #DMC_DIRECTCMD]
202	ldr r1, =0x00110002
203	str r1, [r0, #DMC_DIRECTCMD]
204	ldr r1, =0x00100328
205	str r1, [r0, #DMC_DIRECTCMD]
206
207	/* Wait ?us*/
208	mov r2, #0x100000
209	6: subs r2, r2, #1
210	bne 6b
211
212	/* Chip1: ZQINIT */
213	ldr r1, =0x0a100000
214	str r1, [r0, #DMC_DIRECTCMD]
215
216	/* Wait ?us*/
217	mov r2, #0x100000
218	7: subs r2, r2, #1
219	bne 7b
220
221	ldr r1, =0xe000008e
222	str r1, [r0, #DMC_PHYCONTROL1]
223	ldr r1, =0xe0000086
224	str r1, [r0, #DMC_PHYCONTROL1]
225
226	/* Wait ?us*/
227	mov r2, #0x100000
228	8: subs r2, r2, #1
229	bne 8b
230
231	/* DREX1 */
393cb361	232	ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
b9a1ef21 CK	233
	234	/*
	235	* DLL Parameter Setting:
	236	* Termination: Enable R/W
	237	* Phase Delay for DQS Cleaning: 180' Shift
	238	*/
	239	ldr r1, =0xe0000086
	240	str r1, [r0, #DMC_PHYCONTROL1]
	241
	242	/*
	243	* ZQ Calibration:
	244	* Termination: Disable
	245	* Auto Calibration Start: Enable
	246	*/
	247	ldr r1, =0xE3855703
	248	str r1, [r0, #DMC_PHYZQCONTROL]
	249
	250	/* Wait ?us*/
	251	mov r2, #0x100000
	252	1: subs r2, r2, #1
	253	bne 1b
	254
	255	/*
	256	* Update DLL Information:
	257	* Force DLL Resyncronization
	258	*/
	259	ldr r1, =0xe000008e
	260	str r1, [r0, #DMC_PHYCONTROL1]
	261
	262	/* Reset Force DLL Resyncronization */
	263	ldr r1, =0xe0000086
	264	str r1, [r0, #DMC_PHYCONTROL1]
	265
	266	/* Enable Differential DQS, DLL Off*/
	267	ldr r1, =0x71101008
	268	str r1, [r0, #DMC_PHYCONTROL0]
	269
	270	/* Activate PHY DLL: DLL On */
	271	ldr r1, =0x7110100A
	272	str r1, [r0, #DMC_PHYCONTROL0]
	273
	274	/* Set DLL Parameters */
	275	ldr r1, =0xe0000086
	276	str r1, [r0, #DMC_PHYCONTROL1]
	277
	278	/* DLL Start */
	279	ldr r1, =0x7110100B
	280	str r1, [r0, #DMC_PHYCONTROL0]
	281
	282	ldr r1, =0x00000000
	283	str r1, [r0, #DMC_PHYCONTROL2]
	284
	285	/* Set Clock Ratio of Bus clock to Memory Clock */
	286	ldr r1, =0x0FFF301a
	287	str r1, [r0, #DMC_CONCONTROL]
	288
	289	/*
	290	* Memor Burst length: 8
	291	* Number of chips: 2
	292	* Memory Bus width: 32 bit
	293	* Memory Type: DDR3
	294	* Additional Latancy for PLL: 1 Cycle
	295	*/
	296	ldr r1, =0x00312640
297	str r1, [r0, #DMC_MEMCONTROL]
298
299	/*
300	* Memory Configuration Chip 0
301	* Address Mapping: Interleaved
302	* Number of Column address Bits: 10 bits
303	* Number of Rows Address Bits: 14
304	* Number of Banks: 8
305	*/
306	ldr r1, =0x20e01323
307	str r1, [r0, #DMC_MEMCONFIG0]
308
309	/*
310	* Memory Configuration Chip 1
311	* Address Mapping: Interleaved
312	* Number of Column address Bits: 10 bits
313	* Number of Rows Address Bits: 14
314	* Number of Banks: 8
315	*/
316	ldr r1, =0x40e01323
317	str r1, [r0, #DMC_MEMCONFIG1]
318
319	/* Config Precharge Policy */
320	ldr r1, =0xff000000
321	str r1, [r0, #DMC_PRECHCONFIG]
322
323	/*
324	* TimingAref, TimingRow, TimingData, TimingPower Setting:
325	* Values as per Memory AC Parameters
326	*/
327	ldr r1, =0x000000BB
328	str r1, [r0, #DMC_TIMINGAREF]
329	ldr r1, =0x4046654f
330	str r1, [r0, #DMC_TIMINGROW]
331	ldr r1, =0x46400506
332	str r1, [r0, #DMC_TIMINGDATA]
333	ldr r1, =0x52000A3C
334	str r1, [r0, #DMC_TIMINGPOWER]
335
336	/* Chip0: NOP Command: Assert and Hold CKE to high level */
337	ldr r1, =0x07000000
338	str r1, [r0, #DMC_DIRECTCMD]
339
340	/* Wait ?us*/
341	mov r2, #0x100000
342	2: subs r2, r2, #1
343	bne 2b
344
345	/* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
346	ldr r1, =0x00020000
347	str r1, [r0, #DMC_DIRECTCMD]
348	ldr r1, =0x00030000
349	str r1, [r0, #DMC_DIRECTCMD]
350	ldr r1, =0x00010002
351	str r1, [r0, #DMC_DIRECTCMD]
352	ldr r1, =0x00000328
353	str r1, [r0, #DMC_DIRECTCMD]
354
355	/* Wait ?us*/
356	mov r2, #0x100000
357	3: subs r2, r2, #1
358	bne 3b
359
360	/* Chip 0: ZQINIT */
361	ldr r1, =0x0a000000
362	str r1, [r0, #DMC_DIRECTCMD]
363
364	/* Wait ?us*/
365	mov r2, #0x100000
366	4: subs r2, r2, #1
367	bne 4b
368
369	/* Chip1: NOP Command: Assert and Hold CKE to high level */
370	ldr r1, =0x07100000
371	str r1, [r0, #DMC_DIRECTCMD]
372
373	/* Wait ?us*/
374	mov r2, #0x100000
375	5: subs r2, r2, #1
376	bne 5b
377
378	/* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
379	ldr r1, =0x00120000
380	str r1, [r0, #DMC_DIRECTCMD]
381	ldr r1, =0x00130000
382	str r1, [r0, #DMC_DIRECTCMD]
383	ldr r1, =0x00110002
384	str r1, [r0, #DMC_DIRECTCMD]
385	ldr r1, =0x00100328
386	str r1, [r0, #DMC_DIRECTCMD]
387
388	/* Wait ?us*/
389	mov r2, #0x100000
390	6: subs r2, r2, #1
391	bne 6b
392
393	/* Chip1: ZQINIT */
394	ldr r1, =0x0a100000
395	str r1, [r0, #DMC_DIRECTCMD]
396
397	/* Wait ?us*/
398	mov r2, #0x100000
399	7: subs r2, r2, #1
400	bne 7b
401
402	ldr r1, =0xe000008e
403	str r1, [r0, #DMC_PHYCONTROL1]
404	ldr r1, =0xe0000086
405	str r1, [r0, #DMC_PHYCONTROL1]
406
407	/* Wait ?us*/
408	mov r2, #0x100000
409	8: subs r2, r2, #1
410	bne 8b
411
412	/* turn on DREX0, DREX1 */
393cb361	413	ldr r0, =EXYNOS4_DMC0_BASE
b9a1ef21 CK	414	ldr r1, =0x0FFF303a
	415	str r1, [r0, #DMC_CONCONTROL]
	416
393cb361	417	ldr r0, =EXYNOS4_DMC1_BASE
b9a1ef21 CK	418	ldr r1, =0x0FFF303a
	419	str r1, [r0, #DMC_CONCONTROL]
	420
	421	mov pc, lr