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1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2002 | |
7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
b1c0eaac | 29 | #include <netdev.h> |
c609719b WD |
30 | #include <s3c2410.h> |
31 | ||
d87080b7 | 32 | DECLARE_GLOBAL_DATA_PTR; |
c609719b WD |
33 | |
34 | #define FCLK_SPEED 1 | |
35 | ||
36 | #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ | |
37 | #define M_MDIV 0xC3 | |
38 | #define M_PDIV 0x4 | |
39 | #define M_SDIV 0x1 | |
40 | #elif FCLK_SPEED==1 /* Fout = 202.8MHz */ | |
41 | #define M_MDIV 0xA1 | |
42 | #define M_PDIV 0x3 | |
43 | #define M_SDIV 0x1 | |
44 | #endif | |
45 | ||
46 | #define USB_CLOCK 1 | |
47 | ||
48 | #if USB_CLOCK==0 | |
49 | #define U_M_MDIV 0xA1 | |
50 | #define U_M_PDIV 0x3 | |
51 | #define U_M_SDIV 0x1 | |
52 | #elif USB_CLOCK==1 | |
53 | #define U_M_MDIV 0x48 | |
54 | #define U_M_PDIV 0x3 | |
55 | #define U_M_SDIV 0x2 | |
56 | #endif | |
57 | ||
58 | static inline void delay (unsigned long loops) | |
59 | { | |
60 | __asm__ volatile ("1:\n" | |
61 | "subs %0, %1, #1\n" | |
62 | "bne 1b":"=r" (loops):"0" (loops)); | |
63 | } | |
64 | ||
65 | /* | |
66 | * Miscellaneous platform dependent initialisations | |
67 | */ | |
68 | ||
69 | int board_init (void) | |
70 | { | |
eb0ae7f5 | 71 | struct s3c24x0_clock_power * const clk_power = |
72 | s3c24x0_get_base_clock_power(); | |
73 | struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); | |
c609719b WD |
74 | |
75 | /* to reduce PLL lock time, adjust the LOCKTIME register */ | |
48b42616 | 76 | clk_power->LOCKTIME = 0xFFFFFF; |
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77 | |
78 | /* configure MPLL */ | |
48b42616 | 79 | clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); |
c609719b WD |
80 | |
81 | /* some delay between MPLL and UPLL */ | |
82 | delay (4000); | |
83 | ||
84 | /* configure UPLL */ | |
48b42616 | 85 | clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); |
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86 | |
87 | /* some delay between MPLL and UPLL */ | |
88 | delay (8000); | |
89 | ||
90 | /* set up the I/O ports */ | |
48b42616 WD |
91 | gpio->GPACON = 0x007FFFFF; |
92 | gpio->GPBCON = 0x00044555; | |
93 | gpio->GPBUP = 0x000007FF; | |
94 | gpio->GPCCON = 0xAAAAAAAA; | |
95 | gpio->GPCUP = 0x0000FFFF; | |
96 | gpio->GPDCON = 0xAAAAAAAA; | |
97 | gpio->GPDUP = 0x0000FFFF; | |
98 | gpio->GPECON = 0xAAAAAAAA; | |
99 | gpio->GPEUP = 0x0000FFFF; | |
100 | gpio->GPFCON = 0x000055AA; | |
101 | gpio->GPFUP = 0x000000FF; | |
102 | gpio->GPGCON = 0xFF95FFBA; | |
103 | gpio->GPGUP = 0x0000FFFF; | |
104 | gpio->GPHCON = 0x002AFAAA; | |
105 | gpio->GPHUP = 0x000007FF; | |
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106 | |
107 | /* arch number of SMDK2410-Board */ | |
731215eb | 108 | gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; |
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109 | |
110 | /* adress of boot parameters */ | |
111 | gd->bd->bi_boot_params = 0x30000100; | |
112 | ||
113 | icache_enable(); | |
114 | dcache_enable(); | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | int dram_init (void) | |
120 | { | |
c609719b WD |
121 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
122 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
123 | ||
124 | return 0; | |
125 | } | |
b1c0eaac BW |
126 | |
127 | #ifdef CONFIG_CMD_NET | |
128 | int board_eth_init(bd_t *bis) | |
129 | { | |
130 | int rc = 0; | |
131 | #ifdef CONFIG_CS8900 | |
132 | rc = cs8900_initialize(0, CONFIG_CS8900_BASE); | |
133 | #endif | |
134 | return rc; | |
135 | } | |
136 | #endif |