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752f4c4a A |
1 | /* |
2 | * Copyright (C) 2012 Samsung Electronics | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
752f4c4a A |
5 | */ |
6 | ||
7 | #include <common.h> | |
eb28fdac | 8 | #include <cros_ec.h> |
752f4c4a A |
9 | #include <fdtdec.h> |
10 | #include <asm/io.h> | |
11 | #include <errno.h> | |
12 | #include <i2c.h> | |
13 | #include <netdev.h> | |
14 | #include <spi.h> | |
15 | #include <asm/arch/cpu.h> | |
16 | #include <asm/arch/dwmmc.h> | |
17 | #include <asm/arch/gpio.h> | |
18 | #include <asm/arch/mmc.h> | |
19 | #include <asm/arch/pinmux.h> | |
20 | #include <asm/arch/power.h> | |
21 | #include <asm/arch/sromc.h> | |
22 | #include <power/pmic.h> | |
23 | #include <power/max77686_pmic.h> | |
24 | #include <tmu.h> | |
25 | ||
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
28 | #if defined CONFIG_EXYNOS_TMU | |
29 | /* | |
30 | * Boot Time Thermal Analysis for SoC temperature threshold breach | |
31 | */ | |
32 | static void boot_temp_check(void) | |
33 | { | |
34 | int temp; | |
35 | ||
36 | switch (tmu_monitor(&temp)) { | |
37 | /* Status TRIPPED ans WARNING means corresponding threshold breach */ | |
38 | case TMU_STATUS_TRIPPED: | |
39 | puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); | |
40 | set_ps_hold_ctrl(); | |
41 | hang(); | |
42 | break; | |
43 | case TMU_STATUS_WARNING: | |
44 | puts("EXYNOS_TMU: WARNING! Temperature very high\n"); | |
45 | break; | |
46 | /* | |
47 | * TMU_STATUS_INIT means something is wrong with temperature sensing | |
48 | * and TMU status was changed back from NORMAL to INIT. | |
49 | */ | |
50 | case TMU_STATUS_INIT: | |
51 | default: | |
52 | debug("EXYNOS_TMU: Unknown TMU state\n"); | |
53 | } | |
54 | } | |
55 | #endif | |
56 | ||
eb28fdac HT |
57 | struct local_info { |
58 | struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ | |
59 | int cros_ec_err; /* Error for cros_ec, 0 if ok */ | |
60 | }; | |
61 | ||
62 | static struct local_info local; | |
63 | ||
752f4c4a A |
64 | #ifdef CONFIG_SOUND_MAX98095 |
65 | static void board_enable_audio_codec(void) | |
66 | { | |
67 | struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) | |
68 | samsung_get_base_gpio_part1(); | |
69 | ||
70 | /* Enable MAX98095 Codec */ | |
71 | s5p_gpio_direction_output(&gpio1->x1, 7, 1); | |
72 | s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); | |
73 | } | |
74 | #endif | |
75 | ||
eb28fdac HT |
76 | struct cros_ec_dev *board_get_cros_ec_dev(void) |
77 | { | |
78 | return local.cros_ec_dev; | |
79 | } | |
80 | ||
81 | static int board_init_cros_ec_devices(const void *blob) | |
82 | { | |
83 | local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); | |
84 | if (local.cros_ec_err) | |
85 | return -1; /* Will report in board_late_init() */ | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
752f4c4a A |
90 | int board_init(void) |
91 | { | |
92 | gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); | |
93 | ||
94 | #if defined CONFIG_EXYNOS_TMU | |
95 | if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { | |
96 | debug("%s: Failed to init TMU\n", __func__); | |
97 | return -1; | |
98 | } | |
99 | boot_temp_check(); | |
100 | #endif | |
101 | ||
102 | #ifdef CONFIG_EXYNOS_SPI | |
103 | spi_init(); | |
104 | #endif | |
eb28fdac HT |
105 | |
106 | if (board_init_cros_ec_devices(gd->fdt_blob)) | |
107 | return -1; | |
108 | ||
752f4c4a A |
109 | #ifdef CONFIG_SOUND_MAX98095 |
110 | board_enable_audio_codec(); | |
111 | #endif | |
112 | return 0; | |
113 | } | |
114 | ||
115 | int dram_init(void) | |
116 | { | |
117 | int i; | |
118 | u32 addr; | |
119 | ||
120 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
121 | addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); | |
122 | gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); | |
123 | } | |
124 | return 0; | |
125 | } | |
126 | ||
127 | #if defined(CONFIG_POWER) | |
128 | static int pmic_reg_update(struct pmic *p, int reg, uint regval) | |
129 | { | |
130 | u32 val; | |
131 | int ret = 0; | |
132 | ||
133 | ret = pmic_reg_read(p, reg, &val); | |
134 | if (ret) { | |
135 | debug("%s: PMIC %d register read failed\n", __func__, reg); | |
136 | return -1; | |
137 | } | |
138 | val |= regval; | |
139 | ret = pmic_reg_write(p, reg, val); | |
140 | if (ret) { | |
141 | debug("%s: PMIC %d register write failed\n", __func__, reg); | |
142 | return -1; | |
143 | } | |
144 | return 0; | |
145 | } | |
146 | ||
147 | int power_init_board(void) | |
148 | { | |
149 | struct pmic *p; | |
150 | ||
151 | set_ps_hold_ctrl(); | |
152 | ||
752f4c4a A |
153 | if (pmic_init(I2C_PMIC)) |
154 | return -1; | |
155 | ||
156 | p = pmic_get("MAX77686_PMIC"); | |
157 | if (!p) | |
158 | return -ENODEV; | |
159 | ||
160 | if (pmic_probe(p)) | |
161 | return -1; | |
162 | ||
163 | if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) | |
164 | return -1; | |
165 | ||
166 | if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, | |
167 | MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) | |
168 | return -1; | |
169 | ||
170 | /* VDD_MIF */ | |
171 | if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, | |
172 | MAX77686_BUCK1OUT_1V)) { | |
173 | debug("%s: PMIC %d register write failed\n", __func__, | |
174 | MAX77686_REG_PMIC_BUCK1OUT); | |
175 | return -1; | |
176 | } | |
177 | ||
178 | if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, | |
179 | MAX77686_BUCK1CTRL_EN)) | |
180 | return -1; | |
181 | ||
182 | /* VDD_ARM */ | |
183 | if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, | |
184 | MAX77686_BUCK2DVS1_1_3V)) { | |
185 | debug("%s: PMIC %d register write failed\n", __func__, | |
186 | MAX77686_REG_PMIC_BUCK2DVS1); | |
187 | return -1; | |
188 | } | |
189 | ||
190 | if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, | |
191 | MAX77686_BUCK2CTRL_ON)) | |
192 | return -1; | |
193 | ||
194 | /* VDD_INT */ | |
195 | if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, | |
196 | MAX77686_BUCK3DVS1_1_0125V)) { | |
197 | debug("%s: PMIC %d register write failed\n", __func__, | |
198 | MAX77686_REG_PMIC_BUCK3DVS1); | |
199 | return -1; | |
200 | } | |
201 | ||
202 | if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, | |
203 | MAX77686_BUCK3CTRL_ON)) | |
204 | return -1; | |
205 | ||
206 | /* VDD_G3D */ | |
207 | if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, | |
208 | MAX77686_BUCK4DVS1_1_2V)) { | |
209 | debug("%s: PMIC %d register write failed\n", __func__, | |
210 | MAX77686_REG_PMIC_BUCK4DVS1); | |
211 | return -1; | |
212 | } | |
213 | ||
214 | if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, | |
215 | MAX77686_BUCK3CTRL_ON)) | |
216 | return -1; | |
217 | ||
218 | /* VDD_LDO2 */ | |
219 | if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, | |
220 | MAX77686_LD02CTRL1_1_5V | EN_LDO)) | |
221 | return -1; | |
222 | ||
223 | /* VDD_LDO3 */ | |
224 | if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, | |
225 | MAX77686_LD03CTRL1_1_8V | EN_LDO)) | |
226 | return -1; | |
227 | ||
228 | /* VDD_LDO5 */ | |
229 | if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, | |
230 | MAX77686_LD05CTRL1_1_8V | EN_LDO)) | |
231 | return -1; | |
232 | ||
233 | /* VDD_LDO10 */ | |
234 | if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, | |
235 | MAX77686_LD10CTRL1_1_8V | EN_LDO)) | |
236 | return -1; | |
237 | ||
238 | return 0; | |
239 | } | |
240 | #endif | |
241 | ||
242 | void dram_init_banksize(void) | |
243 | { | |
244 | int i; | |
245 | u32 addr, size; | |
246 | ||
247 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
248 | addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); | |
249 | size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); | |
250 | ||
251 | gd->bd->bi_dram[i].start = addr; | |
252 | gd->bd->bi_dram[i].size = size; | |
253 | } | |
254 | } | |
255 | ||
256 | static int decode_sromc(const void *blob, struct fdt_sromc *config) | |
257 | { | |
258 | int err; | |
259 | int node; | |
260 | ||
261 | node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); | |
262 | if (node < 0) { | |
263 | debug("Could not find SROMC node\n"); | |
264 | return node; | |
265 | } | |
266 | ||
267 | config->bank = fdtdec_get_int(blob, node, "bank", 0); | |
268 | config->width = fdtdec_get_int(blob, node, "width", 2); | |
269 | ||
270 | err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, | |
271 | FDT_SROM_TIMING_COUNT); | |
272 | if (err < 0) { | |
273 | debug("Could not decode SROMC configuration Error: %s\n", | |
274 | fdt_strerror(err)); | |
275 | return -FDT_ERR_NOTFOUND; | |
276 | } | |
277 | return 0; | |
278 | } | |
279 | ||
280 | int board_eth_init(bd_t *bis) | |
281 | { | |
282 | #ifdef CONFIG_SMC911X | |
283 | u32 smc_bw_conf, smc_bc_conf; | |
284 | struct fdt_sromc config; | |
285 | fdt_addr_t base_addr; | |
286 | int node; | |
287 | ||
288 | node = decode_sromc(gd->fdt_blob, &config); | |
289 | if (node < 0) { | |
290 | debug("%s: Could not find sromc configuration\n", __func__); | |
291 | return 0; | |
292 | } | |
293 | node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); | |
294 | if (node < 0) { | |
295 | debug("%s: Could not find lan9215 configuration\n", __func__); | |
296 | return 0; | |
297 | } | |
298 | ||
299 | /* We now have a node, so any problems from now on are errors */ | |
300 | base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); | |
301 | if (base_addr == FDT_ADDR_T_NONE) { | |
302 | debug("%s: Could not find lan9215 address\n", __func__); | |
303 | return -1; | |
304 | } | |
305 | ||
306 | /* Ethernet needs data bus width of 16 bits */ | |
307 | if (config.width != 2) { | |
308 | debug("%s: Unsupported bus width %d\n", __func__, | |
309 | config.width); | |
310 | return -1; | |
311 | } | |
312 | smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) | |
313 | | SROMC_BYTE_ENABLE(config.bank); | |
314 | ||
315 | smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | | |
316 | SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | | |
317 | SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | | |
318 | SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | | |
319 | SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | | |
320 | SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | | |
321 | SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); | |
322 | ||
323 | /* Select and configure the SROMC bank */ | |
324 | exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); | |
325 | s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); | |
326 | return smc911x_initialize(0, base_addr); | |
327 | #endif | |
328 | return 0; | |
329 | } | |
330 | ||
331 | #ifdef CONFIG_DISPLAY_BOARDINFO | |
332 | int checkboard(void) | |
333 | { | |
334 | const char *board_name; | |
335 | ||
336 | board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); | |
337 | if (board_name == NULL) | |
338 | printf("\nUnknown Board\n"); | |
339 | else | |
340 | printf("\nBoard: %s\n", board_name); | |
341 | ||
342 | return 0; | |
343 | } | |
344 | #endif | |
345 | ||
346 | #ifdef CONFIG_GENERIC_MMC | |
347 | int board_mmc_init(bd_t *bis) | |
348 | { | |
349 | int ret; | |
350 | /* dwmmc initializattion for available channels */ | |
351 | ret = exynos_dwmmc_init(gd->fdt_blob); | |
352 | if (ret) | |
353 | debug("dwmmc init failed\n"); | |
354 | ||
355 | return ret; | |
356 | } | |
357 | #endif | |
358 | ||
359 | static int board_uart_init(void) | |
360 | { | |
361 | int err, uart_id, ret = 0; | |
362 | ||
363 | for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { | |
364 | err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); | |
365 | if (err) { | |
366 | debug("UART%d not configured\n", | |
367 | (uart_id - PERIPH_ID_UART0)); | |
368 | ret |= err; | |
369 | } | |
370 | } | |
371 | return ret; | |
372 | } | |
373 | ||
374 | #ifdef CONFIG_BOARD_EARLY_INIT_F | |
375 | int board_early_init_f(void) | |
376 | { | |
377 | int err; | |
378 | err = board_uart_init(); | |
379 | if (err) { | |
380 | debug("UART init failed\n"); | |
381 | return err; | |
382 | } | |
383 | #ifdef CONFIG_SYS_I2C_INIT_BOARD | |
384 | board_i2c_init(gd->fdt_blob); | |
385 | #endif | |
386 | return err; | |
387 | } | |
388 | #endif | |
389 | ||
390 | #ifdef CONFIG_LCD | |
391 | void exynos_cfg_lcd_gpio(void) | |
392 | { | |
393 | struct exynos5_gpio_part1 *gpio1 = | |
394 | (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1(); | |
395 | ||
396 | /* For Backlight */ | |
397 | s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT); | |
398 | s5p_gpio_set_value(&gpio1->b2, 0, 1); | |
399 | ||
400 | /* LCD power on */ | |
401 | s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT); | |
402 | s5p_gpio_set_value(&gpio1->x1, 5, 1); | |
403 | ||
404 | /* Set Hotplug detect for DP */ | |
405 | s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); | |
406 | } | |
407 | ||
408 | void exynos_set_dp_phy(unsigned int onoff) | |
409 | { | |
410 | set_dp_phy_ctrl(onoff); | |
411 | } | |
412 | #endif | |
eb28fdac HT |
413 | |
414 | #ifdef CONFIG_BOARD_LATE_INIT | |
415 | int board_late_init(void) | |
416 | { | |
417 | stdio_print_current_devices(); | |
418 | ||
419 | if (local.cros_ec_err) { | |
420 | /* Force console on */ | |
421 | gd->flags &= ~GD_FLG_SILENT; | |
422 | ||
423 | printf("cros-ec communications failure %d\n", | |
424 | local.cros_ec_err); | |
425 | puts("\nPlease reset with Power+Refresh\n\n"); | |
426 | panic("Cannot init cros-ec device"); | |
427 | return -1; | |
428 | } | |
429 | return 0; | |
430 | } | |
431 | #endif |