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89f95492 HK |
1 | /* |
2 | * Machine Specific Values for TRATS board based on EXYNOS4210 | |
3 | * | |
4 | * Copyright (C) 2011 Samsung Electronics | |
5 | * Heungjun Kim <riverful.kim@samsung.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
89f95492 HK |
8 | */ |
9 | ||
10 | #ifndef _TRATS_SETUP_H | |
11 | #define _TRATS_SETUP_H | |
12 | ||
13 | #include <config.h> | |
14 | #include <version.h> | |
15 | #include <asm/arch/cpu.h> | |
16 | ||
17 | /* CLK_SRC_CPU: APLL(1), MPLL(1), CORE(0), HPM(0) */ | |
18 | #define MUX_HPM_SEL_MOUTAPLL 0x0 | |
19 | #define MUX_HPM_SEL_SCLKMPLL 0x1 | |
20 | #define MUX_CORE_SEL_MOUTAPLL 0x0 | |
21 | #define MUX_CORE_SEL_SCLKMPLL 0x1 | |
22 | #define MUX_MPLL_SEL_FILPLL 0x0 | |
23 | #define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1 | |
24 | #define MUX_APLL_SEL_FILPLL 0x0 | |
25 | #define MUX_APLL_SEL_MOUTMPLLFOUT 0x1 | |
26 | #define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \ | |
27 | | (MUX_CORE_SEL_MOUTAPLL << 16) \ | |
28 | | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\ | |
29 | | (MUX_APLL_SEL_MOUTMPLLFOUT << 0)) | |
30 | ||
31 | /* CLK_DIV_CPU0 */ | |
32 | #define APLL_RATIO 0x0 | |
33 | #define PCLK_DBG_RATIO 0x1 | |
34 | #define ATB_RATIO 0x3 | |
35 | #define PERIPH_RATIO 0x3 | |
36 | #define COREM1_RATIO 0x7 | |
37 | #define COREM0_RATIO 0x3 | |
38 | #define CORE_RATIO 0x0 | |
39 | #define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ | |
40 | | (PCLK_DBG_RATIO << 20) \ | |
41 | | (ATB_RATIO << 16) \ | |
42 | | (PERIPH_RATIO << 12) \ | |
43 | | (COREM1_RATIO << 8) \ | |
44 | | (COREM0_RATIO << 4) \ | |
45 | | (CORE_RATIO << 0)) | |
46 | ||
47 | /* CLK_DIV_CPU1 */ | |
48 | #define HPM_RATIO 0x0 | |
49 | #define COPY_RATIO 0x3 | |
50 | #define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) | |
51 | ||
52 | /* CLK_DIV_DMC0 */ | |
53 | #define CORE_TIMERS_RATIO 0x1 | |
54 | #define COPY2_RATIO 0x3 | |
55 | #define DMCP_RATIO 0x1 | |
56 | #define DMCD_RATIO 0x1 | |
57 | #define DMC_RATIO 0x1 | |
58 | #define DPHY_RATIO 0x1 | |
59 | #define ACP_PCLK_RATIO 0x1 | |
60 | #define ACP_RATIO 0x3 | |
61 | #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ | |
62 | | (COPY2_RATIO << 24) \ | |
63 | | (DMCP_RATIO << 20) \ | |
64 | | (DMCD_RATIO << 16) \ | |
65 | | (DMC_RATIO << 12) \ | |
66 | | (DPHY_RATIO << 8) \ | |
67 | | (ACP_PCLK_RATIO << 4) \ | |
68 | | (ACP_RATIO << 0)) | |
69 | ||
70 | /* CLK_DIV_DMC1 */ | |
71 | #define DPM_RATIO 0x1 | |
72 | #define DVSEM_RATIO 0x1 | |
73 | #define PWI_RATIO 0x1 | |
74 | #define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ | |
75 | | (DVSEM_RATIO << 16) \ | |
76 | | (PWI_RATIO << 8)) | |
77 | ||
78 | /* CLK_SRC_TOP0 */ | |
79 | #define MUX_ONENAND_SEL_ACLK_133 0x0 | |
80 | #define MUX_ONENAND_SEL_ACLK_160 0x1 | |
81 | #define MUX_ACLK_133_SEL_SCLKMPLL 0x0 | |
82 | #define MUX_ACLK_133_SEL_SCLKAPLL 0x1 | |
83 | #define MUX_ACLK_160_SEL_SCLKMPLL 0x0 | |
84 | #define MUX_ACLK_160_SEL_SCLKAPLL 0x1 | |
85 | #define MUX_ACLK_100_SEL_SCLKMPLL 0x0 | |
86 | #define MUX_ACLK_100_SEL_SCLKAPLL 0x1 | |
87 | #define MUX_ACLK_200_SEL_SCLKMPLL 0x0 | |
88 | #define MUX_ACLK_200_SEL_SCLKAPLL 0x1 | |
89 | #define MUX_VPLL_SEL_FINPLL 0x0 | |
90 | #define MUX_VPLL_SEL_FOUTVPLL 0x1 | |
91 | #define MUX_EPLL_SEL_FINPLL 0x0 | |
92 | #define MUX_EPLL_SEL_FOUTEPLL 0x1 | |
93 | #define MUX_ONENAND_1_SEL_MOUTONENAND 0x0 | |
94 | #define MUX_ONENAND_1_SEL_SCLKVPLL 0x1 | |
95 | #define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \ | |
96 | | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \ | |
97 | | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \ | |
98 | | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \ | |
99 | | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \ | |
100 | | (MUX_VPLL_SEL_FOUTVPLL << 8) \ | |
101 | | (MUX_EPLL_SEL_FOUTEPLL << 4) \ | |
102 | | (MUX_ONENAND_1_SEL_MOUTONENAND << 0)) | |
103 | ||
104 | /* CLK_DIV_TOP */ | |
105 | #define ONENAND_RATIO 0x0 | |
106 | #define ACLK_133_RATIO 0x5 | |
107 | #define ACLK_160_RATIO 0x4 | |
108 | #define ACLK_100_RATIO 0x7 | |
109 | #define ACLK_200_RATIO 0x3 | |
110 | #define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \ | |
111 | | (ACLK_133_RATIO << 12)\ | |
112 | | (ACLK_160_RATIO << 8) \ | |
113 | | (ACLK_100_RATIO << 4) \ | |
114 | | (ACLK_200_RATIO << 0)) | |
115 | ||
116 | /* CLK_DIV_LEFTBUS */ | |
117 | #define GPL_RATIO 0x1 | |
118 | #define GDL_RATIO 0x3 | |
119 | #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) | |
120 | ||
121 | /* CLK_DIV_RIGHTBUS */ | |
122 | #define GPR_RATIO 0x1 | |
123 | #define GDR_RATIO 0x3 | |
124 | #define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) | |
125 | ||
126 | /* CLK_SRS_FSYS: 6 = SCLKMPLL */ | |
127 | #define SATA_SEL_SCLKMPLL 0 | |
128 | #define SATA_SEL_SCLKAPLL 1 | |
129 | ||
130 | #define MMC_SEL_XXTI 0 | |
131 | #define MMC_SEL_XUSBXTI 1 | |
132 | #define MMC_SEL_SCLK_HDMI24M 2 | |
133 | #define MMC_SEL_SCLK_USBPHY0 3 | |
134 | #define MMC_SEL_SCLK_USBPHY1 4 | |
135 | #define MMC_SEL_SCLK_HDMIPHY 5 | |
136 | #define MMC_SEL_SCLKMPLL 6 | |
137 | #define MMC_SEL_SCLKEPLL 7 | |
138 | #define MMC_SEL_SCLKVPLL 8 | |
139 | ||
140 | #define MMCC0_SEL MMC_SEL_SCLKMPLL | |
141 | #define MMCC1_SEL MMC_SEL_SCLKMPLL | |
142 | #define MMCC2_SEL MMC_SEL_SCLKMPLL | |
143 | #define MMCC3_SEL MMC_SEL_SCLKMPLL | |
144 | #define MMCC4_SEL MMC_SEL_SCLKMPLL | |
145 | #define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \ | |
146 | | (MMCC4_SEL << 16) \ | |
147 | | (MMCC3_SEL << 12) \ | |
148 | | (MMCC2_SEL << 8) \ | |
149 | | (MMCC1_SEL << 4) \ | |
150 | | (MMCC0_SEL << 0)) | |
151 | ||
152 | /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */ | |
153 | /* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */ | |
154 | #define MMC0_RATIO 0xF | |
155 | #define MMC0_PRE_RATIO 0x0 | |
156 | #define MMC1_RATIO 0xF | |
157 | #define MMC1_PRE_RATIO 0x0 | |
158 | #define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ | |
159 | | (MMC1_RATIO << 16) \ | |
160 | | (MMC0_PRE_RATIO << 8) \ | |
161 | | (MMC0_RATIO << 0)) | |
162 | ||
163 | /* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */ | |
164 | #define MMC2_RATIO 0xF | |
165 | #define MMC2_PRE_RATIO 0x0 | |
166 | #define MMC3_RATIO 0xF | |
167 | #define MMC3_PRE_RATIO 0x0 | |
168 | #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ | |
169 | | (MMC3_RATIO << 16) \ | |
170 | | (MMC2_PRE_RATIO << 8) \ | |
171 | | (MMC2_RATIO << 0)) | |
172 | ||
173 | /* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */ | |
174 | #define MMC4_RATIO 0xF | |
175 | #define MMC4_PRE_RATIO 0x0 | |
176 | #define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ | |
177 | | (MMC4_RATIO << 0)) | |
178 | ||
179 | /* CLK_SRC_PERIL0 */ | |
180 | #define UART_SEL_XXTI 0 | |
181 | #define UART_SEL_XUSBXTI 1 | |
182 | #define UART_SEL_SCLK_HDMI24M 2 | |
183 | #define UART_SEL_SCLK_USBPHY0 3 | |
184 | #define UART_SEL_SCLK_USBPHY1 4 | |
185 | #define UART_SEL_SCLK_HDMIPHY 5 | |
186 | #define UART_SEL_SCLKMPLL 6 | |
187 | #define UART_SEL_SCLKEPLL 7 | |
188 | #define UART_SEL_SCLKVPLL 8 | |
189 | ||
190 | #define UART0_SEL UART_SEL_SCLKMPLL | |
191 | #define UART1_SEL UART_SEL_SCLKMPLL | |
192 | #define UART2_SEL UART_SEL_SCLKMPLL | |
193 | #define UART3_SEL UART_SEL_SCLKMPLL | |
194 | #define UART4_SEL UART_SEL_SCLKMPLL | |
195 | #define UART5_SEL UART_SEL_SCLKMPLL | |
196 | #define CLK_SRC_PERIL0_VAL ((UART5_SEL << 16) \ | |
197 | | (UART4_SEL << 12) \ | |
198 | | (UART3_SEL << 12) \ | |
199 | | (UART2_SEL << 8) \ | |
200 | | (UART1_SEL << 4) \ | |
201 | | (UART0_SEL << 0)) | |
202 | ||
203 | /* SCLK_UART[0-4] = MOUTUART[0-4] / (UART[0-4]_RATIO + 1) */ | |
204 | /* CLK_DIV_PERIL0 */ | |
205 | #define UART0_RATIO 7 | |
206 | #define UART1_RATIO 7 | |
207 | #define UART2_RATIO 7 | |
208 | #define UART3_RATIO 4 | |
209 | #define UART4_RATIO 7 | |
210 | #define UART5_RATIO 7 | |
211 | #define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 16) \ | |
212 | | (UART4_RATIO << 12) \ | |
213 | | (UART3_RATIO << 12) \ | |
214 | | (UART2_RATIO << 8) \ | |
215 | | (UART1_RATIO << 4) \ | |
216 | | (UART0_RATIO << 0)) | |
217 | ||
218 | /* CLK_DIV_PERIL3 */ | |
219 | #define SLIMBUS_RATIO 0x0 | |
220 | #define PWM_RATIO 0x8 | |
221 | #define CLK_DIV_PERIL3_VAL ((SLIMBUS_RATIO << 4) \ | |
222 | | (PWM_RATIO << 0)) | |
223 | ||
224 | /* Required period to generate a stable clock output */ | |
225 | /* PLL_LOCK_TIME */ | |
226 | #define PLL_LOCKTIME 0x1C20 | |
227 | ||
228 | /* PLL Values */ | |
229 | #define DISABLE 0 | |
230 | #define ENABLE 1 | |
231 | #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ | |
232 | | (mdiv << 16) \ | |
233 | | (pdiv << 8) \ | |
234 | | (sdiv << 0)) | |
235 | ||
236 | /* APLL_CON0: 800MHz */ | |
237 | #define APLL_MDIV 0xC8 | |
238 | #define APLL_PDIV 0x6 | |
239 | #define APLL_SDIV 0x1 | |
240 | #define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV) | |
241 | ||
242 | /* APLL_CON1 */ | |
243 | #define APLL_AFC_ENB 0x1 | |
244 | #define APLL_AFC 0x1C | |
245 | #define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0)) | |
246 | ||
247 | /* MPLL_CON0: 800MHz */ | |
248 | #define MPLL_MDIV 0xC8 | |
249 | #define MPLL_PDIV 0x6 | |
250 | #define MPLL_SDIV 0x1 | |
251 | #define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) | |
252 | ||
253 | /* MPLL_CON1 */ | |
254 | #define MPLL_AFC_ENB 0x1 | |
255 | #define MPLL_AFC 0x1C | |
256 | #define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) | |
257 | ||
258 | /* EPLL_CON0: 96MHz */ | |
259 | #define EPLL_MDIV 0x30 | |
260 | #define EPLL_PDIV 0x3 | |
261 | #define EPLL_SDIV 0x2 | |
262 | #define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) | |
263 | ||
264 | /* EPLL_CON1 */ | |
265 | #define EPLL_K 0x0 | |
266 | #define EPLL_CON1_VAL (EPLL_K >> 0) | |
267 | ||
268 | /* VPLL_CON0: 108MHz */ | |
269 | #define VPLL_MDIV 0x35 | |
270 | #define VPLL_PDIV 0x3 | |
271 | #define VPLL_SDIV 0x2 | |
272 | #define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) | |
273 | ||
274 | /* VPLL_CON1 */ | |
275 | #define VPLL_SSCG_EN DISABLE | |
276 | #define VPLL_SEL_PF_DN_SPREAD 0x0 | |
277 | #define VPLL_MRR 0x11 | |
278 | #define VPLL_MFR 0x0 | |
279 | #define VPLL_K 0x400 | |
280 | #define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\ | |
281 | | (VPLL_SEL_PF_DN_SPREAD << 29) \ | |
282 | | (VPLL_MRR << 24) \ | |
283 | | (VPLL_MFR << 16) \ | |
284 | | (VPLL_K << 0)) | |
285 | ||
286 | /* CLOCK GATE */ | |
287 | #define CLK_DIS 0x0 | |
288 | #define CLK_EN 0x1 | |
289 | ||
290 | #define BIT_CAM_CLK_PIXELASYNCM1 18 | |
291 | #define BIT_CAM_CLK_PIXELASYNCM0 17 | |
292 | #define BIT_CAM_CLK_PPMUCAMIF 16 | |
293 | #define BIT_CAM_CLK_QEFIMC3 15 | |
294 | #define BIT_CAM_CLK_QEFIMC2 14 | |
295 | #define BIT_CAM_CLK_QEFIMC1 13 | |
296 | #define BIT_CAM_CLK_QEFIMC0 12 | |
297 | #define BIT_CAM_CLK_SMMUJPEG 11 | |
298 | #define BIT_CAM_CLK_SMMUFIMC3 10 | |
299 | #define BIT_CAM_CLK_SMMUFIMC2 9 | |
300 | #define BIT_CAM_CLK_SMMUFIMC1 8 | |
301 | #define BIT_CAM_CLK_SMMUFIMC0 7 | |
302 | #define BIT_CAM_CLK_JPEG 6 | |
303 | #define BIT_CAM_CLK_CSIS1 5 | |
304 | #define BIT_CAM_CLK_CSIS0 4 | |
305 | #define BIT_CAM_CLK_FIMC3 3 | |
306 | #define BIT_CAM_CLK_FIMC2 2 | |
307 | #define BIT_CAM_CLK_FIMC1 1 | |
308 | #define BIT_CAM_CLK_FIMC0 0 | |
309 | #define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\ | |
310 | | (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\ | |
311 | | (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\ | |
312 | | (CLK_EN << BIT_CAM_CLK_QEFIMC3)\ | |
313 | | (CLK_EN << BIT_CAM_CLK_QEFIMC2)\ | |
314 | | (CLK_EN << BIT_CAM_CLK_QEFIMC1)\ | |
315 | | (CLK_EN << BIT_CAM_CLK_QEFIMC0)\ | |
316 | | (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\ | |
317 | | (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\ | |
318 | | (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\ | |
319 | | (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\ | |
320 | | (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\ | |
321 | | (CLK_EN << BIT_CAM_CLK_JPEG)\ | |
322 | | (CLK_EN << BIT_CAM_CLK_CSIS1)\ | |
323 | | (CLK_EN << BIT_CAM_CLK_CSIS0)\ | |
324 | | (CLK_EN << BIT_CAM_CLK_FIMC3)\ | |
325 | | (CLK_EN << BIT_CAM_CLK_FIMC2)\ | |
326 | | (CLK_EN << BIT_CAM_CLK_FIMC1)\ | |
327 | | (CLK_EN << BIT_CAM_CLK_FIMC0)) | |
328 | #define CLK_GATE_IP_CAM_ALL_DIS ~CLK_GATE_IP_CAM_ALL_EN | |
329 | ||
330 | #define BIT_VP_CLK_PPMUTV 5 | |
331 | #define BIT_VP_CLK_SMMUTV 4 | |
332 | #define BIT_VP_CLK_HDMI 3 | |
333 | #define BIT_VP_CLK_TVENC 2 | |
334 | #define BIT_VP_CLK_MIXER 1 | |
335 | #define BIT_VP_CLK_VP 0 | |
336 | #define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\ | |
337 | | (CLK_EN << BIT_VP_CLK_SMMUTV)\ | |
338 | | (CLK_EN << BIT_VP_CLK_HDMI)\ | |
339 | | (CLK_EN << BIT_VP_CLK_TVENC)\ | |
340 | | (CLK_EN << BIT_VP_CLK_MIXER)\ | |
341 | | (CLK_EN << BIT_VP_CLK_VP)) | |
342 | #define CLK_GATE_IP_VP_ALL_DIS ~CLK_GATE_IP_VP_ALL_EN | |
343 | ||
344 | #define BIT_MFC_CLK_PPMUMFC_R 4 | |
345 | #define BIT_MFC_CLK_PPMUMFC_L 3 | |
346 | #define BIT_MFC_CLK_SMMUMFC_R 2 | |
347 | #define BIT_MFC_CLK_SMMUMFC_L 1 | |
348 | #define BIT_MFC_CLK_MFC 0 | |
349 | #define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\ | |
350 | | (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\ | |
351 | | (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\ | |
352 | | (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\ | |
353 | | (CLK_EN << BIT_MFC_CLK_MFC)) | |
354 | #define CLK_GATE_IP_MFC_ALL_DIS ~CLK_GATE_IP_MFC_ALL_EN | |
355 | ||
356 | #define BIT_G3D_CLK_QEG3D 2 | |
357 | #define BIT_G3D_CLK_PPMUG3D 1 | |
358 | #define BIT_G3D_CLK_G3D 0 | |
359 | #define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\ | |
360 | | (CLK_EN << BIT_G3D_CLK_PPMUG3D)\ | |
361 | | (CLK_EN << BIT_G3D_CLK_G3D)) | |
362 | #define CLK_GATE_IP_G3D_ALL_DIS ~CLK_GATE_IP_G3D_ALL_EN | |
363 | ||
364 | #define BIT_IMAGE_CLK_PPMUIMAGE 9 | |
365 | #define BIT_IMAGE_CLK_QEMDMA 8 | |
366 | #define BIT_IMAGE_CLK_QEROTATOR 7 | |
367 | #define BIT_IMAGE_CLK_QEG2D 6 | |
368 | #define BIT_IMAGE_CLK_SMMUMDMA 5 | |
369 | #define BIT_IMAGE_CLK_SMMUROTATOR 4 | |
370 | #define BIT_IMAGE_CLK_SMMUG2D 3 | |
371 | #define BIT_IMAGE_CLK_MDMA 2 | |
372 | #define BIT_IMAGE_CLK_ROTATOR 1 | |
373 | #define BIT_IMAGE_CLK_G2D 0 | |
374 | #define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\ | |
375 | | (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\ | |
376 | | (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\ | |
377 | | (CLK_EN << BIT_IMAGE_CLK_QEG2D)\ | |
378 | | (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\ | |
379 | | (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\ | |
380 | | (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\ | |
381 | | (CLK_EN << BIT_IMAGE_CLK_MDMA)\ | |
382 | | (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\ | |
383 | | (CLK_EN << BIT_IMAGE_CLK_G2D)) | |
384 | #define CLK_GATE_IP_IMAGE_ALL_DIS ~CLK_GATE_IP_IMAGE_ALL_EN | |
385 | ||
386 | #define BIT_LCD0_CLK_PPMULCD0 5 | |
387 | #define BIT_LCD0_CLK_SMMUFIMD0 4 | |
388 | #define BIT_LCD0_CLK_DSIM0 3 | |
389 | #define BIT_LCD0_CLK_MDNIE0 2 | |
390 | #define BIT_LCD0_CLK_MIE0 1 | |
391 | #define BIT_LCD0_CLK_FIMD0 0 | |
392 | #define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\ | |
393 | | (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\ | |
394 | | (CLK_EN << BIT_LCD0_CLK_DSIM0)\ | |
395 | | (CLK_EN << BIT_LCD0_CLK_MDNIE0)\ | |
396 | | (CLK_EN << BIT_LCD0_CLK_MIE0)\ | |
397 | | (CLK_EN << BIT_LCD0_CLK_FIMD0)) | |
398 | #define CLK_GATE_IP_LCD0_ALL_DIS ~CLK_GATE_IP_LCD0_ALL_EN | |
399 | ||
400 | #define BIT_LCD1_CLK_PPMULCD1 5 | |
401 | #define BIT_LCD1_CLK_SMMUFIMD1 4 | |
402 | #define BIT_LCD1_CLK_DSIM1 3 | |
403 | #define BIT_LCD1_CLK_MDNIE1 2 | |
404 | #define BIT_LCD1_CLK_MIE1 1 | |
405 | #define BIT_LCD1_CLK_FIMD1 0 | |
406 | #define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\ | |
407 | | (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\ | |
408 | | (CLK_EN << BIT_LCD1_CLK_DSIM1)\ | |
409 | | (CLK_EN << BIT_LCD1_CLK_MDNIE1)\ | |
410 | | (CLK_EN << BIT_LCD1_CLK_MIE1)\ | |
411 | | (CLK_EN << BIT_LCD1_CLK_FIMD1)) | |
412 | #define CLK_GATE_IP_LCD1_ALL_DIS ~CLK_GATE_IP_LCD1_ALL_EN | |
413 | ||
414 | #define BIT_FSYS_CLK_SMMUPCIE 18 | |
415 | #define BIT_FSYS_CLK_PPMUFILE 17 | |
416 | #define BIT_FSYS_CLK_NFCON 16 | |
417 | #define BIT_FSYS_CLK_ONENAND 15 | |
418 | #define BIT_FSYS_CLK_PCIE 14 | |
419 | #define BIT_FSYS_CLK_USBDEVICE 13 | |
420 | #define BIT_FSYS_CLK_USBHOST 12 | |
421 | #define BIT_FSYS_CLK_SROMC 11 | |
422 | #define BIT_FSYS_CLK_SATA 10 | |
423 | #define BIT_FSYS_CLK_SDMMC4 9 | |
424 | #define BIT_FSYS_CLK_SDMMC3 8 | |
425 | #define BIT_FSYS_CLK_SDMMC2 7 | |
426 | #define BIT_FSYS_CLK_SDMMC1 6 | |
427 | #define BIT_FSYS_CLK_SDMMC0 5 | |
428 | #define BIT_FSYS_CLK_TSI 4 | |
429 | #define BIT_FSYS_CLK_SATAPHY 3 | |
430 | #define BIT_FSYS_CLK_PCIEPHY 2 | |
431 | #define BIT_FSYS_CLK_PDMA1 1 | |
432 | #define BIT_FSYS_CLK_PDMA0 0 | |
433 | #define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\ | |
434 | | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\ | |
435 | | (CLK_EN << BIT_FSYS_CLK_NFCON)\ | |
436 | | (CLK_EN << BIT_FSYS_CLK_ONENAND)\ | |
437 | | (CLK_EN << BIT_FSYS_CLK_PCIE)\ | |
438 | | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\ | |
439 | | (CLK_EN << BIT_FSYS_CLK_USBHOST)\ | |
440 | | (CLK_EN << BIT_FSYS_CLK_SROMC)\ | |
441 | | (CLK_EN << BIT_FSYS_CLK_SATA)\ | |
442 | | (CLK_EN << BIT_FSYS_CLK_SDMMC4)\ | |
443 | | (CLK_EN << BIT_FSYS_CLK_SDMMC3)\ | |
444 | | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\ | |
445 | | (CLK_EN << BIT_FSYS_CLK_SDMMC1)\ | |
446 | | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\ | |
447 | | (CLK_EN << BIT_FSYS_CLK_TSI)\ | |
448 | | (CLK_EN << BIT_FSYS_CLK_SATAPHY)\ | |
449 | | (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\ | |
450 | | (CLK_EN << BIT_FSYS_CLK_PDMA1)\ | |
451 | | (CLK_EN << BIT_FSYS_CLK_PDMA0)) | |
452 | #define CLK_GATE_IP_FSYS_ALL_DIS ~CLK_GATE_IP_FSYS_ALL_EN | |
453 | ||
454 | #define BIT_GPS_CLK_SMMUGPS 1 | |
455 | #define BIT_GPS_CLK_GPS 0 | |
456 | #define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\ | |
457 | | (CLK_EN << BIT_GPS_CLK_GPS)) | |
458 | #define CLK_GATE_IP_GPS_ALL_DIS ~CLK_GATE_IP_GPS_ALL_EN | |
459 | ||
460 | #define BIT_PERIL_CLK_MODEMIF 28 | |
461 | #define BIT_PERIL_CLK_AC97 27 | |
462 | #define BIT_PERIL_CLK_SPDIF 26 | |
463 | #define BIT_PERIL_CLK_SLIMBUS 25 | |
464 | #define BIT_PERIL_CLK_PWM 24 | |
465 | #define BIT_PERIL_CLK_PCM2 23 | |
466 | #define BIT_PERIL_CLK_PCM1 22 | |
467 | #define BIT_PERIL_CLK_I2S2 21 | |
468 | #define BIT_PERIL_CLK_I2S1 20 | |
469 | #define BIT_PERIL_CLK_RESERVED0 19 | |
470 | #define BIT_PERIL_CLK_SPI2 18 | |
471 | #define BIT_PERIL_CLK_SPI1 17 | |
472 | #define BIT_PERIL_CLK_SPI0 16 | |
473 | #define BIT_PERIL_CLK_TSADC 15 | |
474 | #define BIT_PERIL_CLK_I2CHDMI 14 | |
475 | #define BIT_PERIL_CLK_I2C7 13 | |
476 | #define BIT_PERIL_CLK_I2C6 12 | |
477 | #define BIT_PERIL_CLK_I2C5 11 | |
478 | #define BIT_PERIL_CLK_I2C4 10 | |
479 | #define BIT_PERIL_CLK_I2C3 9 | |
480 | #define BIT_PERIL_CLK_I2C2 8 | |
481 | #define BIT_PERIL_CLK_I2C1 7 | |
482 | #define BIT_PERIL_CLK_I2C0 6 | |
483 | #define BIT_PERIL_CLK_RESERVED1 5 | |
484 | #define BIT_PERIL_CLK_UART4 4 | |
485 | #define BIT_PERIL_CLK_UART3 3 | |
486 | #define BIT_PERIL_CLK_UART2 2 | |
487 | #define BIT_PERIL_CLK_UART1 1 | |
488 | #define BIT_PERIL_CLK_UART0 0 | |
489 | #define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\ | |
490 | | (CLK_EN << BIT_PERIL_CLK_AC97)\ | |
491 | | (CLK_EN << BIT_PERIL_CLK_SPDIF)\ | |
492 | | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\ | |
493 | | (CLK_EN << BIT_PERIL_CLK_PWM)\ | |
494 | | (CLK_EN << BIT_PERIL_CLK_PCM2)\ | |
495 | | (CLK_EN << BIT_PERIL_CLK_PCM1)\ | |
496 | | (CLK_EN << BIT_PERIL_CLK_I2S2)\ | |
497 | | (CLK_EN << BIT_PERIL_CLK_I2S1)\ | |
498 | | (CLK_EN << BIT_PERIL_CLK_RESERVED0)\ | |
499 | | (CLK_EN << BIT_PERIL_CLK_SPI2)\ | |
500 | | (CLK_EN << BIT_PERIL_CLK_SPI1)\ | |
501 | | (CLK_EN << BIT_PERIL_CLK_SPI0)\ | |
502 | | (CLK_EN << BIT_PERIL_CLK_TSADC)\ | |
503 | | (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\ | |
504 | | (CLK_EN << BIT_PERIL_CLK_I2C7)\ | |
505 | | (CLK_EN << BIT_PERIL_CLK_I2C6)\ | |
506 | | (CLK_EN << BIT_PERIL_CLK_I2C5)\ | |
507 | | (CLK_EN << BIT_PERIL_CLK_I2C4)\ | |
508 | | (CLK_EN << BIT_PERIL_CLK_I2C3)\ | |
509 | | (CLK_EN << BIT_PERIL_CLK_I2C2)\ | |
510 | | (CLK_EN << BIT_PERIL_CLK_I2C1)\ | |
511 | | (CLK_EN << BIT_PERIL_CLK_I2C0)\ | |
512 | | (CLK_EN << BIT_PERIL_CLK_RESERVED1)\ | |
513 | | (CLK_EN << BIT_PERIL_CLK_UART4)\ | |
514 | | (CLK_EN << BIT_PERIL_CLK_UART3)\ | |
515 | | (CLK_EN << BIT_PERIL_CLK_UART2)\ | |
516 | | (CLK_EN << BIT_PERIL_CLK_UART1)\ | |
517 | | (CLK_EN << BIT_PERIL_CLK_UART0)) | |
518 | #define CLK_GATE_IP_PERIL_ALL_DIS ~CLK_GATE_IP_PERIL_ALL_EN | |
519 | ||
520 | #define BIT_PERIR_CLK_TMU_APBIF 17 | |
521 | #define BIT_PERIR_CLK_KEYIF 16 | |
522 | #define BIT_PERIR_CLK_RTC 15 | |
523 | #define BIT_PERIR_CLK_WDT 14 | |
524 | #define BIT_PERIR_CLK_MCT 13 | |
525 | #define BIT_PERIR_CLK_SECKEY 12 | |
526 | #define BIT_PERIR_CLK_HDMI_CEC 11 | |
527 | #define BIT_PERIR_CLK_TZPC5 10 | |
528 | #define BIT_PERIR_CLK_TZPC4 9 | |
529 | #define BIT_PERIR_CLK_TZPC3 8 | |
530 | #define BIT_PERIR_CLK_TZPC2 7 | |
531 | #define BIT_PERIR_CLK_TZPC1 6 | |
532 | #define BIT_PERIR_CLK_TZPC0 5 | |
533 | #define BIT_PERIR_CLK_CMU_DMCPART 4 | |
534 | #define BIT_PERIR_CLK_RESERVED 3 | |
535 | #define BIT_PERIR_CLK_CMU_APBIF 2 | |
536 | #define BIT_PERIR_CLK_SYSREG 1 | |
537 | #define BIT_PERIR_CLK_CHIP_ID 0 | |
538 | #define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\ | |
539 | | (CLK_EN << BIT_PERIR_CLK_KEYIF)\ | |
540 | | (CLK_EN << BIT_PERIR_CLK_RTC)\ | |
541 | | (CLK_EN << BIT_PERIR_CLK_WDT)\ | |
542 | | (CLK_EN << BIT_PERIR_CLK_MCT)\ | |
543 | | (CLK_EN << BIT_PERIR_CLK_SECKEY)\ | |
544 | | (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\ | |
545 | | (CLK_EN << BIT_PERIR_CLK_TZPC5)\ | |
546 | | (CLK_EN << BIT_PERIR_CLK_TZPC4)\ | |
547 | | (CLK_EN << BIT_PERIR_CLK_TZPC3)\ | |
548 | | (CLK_EN << BIT_PERIR_CLK_TZPC2)\ | |
549 | | (CLK_EN << BIT_PERIR_CLK_TZPC1)\ | |
550 | | (CLK_EN << BIT_PERIR_CLK_TZPC0)\ | |
551 | | (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\ | |
552 | | (CLK_EN << BIT_PERIR_CLK_RESERVED)\ | |
553 | | (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\ | |
554 | | (CLK_EN << BIT_PERIR_CLK_SYSREG)\ | |
555 | | (CLK_EN << BIT_PERIR_CLK_CHIP_ID)) | |
556 | #define CLK_GATE_IP_PERIR_ALL_DIS ~CLK_GATE_IP_PERIR_ALL_EN | |
557 | ||
558 | #define BIT_BLOCK_CLK_GPS 7 | |
559 | #define BIT_BLOCK_CLK_RESERVED 6 | |
560 | #define BIT_BLOCK_CLK_LCD1 5 | |
561 | #define BIT_BLOCK_CLK_LCD0 4 | |
562 | #define BIT_BLOCK_CLK_G3D 3 | |
563 | #define BIT_BLOCK_CLK_MFC 2 | |
564 | #define BIT_BLOCK_CLK_TV 1 | |
565 | #define BIT_BLOCK_CLK_CAM 0 | |
566 | #define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\ | |
567 | | (CLK_EN << BIT_BLOCK_CLK_RESERVED)\ | |
568 | | (CLK_EN << BIT_BLOCK_CLK_LCD1)\ | |
569 | | (CLK_EN << BIT_BLOCK_CLK_LCD0)\ | |
570 | | (CLK_EN << BIT_BLOCK_CLK_G3D)\ | |
571 | | (CLK_EN << BIT_BLOCK_CLK_MFC)\ | |
572 | | (CLK_EN << BIT_BLOCK_CLK_TV)\ | |
573 | | (CLK_EN << BIT_BLOCK_CLK_CAM)) | |
574 | #define CLK_GATE_BLOCK_ALL_DIS ~CLK_GATE_BLOCK_ALL_EN | |
575 | ||
576 | /* | |
577 | * GATE CAM : All block | |
578 | * GATE VP : All block | |
579 | * GATE MFC : All block | |
580 | * GATE G3D : All block | |
581 | * GATE IMAGE : All block | |
582 | * GATE LCD0 : All block | |
583 | * GATE LCD1 : All block | |
584 | * GATE FSYS : Enable - PDMA0,1, SDMMC0,2, USBHOST, USBDEVICE, PPMUFILE | |
585 | * GATE GPS : All block | |
586 | * GATE PERI Left : All Enable, Block - SLIMBUS, SPDIF, AC97 | |
587 | * GATE PERI Right : All Enable, Block - KEYIF | |
588 | * GATE Block : All block | |
589 | */ | |
590 | #define CLK_GATE_IP_CAM_VAL CLK_GATE_IP_CAM_ALL_DIS | |
591 | #define CLK_GATE_IP_VP_VAL CLK_GATE_IP_VP_ALL_DIS | |
592 | #define CLK_GATE_IP_MFC_VAL CLK_GATE_IP_MFC_ALL_DIS | |
593 | #define CLK_GATE_IP_G3D_VAL CLK_GATE_IP_G3D_ALL_DIS | |
594 | #define CLK_GATE_IP_IMAGE_VAL CLK_GATE_IP_IMAGE_ALL_DIS | |
595 | #define CLK_GATE_IP_LCD0_VAL CLK_GATE_IP_LCD0_ALL_DIS | |
596 | #define CLK_GATE_IP_LCD1_VAL CLK_GATE_IP_LCD1_ALL_DIS | |
597 | #define CLK_GATE_IP_FSYS_VAL (CLK_GATE_IP_FSYS_ALL_DIS \ | |
598 | | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\ | |
599 | | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\ | |
600 | | (CLK_EN << BIT_FSYS_CLK_USBHOST)\ | |
601 | | (CLK_EN << BIT_FSYS_CLK_SROMC)\ | |
602 | | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\ | |
603 | | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\ | |
604 | | (CLK_EN << BIT_FSYS_CLK_PDMA1)\ | |
605 | | (CLK_EN << BIT_FSYS_CLK_PDMA0)) | |
606 | #define CLK_GATE_IP_GPS_VAL CLK_GATE_IP_GPS_ALL_DIS | |
607 | #define CLK_GATE_IP_PERIL_VAL (CLK_GATE_IP_PERIL_ALL_DIS \ | |
608 | | ~((CLK_EN << BIT_PERIL_CLK_AC97)\ | |
609 | | (CLK_EN << BIT_PERIL_CLK_SPDIF)\ | |
610 | | (CLK_EN << BIT_PERIL_CLK_I2C2)\ | |
611 | | (CLK_EN << BIT_PERIL_CLK_SLIMBUS))) | |
612 | #define CLK_GATE_IP_PERIR_VAL (CLK_GATE_IP_PERIR_ALL_DIS \ | |
613 | | ~((CLK_EN << BIT_PERIR_CLK_KEYIF))) | |
614 | #define CLK_GATE_BLOCK_VAL CLK_GATE_BLOCK_ALL_DIS | |
615 | ||
616 | /* PS_HOLD: Data Hight, Output En */ | |
617 | #define BIT_DAT 8 | |
618 | #define BIT_EN 9 | |
619 | #define EXYNOS4_PS_HOLD_CON_VAL (0x1 << BIT_DAT | 0x1 << BIT_EN) | |
620 | ||
621 | #endif |