[people/ms/u-boot.git] / board / sandburst / common / ppc440gx_i2c.c

/*
 *  Copyright (C) 2005 Sandburst Corporation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
 * Travis B. Sawyer
 * Sandburst Corporation.
 */
#include <common.h>
#include <ppc4xx.h>
#include <4xx_i2c.h>
#include <i2c.h>
#include <command.h>
#include "ppc440gx_i2c.h"
#include <asm/io.h>

#ifdef CONFIG_I2C_BUS1

#define IIC_OK		0
#define IIC_NOK		1
#define IIC_NOK_LA	2		/* Lost arbitration */
#define IIC_NOK_ICT	3		/* Incomplete transfer */
#define IIC_NOK_XFRA	4		/* Transfer aborted */
#define IIC_NOK_DATA	5		/* No data in buffer */
#define IIC_NOK_TOUT	6		/* Transfer timeout */

#define IIC_TIMEOUT 1			/* 1 second */
#if defined(CONFIG_SYS_I2C_NOPROBES)
static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
#endif

static struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_REGISTERS_BUS1_BASE_ADDRESS;

static void _i2c_bus1_reset (void)
{
	int i, status;

	/* Reset status register */
	/* write 1 in SCMP and IRQA to clear these fields */
	out_8 (IIC_STS1, 0x0A);

	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
	out_8 (IIC_EXTSTS1, 0x8F);
	__asm__ volatile ("eieio");

	/*
	 * Get current state, reset bus
	 * only if no transfers are pending.
	 */
	i = 10;
	do {
		/* Get status */
		status = in_8 (IIC_STS1);
		udelay (500);			/* 500us */
		i--;
	} while ((status & IIC_STS_PT) && (i > 0));
	/* Soft reset controller */
	status = in_8 (IIC_XTCNTLSS1);
	out_8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
	__asm__ volatile ("eieio");

	/* make sure where in initial state, data hi, clock hi */
	out_8 (IIC_DIRECTCNTL1, 0xC);
	for (i = 0; i < 10; i++) {
		if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
			/* clock until we get to known state */
			out_8 (IIC_DIRECTCNTL1, 0x8);	/* clock lo */
			udelay (100);		/* 100us */
			out_8 (IIC_DIRECTCNTL1, 0xC);	/* clock hi */
			udelay (100);		/* 100us */
		} else {
			break;
		}
	}
	/* send start condition */
	out_8 (IIC_DIRECTCNTL1, 0x4);
	udelay (1000);				/* 1ms */
	/* send stop condition */
	out_8 (IIC_DIRECTCNTL1, 0xC);
	udelay (1000);				/* 1ms */
	/* Unreset controller */
	out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
	udelay (1000);				/* 1ms */
}

void i2c1_init (int speed, int slaveadd)
{
	sys_info_t sysInfo;
	unsigned long freqOPB;
	int val, divisor;

#ifdef CONFIG_SYS_I2C_INIT_BOARD
	/* call board specific i2c bus reset routine before accessing the   */
	/* environment, which might be in a chip on that bus. For details   */
	/* about this problem see doc/I2C_Edge_Conditions.                  */
	i2c_init_board();
#endif

	/* Handle possible failed I2C state */
	/* FIXME: put this into i2c_init_board()? */
	_i2c_bus1_reset ();

	/* clear lo master address */
	out_8 (IIC_LMADR1, 0);

	/* clear hi master address */
	out_8 (IIC_HMADR1, 0);

	/* clear lo slave address */
	out_8 (IIC_LSADR1, 0);

	/* clear hi slave address */
	out_8 (IIC_HSADR1, 0);

	/* Clock divide Register */
	/* get OPB frequency */
	get_sys_info (&sysInfo);
	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
	/* set divisor according to freqOPB */
	divisor = (freqOPB - 1) / 10000000;
	if (divisor == 0)
		divisor = 1;
	out_8 (IIC_CLKDIV1, divisor);

	/* no interrupts */
	out_8 (IIC_INTRMSK1, 0);

	/* clear transfer count */
	out_8 (IIC_XFRCNT1, 0);

	/* clear extended control & stat */
	/* write 1 in SRC SRS SWC SWS to clear these fields */
	out_8 (IIC_XTCNTLSS1, 0xF0);

	/* Mode Control Register
	   Flush Slave/Master data buffer */
	out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
	__asm__ volatile ("eieio");


	val = in_8(IIC_MDCNTL1);
	__asm__ volatile ("eieio");

	/* Ignore General Call, slave transfers are ignored,
	   disable interrupts, exit unknown bus state, enable hold
	   SCL
	   100kHz normaly or FastMode for 400kHz and above
	*/

	val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
	if( speed >= 400000 ){
		val |= IIC_MDCNTL_FSM;
	}
	out_8 (IIC_MDCNTL1, val);

	/* clear control reg */
	out_8 (IIC_CNTL1, 0x00);
	__asm__ volatile ("eieio");

}

/*
  This code tries to use the features of the 405GP i2c
  controller. It will transfer up to 4 bytes in one pass
  on the loop. It only does out_8(lbz) to the buffer when it
  is possible to do out16(lhz) transfers.

  cmd_type is 0 for write 1 for read.

  addr_len can take any value from 0-255, it is only limited
  by the char, we could make it larger if needed. If it is
  0 we skip the address write cycle.

  Typical case is a Write of an addr followd by a Read. The
  IBM FAQ does not cover this. On the last byte of the write
  we don't set the creg CHT bit, and on the first bytes of the
  read we set the RPST bit.

  It does not support address only transfers, there must be
  a data part. If you want to write the address yourself, put
  it in the data pointer.

  It does not support transfer to/from address 0.

  It does not check XFRCNT.
*/
static
int i2c_transfer1(unsigned char cmd_type,
		  unsigned char chip,
		  unsigned char addr[],
		  unsigned char addr_len,
		  unsigned char data[],
		  unsigned short data_len )
{
	unsigned char* ptr;
	int reading;
	int tran,cnt;
	int result;
	int status;
	int i;
	uchar creg;

	if( data == 0 || data_len == 0 ){
		/*Don't support data transfer of no length or to address 0*/
		printf( "i2c_transfer: bad call\n" );
		return IIC_NOK;
	}
	if( addr && addr_len ){
		ptr = addr;
		cnt = addr_len;
		reading = 0;
	}else{
		ptr = data;
		cnt = data_len;
		reading = cmd_type;
	}

	/*Clear Stop Complete Bit*/
	out_8(IIC_STS1,IIC_STS_SCMP);
	/* Check init */
	i=10;
	do {
		/* Get status */
		status = in_8(IIC_STS1);
		__asm__ volatile("eieio");
		i--;
	} while ((status & IIC_STS_PT) && (i>0));

	if (status & IIC_STS_PT) {
		result = IIC_NOK_TOUT;
		return(result);
	}
	/*flush the Master/Slave Databuffers*/
	out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
	/*need to wait 4 OPB clocks? code below should take that long*/

	/* 7-bit adressing */
	out_8(IIC_HMADR1,0);
	out_8(IIC_LMADR1, chip);
	__asm__ volatile("eieio");

	tran = 0;
	result = IIC_OK;
	creg = 0;

	while ( tran != cnt && (result == IIC_OK)) {
		int  bc,j;

		/* Control register =
		   Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
		   Transfer is a sequence of transfers
		*/
		creg |= IIC_CNTL_PT;

		bc = (cnt - tran) > 4 ? 4 :
			cnt - tran;
		creg |= (bc-1)<<4;
		/* if the real cmd type is write continue trans*/
		if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
			creg |= IIC_CNTL_CHT;

		if (reading)
			creg |= IIC_CNTL_READ;
		else {
			for(j=0; j<bc; j++) {
				/* Set buffer */
				out_8(IIC_MDBUF1,ptr[tran+j]);
				__asm__ volatile("eieio");
			}
		}
		out_8(IIC_CNTL1, creg );
		__asm__ volatile("eieio");

		/* Transfer is in progress
		   we have to wait for upto 5 bytes of data
		   1 byte chip address+r/w bit then bc bytes
		   of data.
		   udelay(10) is 1 bit time at 100khz
		   Doubled for slop. 20 is too small.
		*/
		i=2*5*8;
		do {
			/* Get status */
			status = in_8(IIC_STS1);
			__asm__ volatile("eieio");
			udelay (10);
			i--;
		} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
			 && (i>0));

		if (status & IIC_STS_ERR) {
			result = IIC_NOK;
			status = in_8 (IIC_EXTSTS1);
			/* Lost arbitration? */
			if (status & IIC_EXTSTS_LA)
				result = IIC_NOK_LA;
			/* Incomplete transfer? */
			if (status & IIC_EXTSTS_ICT)
				result = IIC_NOK_ICT;
			/* Transfer aborted? */
			if (status & IIC_EXTSTS_XFRA)
				result = IIC_NOK_XFRA;
		} else if ( status & IIC_STS_PT) {
			result = IIC_NOK_TOUT;
		}
		/* Command is reading => get buffer */
		if ((reading) && (result == IIC_OK)) {
			/* Are there data in buffer */
			if (status & IIC_STS_MDBS) {
				/*
				  even if we have data we have to wait 4OPB clocks
				  for it to hit the front of the FIFO, after that
				  we can just read. We should check XFCNT here and
				  if the FIFO is full there is no need to wait.
				*/
				udelay (1);
				for(j=0;j<bc;j++) {
					ptr[tran+j] = in_8(IIC_MDBUF1);
					__asm__ volatile("eieio");
				}
			} else
				result = IIC_NOK_DATA;
		}
		creg = 0;
		tran+=bc;
		if( ptr == addr && tran == cnt ) {
			ptr = data;
			cnt = data_len;
			tran = 0;
			reading = cmd_type;
			if( reading )
				creg = IIC_CNTL_RPST;
		}
	}
	return (result);
}

int i2c_probe1 (uchar chip)
{
	uchar buf[1];

	buf[0] = 0;

	/*
	 * What is needed is to send the chip address and verify that the
	 * address was <ACK>ed (i.e. there was a chip at that address which
	 * drove the data line low).
	 */
	return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
}


int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
	uchar xaddr[4];
	int ret;

	if ( alen > 4 ) {
		printf ("I2C read: addr len %d not supported\n", alen);
		return 1;
	}

	if ( alen > 0 ) {
		xaddr[0] = (addr >> 24) & 0xFF;
		xaddr[1] = (addr >> 16) & 0xFF;
		xaddr[2] = (addr >> 8) & 0xFF;
		xaddr[3] = addr & 0xFF;
	}


#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	if( alen > 0 )
		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
	if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
		printf( "I2c read: failed %d\n", ret);
		return 1;
	}
	return 0;
}

int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
	uchar xaddr[4];

	if ( alen > 4 ) {
		printf ("I2C write: addr len %d not supported\n", alen);
		return 1;

	}
	if ( alen > 0 ) {
		xaddr[0] = (addr >> 24) & 0xFF;
		xaddr[1] = (addr >> 16) & 0xFF;
		xaddr[2] = (addr >> 8) & 0xFF;
		xaddr[3] = addr & 0xFF;
	}

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	if( alen > 0 )
		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif

	return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
}

/*-----------------------------------------------------------------------
 * Read a register
 */
uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
{
	uchar buf;

	i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);

	return(buf);
}

/*-----------------------------------------------------------------------
 * Write a register
 */
void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
{
	i2c_write1(i2c_addr, reg, 1, &val, 1);
}


int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int j;
#if defined(CONFIG_SYS_I2C_NOPROBES)
	int k, skip;
#endif

	puts ("Valid chip addresses:");
	for(j = 0; j < 128; j++) {
#if defined(CONFIG_SYS_I2C_NOPROBES)
		skip = 0;
		for (k = 0; k < sizeof(i2c_no_probes); k++){
			if (j == i2c_no_probes[k]){
				skip = 1;
				break;
			}
		}
		if (skip)
			continue;
#endif
		if(i2c_probe1(j) == 0) {
			printf(" %02X", j);
		}
	}
	putc ('\n');

#if defined(CONFIG_SYS_I2C_NOPROBES)
	puts ("Excluded chip addresses:");
	for( k = 0; k < sizeof(i2c_no_probes); k++ )
		printf(" %02X", i2c_no_probes[k] );
	putc ('\n');
#endif

	return 0;
}

U_BOOT_CMD(
	iprobe1,	1,	1,	do_i2c1_probe,
	"probe to discover valid I2C chip addresses",
	""
);

#endif	/* CONFIG_I2C_BUS1 */
Commit	Line	Data
b79316f2 SR	1	/*
	2	* Copyright (C) 2005 Sandburst Corporation
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/*
	24	* Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by
	25	* Travis B. Sawyer
	26	* Sandburst Corporation.
	27	*/
	28	#include <common.h>
	29	#include <ppc4xx.h>
79b2d0bb	30	#include <4xx_i2c.h>
b79316f2	31	#include <i2c.h>
b79316f2 SR	32	#include <command.h>
b79316f2 SR	33	#include "ppc440gx_i2c.h"
61f2b38a	34	#include <asm/io.h>
b79316f2 SR	35
	36	#ifdef CONFIG_I2C_BUS1
	37
b79316f2 SR	38	#define IIC_OK 0
	39	#define IIC_NOK 1
	40	#define IIC_NOK_LA 2 /* Lost arbitration */
	41	#define IIC_NOK_ICT 3 /* Incomplete transfer */
	42	#define IIC_NOK_XFRA 4 /* Transfer aborted */
	43	#define IIC_NOK_DATA 5 /* No data in buffer */
	44	#define IIC_NOK_TOUT 6 /* Transfer timeout */
	45
	46	#define IIC_TIMEOUT 1 /* 1 second */
6d0f6bcf JCPV	47	#if defined(CONFIG_SYS_I2C_NOPROBES)
6d0f6bcf JCPV	48	static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
b79316f2 SR	49	#endif
b79316f2 SR	50
072e754b HS	51	static struct ppc4xx_i2c i2c = (struct ppc4xx_i2c )I2C_REGISTERS_BUS1_BASE_ADDRESS;
072e754b HS	52
b79316f2 SR	53	static void _i2c_bus1_reset (void)
	54	{
	55	int i, status;
	56
	57	/* Reset status register */
	58	/* write 1 in SCMP and IRQA to clear these fields */
072e754b	59	out_8 (IIC_STS1, 0x0A);
b79316f2 SR	60
b79316f2 SR	61	/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
072e754b	62	out_8 (IIC_EXTSTS1, 0x8F);
b79316f2 SR	63	__asm__ volatile ("eieio");
	64
	65	/*
	66	* Get current state, reset bus
	67	* only if no transfers are pending.
	68	*/
	69	i = 10;
	70	do {
	71	/* Get status */
072e754b	72	status = in_8 (IIC_STS1);
b79316f2 SR	73	udelay (500); /* 500us */
	74	i--;
	75	} while ((status & IIC_STS_PT) && (i > 0));
	76	/* Soft reset controller */
072e754b HS	77	status = in_8 (IIC_XTCNTLSS1);
072e754b HS	78	out_8 (IIC_XTCNTLSS1, (status \| IIC_XTCNTLSS_SRST));
b79316f2 SR	79	__asm__ volatile ("eieio");
	80
	81	/* make sure where in initial state, data hi, clock hi */
072e754b	82	out_8 (IIC_DIRECTCNTL1, 0xC);
b79316f2	83	for (i = 0; i < 10; i++) {
072e754b	84	if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
b79316f2	85	/* clock until we get to known state */
072e754b	86	out_8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
b79316f2	87	udelay (100); /* 100us */
072e754b	88	out_8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
b79316f2 SR	89	udelay (100); /* 100us */
	90	} else {
	91	break;
	92	}
	93	}
	94	/* send start condition */
072e754b	95	out_8 (IIC_DIRECTCNTL1, 0x4);
b79316f2 SR	96	udelay (1000); /* 1ms */
b79316f2 SR	97	/* send stop condition */
072e754b	98	out_8 (IIC_DIRECTCNTL1, 0xC);
b79316f2 SR	99	udelay (1000); /* 1ms */
b79316f2 SR	100	/* Unreset controller */
072e754b	101	out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
b79316f2 SR	102	udelay (1000); /* 1ms */
	103	}
	104
	105	void i2c1_init (int speed, int slaveadd)
	106	{
	107	sys_info_t sysInfo;
	108	unsigned long freqOPB;
	109	int val, divisor;
	110
6d0f6bcf	111	#ifdef CONFIG_SYS_I2C_INIT_BOARD
b79316f2 SR	112	/* call board specific i2c bus reset routine before accessing the */
	113	/* environment, which might be in a chip on that bus. For details */
	114	/* about this problem see doc/I2C_Edge_Conditions. */
	115	i2c_init_board();
	116	#endif
	117
	118	/* Handle possible failed I2C state */
	119	/* FIXME: put this into i2c_init_board()? */
	120	_i2c_bus1_reset ();
	121
	122	/* clear lo master address */
072e754b	123	out_8 (IIC_LMADR1, 0);
b79316f2 SR	124
b79316f2 SR	125	/* clear hi master address */
072e754b	126	out_8 (IIC_HMADR1, 0);
b79316f2 SR	127
b79316f2 SR	128	/* clear lo slave address */
072e754b	129	out_8 (IIC_LSADR1, 0);
b79316f2 SR	130
b79316f2 SR	131	/* clear hi slave address */
072e754b	132	out_8 (IIC_HSADR1, 0);
b79316f2 SR	133
	134	/* Clock divide Register */
	135	/* get OPB frequency */
	136	get_sys_info (&sysInfo);
	137	freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
	138	/* set divisor according to freqOPB */
	139	divisor = (freqOPB - 1) / 10000000;
	140	if (divisor == 0)
	141	divisor = 1;
072e754b	142	out_8 (IIC_CLKDIV1, divisor);
b79316f2 SR	143
b79316f2 SR	144	/* no interrupts */
072e754b	145	out_8 (IIC_INTRMSK1, 0);
b79316f2 SR	146
b79316f2 SR	147	/* clear transfer count */
072e754b	148	out_8 (IIC_XFRCNT1, 0);
b79316f2 SR	149
	150	/* clear extended control & stat */
	151	/* write 1 in SRC SRS SWC SWS to clear these fields */
072e754b	152	out_8 (IIC_XTCNTLSS1, 0xF0);
b79316f2 SR	153
	154	/* Mode Control Register
	155	Flush Slave/Master data buffer */
072e754b	156	out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB \| IIC_MDCNTL_FMDB);
b79316f2 SR	157	__asm__ volatile ("eieio");
	158
	159
072e754b	160	val = in_8(IIC_MDCNTL1);
b79316f2 SR	161	__asm__ volatile ("eieio");
	162
	163	/* Ignore General Call, slave transfers are ignored,
	164	disable interrupts, exit unknown bus state, enable hold
	165	SCL
	166	100kHz normaly or FastMode for 400kHz and above
	167	*/
	168
	169	val \|= IIC_MDCNTL_EUBS\|IIC_MDCNTL_HSCL;
	170	if( speed >= 400000 ){
	171	val \|= IIC_MDCNTL_FSM;
	172	}
072e754b	173	out_8 (IIC_MDCNTL1, val);
b79316f2 SR	174
b79316f2 SR	175	/* clear control reg */
072e754b	176	out_8 (IIC_CNTL1, 0x00);
b79316f2 SR	177	__asm__ volatile ("eieio");
	178
	179	}
	180
	181	/*
	182	This code tries to use the features of the 405GP i2c
	183	controller. It will transfer up to 4 bytes in one pass
072e754b	184	on the loop. It only does out_8(lbz) to the buffer when it
b79316f2 SR	185	is possible to do out16(lhz) transfers.
	186
	187	cmd_type is 0 for write 1 for read.
	188
	189	addr_len can take any value from 0-255, it is only limited
	190	by the char, we could make it larger if needed. If it is
	191	0 we skip the address write cycle.
	192
	193	Typical case is a Write of an addr followd by a Read. The
	194	IBM FAQ does not cover this. On the last byte of the write
	195	we don't set the creg CHT bit, and on the first bytes of the
	196	read we set the RPST bit.
	197
	198	It does not support address only transfers, there must be
	199	a data part. If you want to write the address yourself, put
	200	it in the data pointer.
	201
	202	It does not support transfer to/from address 0.
	203
	204	It does not check XFRCNT.
	205	*/
	206	static
	207	int i2c_transfer1(unsigned char cmd_type,
	208	unsigned char chip,
	209	unsigned char addr[],
	210	unsigned char addr_len,
	211	unsigned char data[],
	212	unsigned short data_len )
	213	{
	214	unsigned char* ptr;
	215	int reading;
	216	int tran,cnt;
	217	int result;
	218	int status;
	219	int i;
	220	uchar creg;
	221
	222	if( data == 0 \|\| data_len == 0 ){
	223	/Don't support data transfer of no length or to address 0/
	224	printf( "i2c_transfer: bad call\n" );
	225	return IIC_NOK;
	226	}
	227	if( addr && addr_len ){
	228	ptr = addr;
	229	cnt = addr_len;
	230	reading = 0;
	231	}else{
	232	ptr = data;
	233	cnt = data_len;
	234	reading = cmd_type;
	235	}
	236
	237	/Clear Stop Complete Bit/
072e754b	238	out_8(IIC_STS1,IIC_STS_SCMP);
b79316f2 SR	239	/* Check init */
	240	i=10;
	241	do {
	242	/* Get status */
072e754b	243	status = in_8(IIC_STS1);
b79316f2 SR	244	__asm__ volatile("eieio");
	245	i--;
	246	} while ((status & IIC_STS_PT) && (i>0));
	247
	248	if (status & IIC_STS_PT) {
	249	result = IIC_NOK_TOUT;
	250	return(result);
	251	}
	252	/flush the Master/Slave Databuffers/
072e754b	253	out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))\|IIC_MDCNTL_FMDB\|IIC_MDCNTL_FSDB));
b79316f2 SR	254	/need to wait 4 OPB clocks? code below should take that long/
	255
	256	/* 7-bit adressing */
072e754b HS	257	out_8(IIC_HMADR1,0);
072e754b HS	258	out_8(IIC_LMADR1, chip);
b79316f2 SR	259	__asm__ volatile("eieio");
	260
	261	tran = 0;
	262	result = IIC_OK;
	263	creg = 0;
	264
	265	while ( tran != cnt && (result == IIC_OK)) {
	266	int bc,j;
	267
	268	/* Control register =
	269	Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
	270	Transfer is a sequence of transfers
	271	*/
	272	creg \|= IIC_CNTL_PT;
	273
	274	bc = (cnt - tran) > 4 ? 4 :
	275	cnt - tran;
	276	creg \|= (bc-1)<<4;
	277	/* if the real cmd type is write continue trans*/
	278	if ( (!cmd_type && (ptr == addr)) \|\| ((tran+bc) != cnt) )
	279	creg \|= IIC_CNTL_CHT;
	280
	281	if (reading)
	282	creg \|= IIC_CNTL_READ;
	283	else {
	284	for(j=0; j<bc; j++) {
	285	/* Set buffer */
072e754b	286	out_8(IIC_MDBUF1,ptr[tran+j]);
b79316f2 SR	287	__asm__ volatile("eieio");
	288	}
	289	}
072e754b	290	out_8(IIC_CNTL1, creg );
b79316f2 SR	291	__asm__ volatile("eieio");
	292
	293	/* Transfer is in progress
	294	we have to wait for upto 5 bytes of data
	295	1 byte chip address+r/w bit then bc bytes
	296	of data.
	297	udelay(10) is 1 bit time at 100khz
	298	Doubled for slop. 20 is too small.
	299	*/
	300	i=258;
	301	do {
	302	/* Get status */
072e754b	303	status = in_8(IIC_STS1);
b79316f2 SR	304	__asm__ volatile("eieio");
	305	udelay (10);
	306	i--;
	307	} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
	308	&& (i>0));
	309
	310	if (status & IIC_STS_ERR) {
	311	result = IIC_NOK;
072e754b	312	status = in_8 (IIC_EXTSTS1);
b79316f2 SR	313	/* Lost arbitration? */
	314	if (status & IIC_EXTSTS_LA)
	315	result = IIC_NOK_LA;
	316	/* Incomplete transfer? */
	317	if (status & IIC_EXTSTS_ICT)
	318	result = IIC_NOK_ICT;
	319	/* Transfer aborted? */
	320	if (status & IIC_EXTSTS_XFRA)
	321	result = IIC_NOK_XFRA;
	322	} else if ( status & IIC_STS_PT) {
	323	result = IIC_NOK_TOUT;
	324	}
	325	/* Command is reading => get buffer */
	326	if ((reading) && (result == IIC_OK)) {
	327	/* Are there data in buffer */
	328	if (status & IIC_STS_MDBS) {
	329	/*
	330	even if we have data we have to wait 4OPB clocks
	331	for it to hit the front of the FIFO, after that
	332	we can just read. We should check XFCNT here and
	333	if the FIFO is full there is no need to wait.
	334	*/
	335	udelay (1);
	336	for(j=0;j<bc;j++) {
072e754b	337	ptr[tran+j] = in_8(IIC_MDBUF1);
b79316f2 SR	338	__asm__ volatile("eieio");
	339	}
	340	} else
	341	result = IIC_NOK_DATA;
	342	}
	343	creg = 0;
	344	tran+=bc;
	345	if( ptr == addr && tran == cnt ) {
	346	ptr = data;
	347	cnt = data_len;
	348	tran = 0;
	349	reading = cmd_type;
	350	if( reading )
	351	creg = IIC_CNTL_RPST;
	352	}
	353	}
	354	return (result);
	355	}
	356
	357	int i2c_probe1 (uchar chip)
	358	{
	359	uchar buf[1];
	360
	361	buf[0] = 0;
	362
	363	/*
	364	* What is needed is to send the chip address and verify that the
	365	* address was <ACK>ed (i.e. there was a chip at that address which
	366	* drove the data line low).
	367	*/
	368	return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
	369	}
	370
	371
	372	int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
	373	{
	374	uchar xaddr[4];
	375	int ret;
	376
	377	if ( alen > 4 ) {
	378	printf ("I2C read: addr len %d not supported\n", alen);
	379	return 1;
	380	}
	381
	382	if ( alen > 0 ) {
	383	xaddr[0] = (addr >> 24) & 0xFF;
	384	xaddr[1] = (addr >> 16) & 0xFF;
	385	xaddr[2] = (addr >> 8) & 0xFF;
	386	xaddr[3] = addr & 0xFF;
	387	}
	388
	389
6d0f6bcf	390	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
b79316f2 SR	391	/*
	392	* EEPROM chips that implement "address overflow" are ones
	393	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	394	* address and the extra bits end up in the "chip address"
	395	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	396	* four 256 byte chips.
	397	*
	398	* Note that we consider the length of the address field to
	399	* still be one byte because the extra address bits are
	400	* hidden in the chip address.
	401	*/
	402	if( alen > 0 )
6d0f6bcf	403	chip \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
b79316f2 SR	404	#endif
	405	if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
	406	printf( "I2c read: failed %d\n", ret);
	407	return 1;
	408	}
	409	return 0;
	410	}
	411
	412	int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
	413	{
	414	uchar xaddr[4];
	415
	416	if ( alen > 4 ) {
	417	printf ("I2C write: addr len %d not supported\n", alen);
	418	return 1;
	419
	420	}
	421	if ( alen > 0 ) {
	422	xaddr[0] = (addr >> 24) & 0xFF;
	423	xaddr[1] = (addr >> 16) & 0xFF;
	424	xaddr[2] = (addr >> 8) & 0xFF;
	425	xaddr[3] = addr & 0xFF;
	426	}
	427
6d0f6bcf	428	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
b79316f2 SR	429	/*
	430	* EEPROM chips that implement "address overflow" are ones
	431	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	432	* address and the extra bits end up in the "chip address"
	433	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	434	* four 256 byte chips.
	435	*
	436	* Note that we consider the length of the address field to
	437	* still be one byte because the extra address bits are
	438	* hidden in the chip address.
	439	*/
	440	if( alen > 0 )
6d0f6bcf	441	chip \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
b79316f2 SR	442	#endif
	443
	444	return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
	445	}
	446
	447	/*-----------------------------------------------------------------------
	448	* Read a register
	449	*/
	450	uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
	451	{
77ddac94	452	uchar buf;
b79316f2	453
77ddac94	454	i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
b79316f2 SR	455
	456	return(buf);
	457	}
	458
	459	/*-----------------------------------------------------------------------
	460	* Write a register
	461	*/
	462	void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
	463	{
	464	i2c_write1(i2c_addr, reg, 1, &val, 1);
	465	}
	466
	467
	468	int do_i2c1_probe(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	469	{
	470	int j;
6d0f6bcf	471	#if defined(CONFIG_SYS_I2C_NOPROBES)
b79316f2 SR	472	int k, skip;
	473	#endif
	474
	475	puts ("Valid chip addresses:");
	476	for(j = 0; j < 128; j++) {
6d0f6bcf	477	#if defined(CONFIG_SYS_I2C_NOPROBES)
b79316f2 SR	478	skip = 0;
	479	for (k = 0; k < sizeof(i2c_no_probes); k++){
	480	if (j == i2c_no_probes[k]){
	481	skip = 1;
	482	break;
	483	}
	484	}
	485	if (skip)
	486	continue;
	487	#endif
	488	if(i2c_probe1(j) == 0) {
	489	printf(" %02X", j);
	490	}
	491	}
	492	putc ('\n');
	493
6d0f6bcf	494	#if defined(CONFIG_SYS_I2C_NOPROBES)
b79316f2 SR	495	puts ("Excluded chip addresses:");
	496	for( k = 0; k < sizeof(i2c_no_probes); k++ )
	497	printf(" %02X", i2c_no_probes[k] );
	498	putc ('\n');
	499	#endif
	500
	501	return 0;
	502	}
	503
	504	U_BOOT_CMD(
	505	iprobe1, 1, 1, do_i2c1_probe,
2fb2604d	506	"probe to discover valid I2C chip addresses",
a89c33db	507	""
b79316f2 SR	508	);
b79316f2 SR	509
3d078ce6	510	#endif /* CONFIG_I2C_BUS1 */