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1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * | |
6 | * (C) Copyright 2001 | |
7 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
8 | * Jay Monkman <jtm@smoothsmoothie.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #include <common.h> | |
30 | #include <ioports.h> | |
31 | #include <mpc8260.h> | |
32 | ||
33 | /* | |
34 | * I/O Port configuration table | |
35 | * | |
36 | * if conf is 1, then that port pin will be configured at boot time | |
37 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
38 | */ | |
39 | ||
40 | const iop_conf_t iop_conf_tab[4][32] = { | |
41 | ||
42 | /* Port A configuration */ | |
43 | { /* conf ppar psor pdir podr pdat */ | |
44 | /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ | |
45 | /* PA30 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ | |
46 | /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ | |
47 | /* PA28 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ | |
48 | /* PA27 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ | |
49 | /* PA26 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ | |
50 | /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ | |
51 | /* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ | |
52 | /* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ | |
53 | /* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ | |
54 | /* PA21 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ | |
55 | /* PA20 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ | |
56 | /* PA19 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ | |
57 | /* PA18 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ | |
58 | /* PA17 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ | |
59 | /* PA16 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ | |
60 | /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ | |
61 | /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ | |
62 | /* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ | |
63 | /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ | |
64 | /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ | |
65 | /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ | |
66 | /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ | |
67 | /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ | |
68 | /* PA7 */ { 1, 0, 0, 1, 0, 0 }, /* PA7 */ | |
69 | /* PA6 */ { 1, 0, 0, 1, 0, 0 }, /* PA6 */ | |
70 | /* PA5 */ { 1, 0, 0, 1, 0, 0 }, /* PA5 */ | |
71 | /* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* PA4 */ | |
72 | /* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* PA3 */ | |
73 | /* PA2 */ { 1, 0, 0, 1, 0, 0 }, /* PA2 */ | |
74 | /* PA1 */ { 1, 0, 0, 1, 0, 0 }, /* PA1 */ | |
75 | /* PA0 */ { 1, 0, 0, 1, 0, 0 } /* PA0 */ | |
76 | }, | |
77 | ||
78 | /* Port B configuration */ | |
79 | { /* conf ppar psor pdir podr pdat */ | |
80 | /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ | |
81 | /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ | |
82 | /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ | |
83 | /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ | |
84 | /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ | |
85 | /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ | |
86 | /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ | |
87 | /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ | |
88 | /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ | |
89 | /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ | |
90 | /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ | |
91 | /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ | |
92 | /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ | |
93 | /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ | |
94 | /* PB17 */ { 1, 0, 0, 1, 0, 0 }, /* PB17 */ | |
95 | /* PB16 */ { 1, 0, 0, 1, 0, 0 }, /* PB16 */ | |
96 | /* PB15 */ { 1, 0, 0, 1, 0, 0 }, /* PB15 */ | |
97 | /* PB14 */ { 1, 0, 0, 1, 0, 0 }, /* PB14 */ | |
98 | /* PB13 */ { 1, 0, 0, 1, 0, 0 }, /* PB13 */ | |
99 | /* PB12 */ { 1, 0, 0, 1, 0, 0 }, /* PB12 */ | |
100 | /* PB11 */ { 1, 0, 0, 1, 0, 0 }, /* PB11 */ | |
101 | /* PB10 */ { 1, 0, 0, 1, 0, 0 }, /* PB10 */ | |
102 | /* PB9 */ { 1, 0, 0, 1, 0, 0 }, /* PB9 */ | |
103 | /* PB8 */ { 1, 0, 0, 1, 0, 0 }, /* PB8 */ | |
104 | /* PB7 */ { 1, 0, 0, 1, 0, 0 }, /* PB7 */ | |
105 | /* PB6 */ { 1, 0, 0, 1, 0, 0 }, /* PB6 */ | |
106 | /* PB5 */ { 1, 0, 0, 1, 0, 0 }, /* PB5 */ | |
107 | /* PB4 */ { 1, 0, 0, 1, 0, 0 }, /* PB4 */ | |
108 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
109 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
110 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
111 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
112 | }, | |
113 | ||
114 | /* Port C */ | |
115 | { /* conf ppar psor pdir podr pdat */ | |
116 | /* PC31 */ { 1, 0, 0, 1, 0, 0 }, /* PC31 */ | |
117 | /* PC30 */ { 1, 0, 0, 1, 0, 0 }, /* PC30 */ | |
118 | /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ | |
119 | /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* PC28 */ | |
120 | /* PC27 */ { 1, 0, 0, 1, 0, 0 }, /* PC27 */ | |
121 | /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* PC26 */ | |
122 | /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* PC25 */ | |
123 | /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* PC24 */ | |
124 | /* PC23 */ { 1, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ | |
125 | /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ | |
126 | /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ | |
127 | /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ | |
128 | /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ | |
129 | /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ | |
130 | /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 */ | |
131 | /* PC16 */ { 1, 0, 0, 1, 0, 0 }, /* PC16 */ | |
132 | /* PC15 */ { 1, 0, 0, 1, 0, 0 }, /* PC15 */ | |
133 | /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ | |
134 | /* PC13 */ { 1, 0, 0, 1, 0, 0 }, /* PC13 */ | |
135 | /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* PC12 */ | |
136 | /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* PC11 */ | |
137 | /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ | |
138 | /* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ | |
139 | /* PC8 */ { 1, 0, 0, 1, 0, 0 }, /* PC8 */ | |
140 | /* PC7 */ { 1, 0, 0, 1, 0, 0 }, /* PC7 */ | |
141 | /* PC6 */ { 1, 0, 0, 1, 0, 0 }, /* PC6 */ | |
142 | /* PC5 */ { 1, 0, 0, 1, 0, 0 }, /* PC5 */ | |
143 | /* PC4 */ { 1, 0, 0, 1, 0, 0 }, /* PC4 */ | |
144 | /* PC3 */ { 1, 0, 0, 1, 0, 0 }, /* PC3 */ | |
145 | /* PC2 */ { 1, 0, 0, 1, 0, 1 }, /* ENET FDE */ | |
146 | /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* ENET DSQE */ | |
147 | /* PC0 */ { 1, 0, 0, 1, 0, 0 }, /* ENET LBK */ | |
148 | }, | |
149 | ||
150 | /* Port D */ | |
151 | { /* conf ppar psor pdir podr pdat */ | |
152 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ | |
153 | /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ | |
154 | /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ | |
155 | /* PD28 */ { 1, 0, 0, 1, 0, 0 }, /* PD28 */ | |
156 | /* PD27 */ { 1, 0, 0, 1, 0, 0 }, /* PD27 */ | |
157 | /* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* PD26 */ | |
158 | /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* PD25 */ | |
159 | /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* PD24 */ | |
160 | /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* PD23 */ | |
161 | /* PD22 */ { 1, 0, 0, 1, 0, 0 }, /* PD22 */ | |
162 | /* PD21 */ { 1, 0, 0, 1, 0, 0 }, /* PD21 */ | |
163 | /* PD20 */ { 1, 0, 0, 1, 0, 0 }, /* PD20 */ | |
164 | /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* PD19 */ | |
165 | /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* PD18 */ | |
166 | /* PD17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ | |
167 | /* PD16 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ | |
168 | #if defined(CONFIG_SOFT_I2C) | |
169 | /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ | |
170 | /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ | |
171 | #else | |
172 | #if defined(CONFIG_HARD_I2C) | |
173 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
174 | /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
175 | #else /* normal I/O port pins */ | |
176 | /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SDA */ | |
177 | /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* I2C SCL */ | |
178 | #endif | |
179 | #endif | |
180 | /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* PD13 */ | |
181 | /* PD12 */ { 1, 0, 0, 0, 0, 0 }, /* PD12 */ | |
182 | /* PD11 */ { 1, 0, 0, 0, 0, 0 }, /* PD11 */ | |
183 | /* PD10 */ { 1, 0, 0, 0, 0, 0 }, /* PD10 */ | |
184 | /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ | |
185 | /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ | |
186 | /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* PD7 */ | |
187 | /* PD6 */ { 1, 0, 0, 1, 0, 1 }, /* PD6 */ | |
188 | /* PD5 */ { 1, 0, 0, 1, 0, 1 }, /* PD5 */ | |
189 | /* PD4 */ { 1, 0, 0, 1, 0, 1 }, /* PD4 */ | |
190 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
191 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
192 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ | |
193 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ | |
194 | } | |
195 | }; | |
196 | ||
197 | /* ------------------------------------------------------------------------- */ | |
198 | ||
199 | /* | |
200 | * Check Board Identity: | |
201 | */ | |
202 | ||
203 | int checkboard (void) | |
204 | { | |
205 | puts ("Board: EST SBC8260\n"); | |
206 | return 0; | |
207 | } | |
208 | ||
209 | /* ------------------------------------------------------------------------- */ | |
210 | ||
211 | long int initdram (int board_type) | |
212 | { | |
213 | volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
214 | volatile memctl8260_t *memctl = &immap->im_memctl; | |
215 | volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); | |
216 | ulong psdmr = CFG_PSDMR; | |
217 | int i; | |
218 | ||
219 | /* | |
220 | * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): | |
221 | * | |
222 | * "At system reset, initialization software must set up the | |
223 | * programmable parameters in the memory controller banks registers | |
224 | * (ORx, BRx, P/LSDMR). After all memory parameters are configured, | |
225 | * system software should execute the following initialization sequence | |
226 | * for each SDRAM device. | |
227 | * | |
228 | * 1. Issue a PRECHARGE-ALL-BANKS command | |
229 | * 2. Issue eight CBR REFRESH commands | |
230 | * 3. Issue a MODE-SET command to initialize the mode register | |
231 | * | |
232 | * The initial commands are executed by setting P/LSDMR[OP] and | |
233 | * accessing the SDRAM with a single-byte transaction." | |
234 | * | |
235 | * The appropriate BRx/ORx registers have already been set when we | |
236 | * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. | |
237 | */ | |
238 | ||
239 | memctl->memc_psrt = CFG_PSRT; | |
240 | memctl->memc_mptpr = CFG_MPTPR; | |
241 | ||
242 | memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; | |
243 | *ramaddr = c; | |
244 | ||
245 | memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; | |
246 | for (i = 0; i < 8; i++) | |
247 | *ramaddr = c; | |
248 | ||
249 | memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; | |
250 | *ramaddr = c; | |
251 | ||
252 | memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; | |
253 | *ramaddr = c; | |
254 | ||
255 | /* return total ram size */ | |
256 | return (CFG_SDRAM0_SIZE * 1024 * 1024); | |
257 | } | |
258 | ||
259 | #ifdef CONFIG_MISC_INIT_R | |
260 | /* ------------------------------------------------------------------------- */ | |
261 | int misc_init_r (void) | |
262 | { | |
263 | #ifdef CFG_LED_BASE | |
264 | uchar ds = *(unsigned char *) (CFG_LED_BASE + 1); | |
265 | uchar ss; | |
266 | uchar tmp[64]; | |
267 | int res; | |
268 | ||
269 | if ((ds != 0) && (ds != 0xff)) { | |
270 | res = getenv_r ("ethaddr", tmp, sizeof (tmp)); | |
271 | if (res > 0) { | |
272 | ss = ((ds >> 4) & 0x0f); | |
273 | ss += ss < 0x0a ? '0' : ('a' - 10); | |
274 | tmp[15] = ss; | |
275 | ||
276 | ss = (ds & 0x0f); | |
277 | ss += ss < 0x0a ? '0' : ('a' - 10); | |
278 | tmp[16] = ss; | |
279 | ||
280 | tmp[17] = '\0'; | |
281 | setenv ("ethaddr", tmp); | |
282 | /* set the led to show the address */ | |
283 | *((unsigned char *) (CFG_LED_BASE + 1)) = ds; | |
284 | } | |
285 | } | |
286 | #endif /* CFG_LED_BASE */ | |
287 | return (0); | |
288 | } | |
289 | #endif /* CONFIG_MISC_INIT_R */ |