[people/ms/u-boot.git] / board / sbc8349 / pci.c

/*
 * pci.c -- WindRiver SBC8349 PCI board support.
 * Copyright (c) 2006 Wind River Systems, Inc.
 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
 *
 * Based on MPC8349 PCI support but w/o PIB related code.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>

DECLARE_GLOBAL_DATA_PTR;

static struct pci_region pci1_regions[] = {
	{
		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
		size: CONFIG_SYS_PCI1_MEM_SIZE,
		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
	},
	{
		bus_start: CONFIG_SYS_PCI1_IO_BASE,
		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
		size: CONFIG_SYS_PCI1_IO_SIZE,
		flags: PCI_REGION_IO
	},
	{
		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
		size: CONFIG_SYS_PCI1_MMIO_SIZE,
		flags: PCI_REGION_MEM
	},
};

/*
 * pci_init_board()
 *
 * NOTICE: PCI2 is not supported. There is only one
 * physical PCI slot on the board.
 *
 */
void
pci_init_board(void)
{
	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	struct pci_region *reg[] = { pci1_regions };

	/* Enable all 8 PCI_CLK_OUTPUTS */
	clk->occr = 0xff000000;
	udelay(2000);

	/* Configure PCI Local Access Windows */
	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;

	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;

	udelay(2000);

	mpc83xx_pci_init(1, reg);
}
Commit	Line	Data
91e25769 PG	1	/*
	2	* pci.c -- WindRiver SBC8349 PCI board support.
	3	* Copyright (c) 2006 Wind River Systems, Inc.
9993e196	4	* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
91e25769 PG	5	*
	6	* Based on MPC8349 PCI support but w/o PIB related code.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*
	26	*/
	27
	28	#include <asm/mmu.h>
9993e196	29	#include <asm/io.h>
91e25769	30	#include <common.h>
9993e196	31	#include <mpc83xx.h>
91e25769	32	#include <pci.h>
91e25769	33	#include <i2c.h>
9993e196	34	#include <asm/fsl_i2c.h>
91e25769 PG	35
	36	DECLARE_GLOBAL_DATA_PTR;
	37
9993e196 KP	38	static struct pci_region pci1_regions[] = {
	39	{
	40	bus_start: CONFIG_SYS_PCI1_MEM_BASE,
	41	phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
	42	size: CONFIG_SYS_PCI1_MEM_SIZE,
	43	flags: PCI_REGION_MEM \| PCI_REGION_PREFETCH
	44	},
	45	{
	46	bus_start: CONFIG_SYS_PCI1_IO_BASE,
	47	phys_start: CONFIG_SYS_PCI1_IO_PHYS,
	48	size: CONFIG_SYS_PCI1_IO_SIZE,
	49	flags: PCI_REGION_IO
	50	},
	51	{
	52	bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
	53	phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
	54	size: CONFIG_SYS_PCI1_MMIO_SIZE,
	55	flags: PCI_REGION_MEM
91e25769	56	},
91e25769 PG	57	};
91e25769 PG	58
9993e196	59	/*
91e25769 PG	60	* pci_init_board()
	61	*
	62	* NOTICE: PCI2 is not supported. There is only one
	63	* physical PCI slot on the board.
	64	*
	65	*/
	66	void
	67	pci_init_board(void)
	68	{
9993e196 KP	69	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
	70	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
	71	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	72	struct pci_region *reg[] = { pci1_regions };
91e25769	73
9993e196	74	/* Enable all 8 PCI_CLK_OUTPUTS */
91e25769 PG	75	clk->occr = 0xff000000;
	76	udelay(2000);
	77
9993e196	78	/* Configure PCI Local Access Windows */
6d0f6bcf	79	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
91e25769 PG	80	pci_law[0].ar = LAWAR_EN \| LAWAR_SIZE_1G;
91e25769 PG	81
6d0f6bcf	82	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
91e25769 PG	83	pci_law[1].ar = LAWAR_EN \| LAWAR_SIZE_4M;
91e25769 PG	84
9993e196	85	udelay(2000);
5b8bc606	86
6aa3d3bf	87	mpc83xx_pci_init(1, reg);
5b8bc606	88	}