[people/ms/u-boot.git] / board / sbc8349 / sbc8349.c

/*
 * sbc8349.c -- WindRiver SBC8349 board support.
 * Copyright (c) 2006-2007 Wind River Systems, Inc.
 *
 * Paul Gortmaker <paul.gortmaker@windriver.com>
 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spd_sdram.h>
#include <miiphy.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif

int fixed_sdram(void);
void sdram_init(void);

#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
void ddr_enable_ecc(unsigned int dram_size);
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f (void)
{
	return 0;
}
#endif

#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)

phys_size_t initdram (int board_type)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	u32 msize = 0;

	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
		return -1;

	/* DDR SDRAM - Main SODIMM */
	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
	msize = spd_sdram();
#else
	msize = fixed_sdram();
#endif
	/*
	 * Initialize SDRAM if it is on local bus.
	 */
	sdram_init();

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(msize * 1024 * 1024);
#endif
	/* return total bus SDRAM size(bytes)  -- DDR */
	return (msize * 1024 * 1024);
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
int fixed_sdram(void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	u32 msize = CONFIG_SYS_DDR_SIZE;
	u32 ddr_size = msize << 20;	/* DDR size in bytes */
	u32 ddr_size_log2 = __ilog2(msize);

	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);

#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currently any ddr size other than 256 is not supported
#endif

#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
	im->ddr.csbnds[2].csbnds =
		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
		(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
				CSBNDS_EA_SHIFT) & CSBNDS_EA);
	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;

	/* currently we use only one CS, so disable the other banks */
	im->ddr.cs_config[0] = 0;
	im->ddr.cs_config[1] = 0;
	im->ddr.cs_config[3] = 0;

	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;

	im->ddr.sdram_cfg =
		SDRAM_CFG_SREN
#if defined(CONFIG_DDR_2T_TIMING)
		| SDRAM_CFG_2T_EN
#endif
		| SDRAM_CFG_SDRAM_TYPE_DDR1;
#if defined (CONFIG_DDR_32BIT)
	/* for 32-bit mode burst length is 8 */
	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
#endif
	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;

	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
	udelay(200);

	/* enable DDR controller */
	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
	return msize;
}
#endif/*!CONFIG_SYS_SPD_EEPROM*/


int checkboard (void)
{
	puts("Board: Wind River SBC834x\n");
	return 0;
}

/*
 * if board is fitted with SDRAM
 */
#if defined(CONFIG_SYS_BR2_PRELIM)  \
	&& defined(CONFIG_SYS_OR2_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
/*
 * Initialize SDRAM memory on the Local Bus.
 */

void sdram_init(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile fsl_lbc_t *lbc = &immap->im_lbc;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;

	puts("\n   SDRAM on Local Bus: ");
	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
	 */

	/* setup mtrpt, lsrt and lbcr for LB bus */
	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	asm("sync");

	/*
	 * Configure the SDRAM controller Machine Mode Register.
	 */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
	asm("sync");
	/*1 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*2 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*3 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*4 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*5 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*6 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*7 times*/
	*sdram_addr = 0xff;
	udelay(100);
	/*8 times*/
	*sdram_addr = 0xff;
	udelay(100);

	/* 0x58636733; mode register write operation */
	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);

	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
	asm("sync");
	*sdram_addr = 0xff;
	udelay(100);
}
#else
void sdram_init(void)
{
	puts("   SDRAM on Local Bus: Disabled in config\n");
}
#endif

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
	ft_pci_setup(blob, bd);
#endif
}
#endif
Commit	Line	Data
91e25769 PG	1	/*
	2	* sbc8349.c -- WindRiver SBC8349 board support.
	3	* Copyright (c) 2006-2007 Wind River Systems, Inc.
	4	*
	5	* Paul Gortmaker <paul.gortmaker@windriver.com>
	6	* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
91e25769 PG	9	*/
	10
	11	#include <common.h>
	12	#include <ioports.h>
	13	#include <mpc83xx.h>
	14	#include <asm/mpc8349_pci.h>
	15	#include <i2c.h>
91e25769	16	#include <spd_sdram.h>
a30a549a	17	#include <miiphy.h>
b3458d2c	18	#if defined(CONFIG_OF_LIBFDT)
2408b3f2	19	#include <libfdt.h>
91e25769 PG	20	#endif
	21
	22	int fixed_sdram(void);
	23	void sdram_init(void);
	24
0f898604	25	#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
91e25769 PG	26	void ddr_enable_ecc(unsigned int dram_size);
	27	#endif
	28
	29	#ifdef CONFIG_BOARD_EARLY_INIT_F
	30	int board_early_init_f (void)
	31	{
	32	return 0;
	33	}
	34	#endif
	35
	36	#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
	37
9973e3c6	38	phys_size_t initdram (int board_type)
91e25769	39	{
6d0f6bcf	40	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
91e25769 PG	41	u32 msize = 0;
	42
	43	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
	44	return -1;
	45
91e25769	46	/* DDR SDRAM - Main SODIMM */
6d0f6bcf	47	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
91e25769 PG	48	#if defined(CONFIG_SPD_EEPROM)
	49	msize = spd_sdram();
	50	#else
	51	msize = fixed_sdram();
	52	#endif
	53	/*
	54	* Initialize SDRAM if it is on local bus.
	55	*/
	56	sdram_init();
	57
	58	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	59	/*
	60	* Initialize and enable DDR ECC.
	61	*/
	62	ddr_enable_ecc(msize * 1024 * 1024);
	63	#endif
91e25769 PG	64	/* return total bus SDRAM size(bytes) -- DDR */
	65	return (msize * 1024 * 1024);
	66	}
	67
	68	#if !defined(CONFIG_SPD_EEPROM)
	69	/*************************************************************************
	70	* fixed sdram init -- doesn't use serial presence detect.
	71	************************************************************************/
	72	int fixed_sdram(void)
	73	{
6d0f6bcf	74	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
2e651b24 JH	75	u32 msize = CONFIG_SYS_DDR_SIZE;
	76	u32 ddr_size = msize << 20; /* DDR size in bytes */
	77	u32 ddr_size_log2 = __ilog2(msize);
	78
6d0f6bcf	79	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
91e25769 PG	80	im->sysconf.ddrlaw[0].ar = LAWAR_EN \| ((ddr_size_log2 - 1) & LAWAR_SIZE);
91e25769 PG	81
6d0f6bcf	82	#if (CONFIG_SYS_DDR_SIZE != 256)
91e25769 PG	83	#warning Currently any ddr size other than 256 is not supported
91e25769 PG	84	#endif
2e651b24 JH	85
	86	#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
	87	#warning Chip select bounds is only configurable in 16MB increments
	88	#endif
	89	im->ddr.csbnds[2].csbnds =
	90	((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) \|
	91	(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
	92	CSBNDS_EA_SHIFT) & CSBNDS_EA);
	93	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
91e25769 PG	94
	95	/* currently we use only one CS, so disable the other banks */
	96	im->ddr.cs_config[0] = 0;
	97	im->ddr.cs_config[1] = 0;
	98	im->ddr.cs_config[3] = 0;
	99
6d0f6bcf JCPV	100	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
6d0f6bcf JCPV	101	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
91e25769 PG	102
	103	im->ddr.sdram_cfg =
	104	SDRAM_CFG_SREN
	105	#if defined(CONFIG_DDR_2T_TIMING)
	106	\| SDRAM_CFG_2T_EN
	107	#endif
bbea46f7	108	\| SDRAM_CFG_SDRAM_TYPE_DDR1;
91e25769 PG	109	#if defined (CONFIG_DDR_32BIT)
	110	/* for 32-bit mode burst length is 8 */
	111	im->ddr.sdram_cfg \|= (SDRAM_CFG_32_BE \| SDRAM_CFG_8_BE);
	112	#endif
6d0f6bcf	113	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
91e25769	114
6d0f6bcf	115	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
91e25769 PG	116	udelay(200);
	117
	118	/* enable DDR controller */
	119	im->ddr.sdram_cfg \|= SDRAM_CFG_MEM_EN;
	120	return msize;
	121	}
6d0f6bcf	122	#endif/!CONFIG_SYS_SPD_EEPROM/
91e25769 PG	123
	124
	125	int checkboard (void)
	126	{
	127	puts("Board: Wind River SBC834x\n");
	128	return 0;
	129	}
	130
	131	/*
	132	* if board is fitted with SDRAM
	133	*/
6d0f6bcf JCPV	134	#if defined(CONFIG_SYS_BR2_PRELIM) \
	135	&& defined(CONFIG_SYS_OR2_PRELIM) \
	136	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
	137	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
91e25769 PG	138	/*
	139	* Initialize SDRAM memory on the Local Bus.
	140	*/
	141
	142	void sdram_init(void)
	143	{
6d0f6bcf	144	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
f51cdaf1	145	volatile fsl_lbc_t *lbc = &immap->im_lbc;
6d0f6bcf	146	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
91e25769 PG	147
91e25769 PG	148	puts("\n SDRAM on Local Bus: ");
6d0f6bcf	149	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
91e25769 PG	150
	151	/*
	152	* Setup SDRAM Base and Option Registers, already done in cpu_init.c
	153	*/
	154
	155	/* setup mtrpt, lsrt and lbcr for LB bus */
6d0f6bcf JCPV	156	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	157	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	158	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
91e25769 PG	159	asm("sync");
	160
	161	/*
	162	* Configure the SDRAM controller Machine Mode Register.
	163	*/
6d0f6bcf	164	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
91e25769	165
6d0f6bcf	166	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
91e25769 PG	167	asm("sync");
	168	*sdram_addr = 0xff;
	169	udelay(100);
	170
6d0f6bcf	171	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
91e25769 PG	172	asm("sync");
	173	/1 times/
	174	*sdram_addr = 0xff;
	175	udelay(100);
	176	/2 times/
	177	*sdram_addr = 0xff;
	178	udelay(100);
	179	/3 times/
	180	*sdram_addr = 0xff;
	181	udelay(100);
	182	/4 times/
	183	*sdram_addr = 0xff;
	184	udelay(100);
	185	/5 times/
	186	*sdram_addr = 0xff;
	187	udelay(100);
	188	/6 times/
	189	*sdram_addr = 0xff;
	190	udelay(100);
	191	/7 times/
	192	*sdram_addr = 0xff;
	193	udelay(100);
	194	/8 times/
	195	*sdram_addr = 0xff;
	196	udelay(100);
	197
	198	/* 0x58636733; mode register write operation */
6d0f6bcf	199	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
91e25769 PG	200	asm("sync");
	201	*sdram_addr = 0xff;
	202	udelay(100);
	203
6d0f6bcf	204	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
91e25769 PG	205	asm("sync");
	206	*sdram_addr = 0xff;
	207	udelay(100);
	208	}
	209	#else
	210	void sdram_init(void)
	211	{
	212	puts(" SDRAM on Local Bus: Disabled in config\n");
	213	}
	214	#endif
	215
2408b3f2 PG	216	#if defined(CONFIG_OF_BOARD_SETUP)
2408b3f2 PG	217	void ft_board_setup(void blob, bd_t bd)
91e25769	218	{
2408b3f2 PG	219	ft_cpu_setup(blob, bd);
	220	#ifdef CONFIG_PCI
	221	ft_pci_setup(blob, bd);
	222	#endif
91e25769 PG	223	}
91e25769 PG	224	#endif