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1 | Intro: |
2 | ====== | |
9e3ed392 | 3 | |
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4 | The SBC8548 is a stand alone single board computer with a 1GHz |
5 | MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz | |
6 | memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, | |
7 | and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC | |
8 | ethernet connections. | |
9e3ed392 | 9 | |
a187559e | 10 | U-Boot Configuration: |
bd42bbb8 | 11 | ===================== |
9e3ed392 | 12 | |
a187559e | 13 | The following possible U-Boot configuration targets are available: |
9e3ed392 | 14 | |
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15 | 1) sbc8548_config |
16 | 2) sbc8548_PCI_33_config | |
17 | 3) sbc8548_PCI_66_config | |
18 | 4) sbc8548_PCI_33_PCIE_config | |
19 | 5) sbc8548_PCI_66_PCIE_config | |
9e3ed392 | 20 | |
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21 | Generally speaking, most people should choose to use #5. Details |
22 | of each choice are listed below. | |
9e3ed392 | 23 | |
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24 | Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot |
25 | will be left empty (M66EN high), and so the board will operate with | |
a187559e | 26 | a base clock of 66MHz. Note that you need both PCI enabled in U-Boot |
bd42bbb8 | 27 | and linux in order to have functional PCI under linux. |
9e3ed392 | 28 | |
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29 | The second enables PCI support and builds for a 33MHz clock rate. Note |
30 | that if a 33MHz 32bit card is inserted in the slot, then the whole board | |
31 | will clock down to a 33MHz base clock instead of the default 66MHz. This | |
32 | will change the baud clocks and mess up your serial console output if you | |
33 | were previously running at 66MHz. If you want to use a 33MHz PCI card, | |
34 | then you should build a U-Boot with a _PCI_33_ config and store this | |
35 | to flash prior to powering down the board and inserting the 33MHz PCI | |
36 | card. [The above discussion assumes that the SW2[1-4] has not been changed | |
37 | to reflect a different CCB:SYSCLK ratio] | |
38 | ||
39 | The third option builds PCI support in, and leaves the clocking at the | |
f5cdc117 | 40 | default 66MHz. Options four and five are just repeats of option two |
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41 | and three, but with PCI-e support enabled as well. |
42 | ||
43 | PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx | |
f5cdc117 | 44 | is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with |
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45 | a 33MHz PCI configuration is currently untested.) |
46 | ||
47 | => pci 0 | |
48 | Scanning PCI devices on bus 0 | |
f5cdc117 | 49 | BusDevFun VendorId DeviceId Device Class Sub-Class |
bd42bbb8 | 50 | _____________________________________________________________ |
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51 | 00.00.00 0x1057 0x0012 Processor 0x20 |
52 | 00.01.00 0x8086 0x1026 Network controller 0x00 | |
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53 | => pci 1 |
54 | Scanning PCI devices on bus 1 | |
f5cdc117 | 55 | BusDevFun VendorId DeviceId Device Class Sub-Class |
bd42bbb8 | 56 | _____________________________________________________________ |
f5cdc117 | 57 | 01.00.00 0x1957 0x0012 Processor 0x20 |
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58 | => pci 2 |
59 | Scanning PCI devices on bus 2 | |
f5cdc117 | 60 | BusDevFun VendorId DeviceId Device Class Sub-Class |
bd42bbb8 | 61 | _____________________________________________________________ |
f5cdc117 | 62 | 02.00.00 0x1148 0x9e00 Network controller 0x00 |
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63 | => |
64 | ||
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65 | Memory Size and using SPD: |
66 | ========================== | |
67 | ||
68 | The default configuration uses hard coded memory configuration settings | |
69 | for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD | |
70 | EEPROM data to read what memory is installed. | |
71 | ||
72 | There is a hardware errata, which causes the older local bus SDRAM | |
73 | SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so | |
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74 | that the SPD data can not be read reliably. You can test if your |
75 | board has the errata fix by running "i2c probe". If you see 0x53 | |
76 | as a valid device, it has been fixed. If you only see 0x50, 0x51 | |
77 | then your board does not have the fix. | |
78 | ||
79 | You can also visually inspect the board to see if this hardware | |
80 | fix has been applied: | |
81 | ||
82 | 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on | |
f5cdc117 | 83 | the back of the PCB behind the DDR SDRAM SODIMM connector. |
3e3262bd | 84 | 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad |
f5cdc117 WD |
85 | to R313 pin 2. Pin 2 for each resistor is the end of the |
86 | resistor closest to the CPU. | |
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87 | |
88 | Boards without the mod will have R314 and R313 in parallel, like "||". | |
89 | After the mod, they will be touching and form an "L" shape. | |
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90 | |
91 | If you want to upgrade to larger RAM size, you can simply enable | |
92 | #define CONFIG_SPD_EEPROM | |
93 | #define CONFIG_DDR_SPD | |
94 | in include/configs/sbc8548.h file. (The lines are already there | |
95 | but listed as #undef). | |
96 | ||
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97 | If you did the i2c test, and your board does not have the errata |
98 | fix, then you will have to physically remove the LBC 128MB DIMM | |
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99 | from the board's socket to resolve the above i2c address overlap |
100 | issue and allow SPD autodetection of RAM to work. | |
101 | ||
bd42bbb8 | 102 | |
a187559e | 103 | Updating U-Boot with U-Boot: |
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104 | ============================ |
105 | ||
a187559e | 106 | Note that versions of U-Boot up to and including 2009.08 had U-Boot stored |
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107 | at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from |
108 | 0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to | |
a187559e | 109 | update U-Boot with U-Boot and it uses the old address, you will render |
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110 | your board inoperable, and you will require JTAG recovery. |
111 | ||
112 | The following steps list how to update with the current address: | |
113 | ||
114 | tftp u-boot.bin | |
115 | md 200000 10 | |
116 | protect off all | |
117 | erase fffa0000 ffffffff | |
118 | cp.b 200000 fffa0000 60000 | |
119 | md fffa0000 10 | |
120 | protect on all | |
121 | ||
122 | The "md" steps in the above are just a precautionary step that allow | |
a187559e | 123 | you to confirm the U-Boot version that was downloaded, and then confirm |
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124 | that it was copied to flash. |
125 | ||
f0aec4ea | 126 | The above assumes that you are using the default board settings which |
a187559e | 127 | have U-Boot in the 8MB flash, tied to /CS0. |
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128 | |
129 | If you are running the default 8MB /CS0 settings but want to store an | |
130 | image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, | |
131 | (as a backup, etc) then the steps will become: | |
132 | ||
133 | tftp u-boot.bin | |
134 | md 200000 10 | |
135 | protect off all | |
136 | era eff00000 efffffff | |
137 | cp.b 200000 eff00000 100000 | |
138 | md eff00000 10 | |
139 | protect on all | |
140 | ||
141 | Finally, if you are running the alternate 64MB /CS0 settings and want | |
a187559e | 142 | to update the in-use U-Boot image, then (again with CONFIG_SYS_ALT_BOOT |
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143 | enabled) the steps will become: |
144 | ||
145 | tftp u-boot.bin | |
146 | md 200000 10 | |
147 | protect off all | |
148 | era fff00000 ffffffff | |
149 | cp.b 200000 fff00000 100000 | |
150 | md fff00000 10 | |
151 | protect on all | |
152 | ||
dd9ca98f | 153 | |
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154 | Hardware Reference: |
155 | =================== | |
156 | ||
157 | The following contains some summary information on hardware settings | |
a187559e | 158 | that are relevant to U-Boot, based on the board manual. For the |
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159 | most up to date and complete details of the board, please request the |
160 | reference manual ERG-00327-001.pdf from www.windriver.com | |
161 | ||
162 | Boot flash: | |
163 | intel V28F640Jx, 8192x8 (one device) at 0xff80_0000 | |
164 | ||
165 | Sodimm flash: | |
166 | intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 | |
3fd673cf PG |
167 | Note that this address reflects the default setting for |
168 | the JTAG debugging tools, but since the alignment is | |
a187559e | 169 | rather inconvenient, U-Boot puts it at 0xec00_0000. |
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170 | |
171 | ||
172 | Jumpers: | |
173 | ||
174 | Jumper Name ON OFF | |
175 | ---------------------------------------------------------------- | |
176 | JP12 CS0/CS6 swap see note[*] see note[*] | |
177 | ||
178 | JP13 SODIMM flash write OK writes disabled | |
179 | write prot. | |
180 | ||
181 | JP14 HRESET/TRST joined isolated | |
182 | ||
183 | JP15 PWR ON when AC pwr use S1 for on/off | |
184 | ||
185 | JP16 Demo LEDs lit not lit | |
186 | ||
187 | JP19 PCI mode PCI PCI-X | |
188 | ||
189 | ||
190 | [*]JP12, when jumpered parallel to the SODIMM, puts the boot flash | |
191 | onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 | |
192 | is jumpered parallel to the LBC-SDRAM, then /CS0 is for the | |
193 | SODIMM flash and /CS6 is for the boot flash. Note that in this | |
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194 | alternate setting, you also need to switch SW2.8 to ON. |
195 | See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting | |
a187559e | 196 | and boot U-Boot from the 64MB SODIMM |
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197 | |
198 | ||
199 | Switches: | |
200 | ||
201 | The defaults are marked with a * | |
202 | ||
203 | Name Desc. ON OFF | |
204 | ------------------------------------------------------------------ | |
205 | S1 Pwr toggle n/a n/a | |
206 | ||
207 | SW2.1 CFG_SYS_PLL0 1 0* | |
208 | SW2.2 CFG_SYS_PLL1 1* 0 | |
209 | SW2.3 CFG_SYS_PLL2 1* 0 | |
210 | SW2.4 CFG_SYS_PLL3 1 0* | |
211 | SW2.5 CFG_CORE_PLL0 1* 0 | |
212 | SW2.6 CFG_CORE_PLL1 1 0* | |
213 | SW2.7 CFG_CORE_PLL2 1* 0 | |
214 | SW2.8 CFG_ROM_LOC1 1 0* | |
215 | ||
216 | SW3.1 CFG_HOST_AGT0 1* 0 | |
217 | SW3.2 CFG_HOST_AGT1 1* 0 | |
218 | SW3.3 CFG_HOST_AGT2 1* 0 | |
219 | SW3.4 CFG_IO_PORTS0 1* 0 | |
220 | SW3.5 CFG_IO_PORTS0 1 0* | |
221 | SW3.6 CFG_IO_PORTS0 1 0* | |
222 | ||
223 | SerDes CLK(MHz) SW5.1 SW5.2 | |
224 | ---------------------------------------------- | |
225 | 25 0 0 | |
226 | 100* 1 0 | |
227 | 125 0 1 | |
228 | 200 1 1 | |
229 | ||
230 | SerDes CLK spread SW5.3 SW5.4 | |
231 | ---------------------------------------------- | |
232 | +/- 0.25% 0 0 | |
233 | -0.50% 1 0 | |
234 | -0.75% 0 1 | |
235 | No Spread* 1 1 | |
236 | ||
237 | SW4 settings are readable from the EPLD and are currently not used for | |
238 | any hardware settings (i.e. user configuration switches). | |
239 | ||
240 | LEDs: | |
241 | ||
242 | Name Desc. ON OFF | |
243 | ------------------------------------------------------------------ | |
244 | D13 PCI/PCI-X PCI-X PCI | |
245 | D14 3.3V PWR 3.3V no power | |
246 | D15 SYSCLK 66MHz 33MHz | |
247 | ||
248 | ||
249 | Default Memory Map: | |
250 | ||
251 | start end CS<n> width Desc. | |
252 | ---------------------------------------------------------------------- | |
253 | 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) | |
254 | f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) | |
255 | f800_0000 f8b0_1fff CS5 - EPLD | |
3fd673cf | 256 | fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*] |
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257 | ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) |
258 | ||
3fd673cf | 259 | [*] fb80 represents the default programmed by WR JTAG register files, |
a187559e | 260 | but U-Boot places the flash at either ec00 or fc00 based on JP12. |
3fd673cf | 261 | |
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262 | The EPLD on CS5 demuxes the following devices at the following offsets: |
263 | ||
264 | offset size width device | |
265 | -------------------------------------------------------- | |
266 | 0 1fff 8 7 segment display LED | |
267 | 10_0000 1fff 4 user switches | |
268 | 30_0000 1fff 4 HW Rev. register | |
269 | b0_0000 1fff 8 8kB EEPROM |